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Searched +full:ar9130 +full:- +full:pll (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqca,ath79-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qca,ath79-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros ATH79 PLL controller
10 - Alban Bedel <albeu@free.fr>
11 - Antony Pavlov <antonynpavlov@gmail.com>
14 The PLL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
19 - items:
20 - const: qca,ar9132-pll
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H A Dqca,ath79-pll.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
6 - compatible: has to be "qca,<soctype>-pll" and one of the following
8 - "qca,ar7100-pll"
9 - "qca,ar7240-pll"
10 - "qca,ar9130-pll"
11 - "qca,ar9330-pll"
12 - "qca,ar9340-pll"
13 - "qca,qca9550-pll"
14 - reg: Base address and size of the controllers memory area
15 - clock-names: Name of the input clock, has to be "ref"
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/freebsd/sys/contrib/device-tree/src/mips/qca/
H A Dar9132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
17 clocks = <&pll ATH79_CLK_CPU>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
25 interrupt-controller;
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dqca,ar71xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Oleksij Rempel <o.rempel@pengutronix.de>
18 - items:
19 - enum:
20 - qca,ar7100-eth # Atheros AR7100
21 - qca,ar7240-eth # Atheros AR7240
22 - qca,ar7241-eth # Atheros AR7241
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/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416phy.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
120 /* PLL settling times */
132 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
133 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-…
134 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz…
148 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */
222 /* This is AR9130 and later */
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H A Dar5416_reset.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
33 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
122 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); in ar5416Reset()
144 * Don't do this for the AR9285 - it breaks RX for single in ar5416Reset()
173 (ah->ah_config.ah_force_full_reset)) in ar5416Reset()
192 AH5416(ah)->ah_writeIni(ah, chan); in ar5416Reset()
230 * This routine swaps the analog chains - it should be done in ar5416Reset()
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/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9280_attach.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
81 .totalSizeDesired = { -55, -55, -55, -55, -62 }, in ar9280AniSetup()
82 .coarseHigh = { -14, -14, -14, -14, -12 }, in ar9280AniSetup()
83 .coarseLow = { -64, -64, -64, -64, -70 }, in ar9280AniSetup()
84 .firpwr = { -78, -78, -78, -78, -80 }, in ar9280AniSetup()
98 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); in ar9280AniSetup()
107 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); in ar9280InitPLL() local
112 * PLL WAR for Merlin 2.0/2.1 in ar9280InitPLL()
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