Searched full:tbus (Results 1 – 7 of 7) sorted by relevance
608 printf( "Bus:\t\tBus ID\tType\n" ); in MPConfigTableHeader()622 printf( "I/O Ints:\tType\tPolarity Trigger\tBus ID\t IRQ\tAPIC ID\tPIN#\n" ); in MPConfigTableHeader()629 printf( "Local Ints:\tType\tPolarity Trigger\tBus ID\t IRQ\tAPIC ID\tPIN#\n" ); in MPConfigTableHeader()
421 printf("\tBus: %d\n", msg->Bus); in mpt_print_scsi_io_reply()449 printf("\tBus: 0x%04x\n", in mpt_print_event_notice()536 printf("\tBus: %d\n", msg->Bus); in mpt_print_scsi_io_request()
641 ID each, but may master through multiple SMMU TBUs */
988 "\t\tbus:target:lun filename\n"); in usage()
338 /* Relative address of indirect TBUS address register (bits 0..7) */341 /* Relative address of indirect TBUS address register (bits 8..10) */344 /* Relative address of indirect TBUS data register (bits 0..7) */347 /* Relative address of indirect TBUS data register (bits 8..11) */3896 /* Dumps the tbus indirect memory for all PHYs. */4147 /* Dump PHY tbus */ in ecore_grc_dump()
12100 …N_K2_E5 (0x1<<7) // Clock gate enable for the TBUS debug output branch…12112 …G_EN_K2_E5 (0x1<<7) // Clock gate enable for the TBUS debug output branch…12140 …N_K2_E5 (0x1<<7) // Clock gate enable for the TBUS debug output branch…12152 …G_EN_K2_E5 (0x1<<7) // Clock gate enable for the TBUS debug output branch…12164 …N_K2_E5 (0x1<<7) // Clock gate enable for the TBUS debug output branch…12176 …G_EN_K2_E5 (0x1<<7) // Clock gate enable for the TBUS debug output branch…12383 …cess:RW DataWidth:0x8 // lower 8-bits of the 16-bit digital test bus tbus address. Decoding t…12384 …ess:RW DataWidth:0x8 // higher 8-bits of the 16-bit digital test bus tbus address. Decoding t…12388 … 0x0006c0UL //Access:R DataWidth:0x8 // Digital test bus tbus output bits [7:0]12390 … (0xf<<0) // Digital test bus tbus output bits [11:8][all …]
505 printf("\tBUS=%d\n", (u_int)over->Bus); in acpi_print_madt()716 printf("\tBus=%d\n", a->Bus); in acpi_print_hest_aer()