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/freebsd/sys/contrib/device-tree/Bindings/net/pcs/
H A Dsnps,dw-xpcs.yaml18 Synopsys PMA (also called DesignWare Consumer/Enterprise PHY) although in
28 - description: Synopsys DesignWare XPCS with none or unknown PMA
30 - description: Synopsys DesignWare XPCS with Consumer Gen1 3G PMA
32 - description: Synopsys DesignWare XPCS with Consumer Gen2 3G PMA
34 - description: Synopsys DesignWare XPCS with Consumer Gen2 6G PMA
36 - description: Synopsys DesignWare XPCS with Consumer Gen4 3G PMA
38 - description: Synopsys DesignWare XPCS with Consumer Gen4 6G PMA
40 - description: Synopsys DesignWare XPCS with Consumer Gen5 10G PMA
42 - description: Synopsys DesignWare XPCS with Consumer Gen5 12G PMA
83 PCS/PMA layer can be clocked by an internal reference clock source
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dxilinx_axienet.txt30 this to the PCS/PMA PHY is deprecated and should be avoided.
52 PCS/PMA PHY)
74 - pcs-handle: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
76 to the PCS/PMA PHY, and "phy-handle" should point to an
H A Dxlnx,axi-ethernet.yaml101 - description: MGT reference clock (used by optional internal PCS/PMA PHY)
121 description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
122 modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_interface.h120 * Parallel loopback from the PMA receive lane data ports, to the
129 /** Loops TX data (to PMA) to RX path (instead of PMA data) */
463 * @param type The SERDES register type (PMA /PCS)
477 * @param type The SERDES register type (PMA /PCS)
580 * SERDES group PMA hard reset
581 * Controls Serdes group PMA hard reset
589 * SERDES lane PMA hard reset
590 * Controls Serdes lane PMA hard reset
H A Dal_hal_serdes_hssp_internal_regs.h120 * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
128 * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
136 * PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to
145 * PMA Parallel RX-to-TX loop-back enable. Parallel loopback from the PMA
154 * PMA CDR recovered-clock loopback enable; asserted when PARRX2TXTIMEDEN is 1.
478 * Common lane register fields - PMA
H A Dal_hal_serdes_internal_regs.h121 * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
129 * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
137 * PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to
146 * PMA Parallel RX-to-TX loop-back enable. Parallel loopback from the PMA
155 * PMA CDR recovered-clock loopback enable; asserted when PARRX2TXTIMEDEN is 1.
479 * Common lane register fields - PMA
H A Dal_hal_serdes_hssp.c1033 * Disable the Rx rate change software flow by clearing bit 7 of lane PMA register 205 in _al_serdes_lane_rx_rate_change_sw_flow_dis()
1119 * Enable the Rx rate change software flow by setting bit 7 of lane PMA register 205 in _al_serdes_lane_rx_rate_change_sw_flow_en_cond()
2550 * AGC/DFE controlled via PMA registers in al_serdes_rx_equalization()
2591 * to override RxEQ via PMA in al_serdes_rx_equalization()
2764 * to override RxEQ via PMA in al_serdes_calc_eye_size()
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dsamsung,ufs-phy.yaml28 - const: phy-pma
102 reg-names = "phy-pma";
H A Dti,phy-j721e-wiz.yaml79 clock source for the reference clock used in the PHY and PMA digital
147 WIZ node should have subnodes for each of the PMA common refclock
H A Dcdns,dphy.yaml23 - description: PMA state machine clock
H A Dsamsung,usb3-drd-phy.yaml69 - const: pma
/freebsd/sys/riscv/include/
H A Dpte.h92 * | PMA | 00 | None, inherited from Physical Memory Attributes (firmware) |
119 * | PMA | 01110 | Weakly-ordered, cacheable, bufferable, shareable, |
/freebsd/crypto/openssl/test/recipes/04-test_pem_reading_data/
H A Ddsa-threecolumn.pem99 PmA
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dcdns,mhdp8546.yaml24 The AUX and PMA registers are not part of this range, they are instead
/freebsd/sys/ofed/include/rdma/
H A Dib_pma.h43 * PMA class portinfo capability mask bits
/freebsd/sys/dev/xilinx/
H A Dif_xaereg.h48 #define XAE_PPST 0x00030 /* PCS PMA Status register RO */
/freebsd/contrib/ofed/infiniband-diags/man/
H A Dperfquery.842 PortSamplesControl from the PMA at the node/port specified. Optionally shows
/freebsd/sys/arm64/rockchip/
H A Drk3568_pciephy.c222 /* Deassert PCIe PMA output clamp mode */ in rk3568_pciephy_attach()
H A Drk_typec_phy.c278 device_printf(sc->dev, "Timeout waiting for PMA\n"); in rk_typec_phy_enable()
/freebsd/sys/dev/mthca/
H A Dmthca_mad.c227 * Only handle PMA and Mellanox vendor-specific class gets and in mthca_process_mad()
/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h11186 …_E5 (0x3<<0) // FEC lane mapped to PMA lane 0.
11188 …_E5 (0x3<<2) // FEC lane mapped to PMA lane 1.
11190 …_E5 (0x3<<4) // FEC lane mapped to PMA lane 2.
11192 …_E5 (0x3<<6) // FEC lane mapped to PMA lane 3.
11224 …OCK_K2_E5 (0xf<<0) // Per PMA lane FEC synchroniz…
11243 …OCK_K2_E5 (0xf<<0) // Per PMA lane FEC synchroniz…
11445 …MD_PMA_K2_E5 (0x1<<1) // PMD/PMA present when 1.
11622 …//Access:RW DataWidth:0x20 // Vendor Specific Reg; Define Reduced-XLAUI PMA mode using 2 lanes.
11623 … (0x1<<0) // Enable Reduced-XLAUI PMA mode using 2 lanes.
11720 …MD_PMA_K2_E5 (0x1<<1) // PMD/PMA present when 1.
[all …]
/freebsd/sys/dev/mxge/
H A Dmxge_mcp.h365 /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
/freebsd/sys/contrib/device-tree/src/arm64/exynos/google/
H A Dgs101.dtsi1273 reg-names = "phy", "pcs", "pma";
1372 reg-names = "phy-pma";
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynosautov9.dtsi1545 reg-names = "phy-pma";
1577 reg-names = "phy-pma";
H A Dexynos7.dtsi669 reg-names = "phy-pma";

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