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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include "phy-qcom-qmp-qserdes-com.h"
10 #include "phy-qcom-qmp-qserdes-txrx.h"
12 #include "phy-qcom-qmp-qserdes-com-v3.h"
13 #include "phy-qcom-qmp-qserdes-txrx-v3.h"
15 #include "phy-qcom-qmp-qserdes-com-v4.h"
16 #include "phy-qcom-qmp-qserdes-txrx-v4.h"
17 #include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
19 #include "phy-qcom-qmp-qserdes-com-v5.h"
20 #include "phy-qcom-qmp-qserdes-txrx-v5.h"
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H A Dphy-qcom-qmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
24 #include "phy-qcom-qmp-common.h"
26 #include "phy-qcom-qmp.h"
27 #include "phy-qcom-qmp-pcs-ufs-v2.h"
28 #include "phy-qcom-qmp-pcs-ufs-v3.h"
29 #include "phy-qcom-qmp-pcs-ufs-v4.h"
30 #include "phy-qcom-qmp-pcs-ufs-v5.h"
31 #include "phy-qcom-qmp-pcs-ufs-v6.h"
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H A Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
36 /* set of registers with offsets different per-PHY */
43 /* PCS registers */
139 /* struct qmp_phy_cfg - per-PHY initialization config */
144 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
169 * struct qmp_phy - per-lane phy descriptor
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H A Dphy-qcom-qmp-usb-legacy.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include <linux/phy/phy.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
28 #include "phy-qcom-qmp-dp-com-v3.h"
31 /* DP PHY soft reset */
33 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
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H A Dphy-qcom-qmp-usb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
25 #include "phy-qcom-qmp-pcs-misc-v3.h"
26 #include "phy-qcom-qmp-pcs-misc-v4.h"
27 #include "phy-qcom-qmp-pcs-usb-v4.h"
28 #include "phy-qcom-qmp-pcs-usb-v5.h"
29 #include "phy-qcom-qmp-pcs-usb-v6.h"
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H A Dphy-qcom-qmp-pcie.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include <linux/phy/pcie.h>
18 #include <linux/phy/phy.h>
25 #include <dt-bindings/phy/phy-qcom-qmp.h>
27 #include "phy-qcom-qmp-common.h"
29 #include "phy-qcom-qmp.h"
30 #include "phy-qcom-qmp-pcs-misc-v3.h"
31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
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/linux/drivers/net/phy/
H A Dphylink.c1 // SPDX-License-Identifier: GPL-2.0
3 * phylink models the MAC to optional PHY connection, supporting
4 * technologies such as SFP cages where the PHY is hot-pluggable.
15 #include <linux/phy.h>
23 #include "phy-caps.h"
38 * struct phylink - internal data type for phylink
45 struct phylink_pcs *pcs; member
55 u8 link_port; /* The current non-phy ethtool port */
70 /* Serialize updates to pl->phydev with phylink_resolve() */
100 if ((pl)->config->type == PHYLINK_NETDEV) \
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/linux/arch/arm64/boot/dts/freescale/
H A Dtqmls1088a-mbls10xxa-mc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
10 #include <dt-bindings/net/ti-dp83867.h>
17 pcs-handle = <&pcs1>;
21 pcs-handle = <&pcs2>;
25 pcs-handle = <&pcs3_0>;
29 pcs-handle = <&pcs3_1>;
33 pcs-handle = <&pcs3_2>;
37 pcs-handle = <&pcs3_3>;
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H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
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H A Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
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/linux/include/linux/
H A Dphylink.h4 #include <linux/phy.h>
23 MLO_AN_PHY = 0, /* Conventional PHY */
24 MLO_AN_FIXED, /* Fixed-link mode */
25 MLO_AN_INBAND, /* In-band protocol */
27 /* PCS "negotiation" mode.
28 * PHYLINK_PCS_NEG_NONE - protocol has no inband capability
29 * PHYLINK_PCS_NEG_OUTBAND - some out of band or fixed link setting
30 * PHYLINK_PCS_NEG_INBAND_DISABLED - inband mode disabled, e.g.
31 * 1000base-X with autoneg off
32 * PHYLINK_PCS_NEG_INBAND_ENABLED - inban
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/linux/Documentation/networking/
H A Dsfp-phylink.rst1 .. SPDX-License-Identifier: GPL-2.0
10 phylink is a mechanism to support hot-pluggable networking modules
11 directly connected to a MAC without needing to re-initialise the
12 adapter on hot-plug events.
14 phylink supports conventional phylib-based setups, fixed link setups
23 1. PHY mode
25 In PHY mode, we use phylib to read the current link settings from
26 the PHY, and pass them to the MAC driver. We expect the MAC driver
32 Fixed mode is the same as PHY mode as far as the MAC driver is
35 3. In-band mode
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/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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H A Dfsl,fman-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The MDIO is a bus to which the PHY devices are connected.
18 - fsl,fman-mdio
19 - fsl,fman-xmdio
20 - fsl,fman-memac-mdio
22 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
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H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
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H A Dfsl,qoriq-mc-dpmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
14 located under the 'dpmacs' node for the fsl-mc bus DTS node.
17 - $ref: ethernet-controller.yaml#
21 const: fsl,qoriq-mc-dpmac
27 pcs-handle:
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/linux/drivers/net/dsa/sja1105/
H A Dsja1105_mdio.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/pcs/pcs-xpcs.h>
10 int sja1105_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg) in sja1105_pcs_mdio_read_c45() argument
12 struct sja1105_mdio_private *mdio_priv = bus->priv; in sja1105_pcs_mdio_read_c45()
13 struct sja1105_private *priv = mdio_priv->priv; in sja1105_pcs_mdio_read_c45()
35 int sja1105_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, in sja1105_pcs_mdio_write_c45() argument
38 struct sja1105_mdio_private *mdio_priv = bus->priv; in sja1105_pcs_mdio_write_c45()
39 struct sja1105_private *priv = mdio_priv->priv; in sja1105_pcs_mdio_write_c45()
47 return -EINVAL; in sja1105_pcs_mdio_write_c45()
52 int sja1110_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg) in sja1110_pcs_mdio_read_c45() argument
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/linux/drivers/net/fddi/skfp/
H A Dpcmplc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
67 #define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
68 #define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
109 * PCL-S control register
110 * this register in the PLC-S controls the scrambling parameters
121 * PCL-S control register
122 * this register in the PLC-S controls the scrambling parameters
152 #define PLC_MS(m) ((int)((0x10000L-(m*100000L/2048))))
191 static void pcm_fsm(struct s_smc *smc, struct s_phy *phy, int cmd);
192 static void pc_rcode_actions(struct s_smc *smc, int bit, struct s_phy *phy);
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/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6352 family SERDES PCS support
16 #include "phy.h"
36 err = mdiodev_c45_read(&mpcs->mdio, MDIO_MMD_PHYXS, regnum); in mv88e639x_read()
47 return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, val); in mv88e639x_write()
53 return mdiodev_c45_modify(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, mask, in mv88e639x_modify()
60 return mdiodev_c45_modify_changed(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, in mv88e639x_modify_changed()
74 mpcs->mdio.dev.parent = dev; in mv88e639x_pcs_alloc()
75 mpcs->mdio.bus = bus; in mv88e639x_pcs_alloc()
76 mpcs->mdio.addr = addr; in mv88e639x_pcs_alloc()
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/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
13 set PCS delay value.
14 e.g. PCIE PHY in DRA7x
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/linux/drivers/net/dsa/b53/
H A Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Northstar Plus switch SerDes/SGMII PHY main logic
12 #include <linux/phy.h>
20 static inline struct b53_pcs *pcs_to_b53_pcs(struct phylink_pcs *pcs) in pcs_to_b53_pcs() argument
22 return container_of(pcs, struct b53_pcs, pcs); in pcs_to_b53_pcs()
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
68 static int b53_serdes_config(struct phylink_pcs *pcs, unsigned int neg_mode, in b53_serdes_config() argument
73 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_config()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config()
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/linux/Documentation/devicetree/bindings/net/dsa/
H A Drenesas,rzn1-a5psw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clément Léger <clement.leger@bootlin.com>
17 - $ref: dsa.yaml#/$defs/ethernet-ports
22 - enum:
23 - renesas,r9a06g032-a5psw
24 - const: renesas,rzn1-a5psw
31 - description: Device Level Ring (DLR) interrupt
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/linux/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
H A Dmac-phy-support.rst1 .. SPDX-License-Identifier: GPL-2.0
5 DPAA2 MAC / PHY support
11 --------
13 The DPAA2 MAC / PHY support consists of a set of APIs that help DPAA2 network
14 drivers (dpaa2-eth, dpaa2-ethsw) interact with the PHY library.
17 ---------------------------
19 Among other DPAA2 objects, the fsl-mc bus exports DPNI objects (abstracting a
20 network interface) and DPMAC objects (abstracting a MAC). The dpaa2-eth driver
26 directly by the dpaa2-eth driver or by phylink.
28 .. code-block:: none
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/linux/Documentation/devicetree/bindings/net/pcs/
H A Dsnps,dw-xpcs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Ethernet PCS
10 - Serge Semin <fancer.lancer@gmail.com>
16 controlled by means of the IEEE std. Clause 45 registers set. The PCS can be
17 optionally synthesized with a vendor-specific interface connected to
18 Synopsys PMA (also called DesignWare Consumer/Enterprise PHY) although in
19 general it can be used to communicate with any compatible PHY.
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/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-sgmii.c7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
35 #include <asm/octeon/cvmx-config.h>
37 #include <asm/octeon/cvmx-helper.h>
38 #include <asm/octeon/cvmx-helper-board.h>
40 #include <asm/octeon/cvmx-gmxx-defs.h>
41 #include <asm/octeon/cvmx-pcsx-defs.h>
42 #include <asm/octeon/cvmx-pcsxx-defs.h>
54 const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000; in __cvmx_helper_sgmii_hardware_init_one_time()
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