/linux/arch/parisc/kernel/ |
H A D | unaligned.c | 375 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; in handle_unaligned() 390 " at ip " RFMT " (iir " RFMT ")\n", in handle_unaligned() 392 regs->iaoq[0], regs->iir); in handle_unaligned() 406 "(iir " RFMT ")\n", in handle_unaligned() 407 regs->ior, (void *)regs->iaoq[0], regs->iir); in handle_unaligned() 411 switch (MAJOR_OP(regs->iir)) in handle_unaligned() 416 if (regs->iir&0x20) in handle_unaligned() 419 if (regs->iir&0x1000) /* short loads */ in handle_unaligned() 420 if (regs->iir&0x200) in handle_unaligned() 421 newbase += IM5_3(regs->iir); in handle_unaligned() [all …]
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H A D | kgdb.c | 82 gr->iir = regs->iir; in pt_regs_to_gdb_regs() 113 regs->iir = gr->iir; in gdb_regs_to_pt_regs() 190 else if (trap == 9 && regs->iir == in kgdb_arch_handle_exception() 198 } else if (trap == 9 && regs->iir == in kgdb_arch_handle_exception()
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H A D | toc.c | 36 regs->iir = (unsigned long)toc->cr[19]; in toc20_to_pt_regs() 59 regs->iir = toc->cr[19]; in toc11_to_pt_regs()
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/linux/drivers/gpu/drm/i915/gt/ |
H A D | intel_gt_irq.c | 21 static void guc_irq_handler(struct intel_guc *guc, u16 iir) in guc_irq_handler() argument 26 if (iir & GUC_INTR_GUC2HOST) in guc_irq_handler() 66 const u16 iir) in gen11_other_irq_handler() argument 71 return guc_irq_handler(gt_to_guc(gt), iir); in gen11_other_irq_handler() 73 return guc_irq_handler(gt_to_guc(media_gt), iir); in gen11_other_irq_handler() 76 return gen11_rps_irq_handler(>->rps, iir); in gen11_other_irq_handler() 78 return gen11_rps_irq_handler(&media_gt->rps, iir); in gen11_other_irq_handler() 81 return intel_pxp_irq_handler(gt->i915->pxp, iir); in gen11_other_irq_handler() 84 return intel_gsc_irq_handler(gt, iir); in gen11_other_irq_handler() 87 return intel_gsc_proxy_irq_handler(>->uc.gsc, iir); in gen11_other_irq_handler() [all …]
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H A D | intel_gt_irq.h | 44 static inline void intel_engine_cs_irq(struct intel_engine_cs *engine, u16 iir) in intel_engine_cs_irq() argument 46 if (iir) in intel_engine_cs_irq() 47 engine->irq_handler(engine, iir); in intel_engine_cs_irq() 53 u16 iir)) in intel_engine_set_irq_handler() argument
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H A D | intel_gsc.c | 292 void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir) in intel_gsc_irq_handler() argument 294 if (iir & GSC_IRQ_INTF(0)) in intel_gsc_irq_handler() 296 if (iir & GSC_IRQ_INTF(1)) in intel_gsc_irq_handler()
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/linux/drivers/media/platform/ti/omap3isp/ |
H A D | isph3a_af.c | 71 isp_reg_writel(af->isp, conf->iir.h_start, in h3a_af_setup_regs() 77 /*Set IIR Filter0 Coefficients */ in h3a_af_setup_regs() 79 coef |= conf->iir.coeff_set0[index]; in h3a_af_setup_regs() 80 coef |= conf->iir.coeff_set0[index + 1] << in h3a_af_setup_regs() 86 /*Set IIR Filter1 Coefficients */ in h3a_af_setup_regs() 88 coef |= conf->iir.coeff_set1[index]; in h3a_af_setup_regs() 89 coef |= conf->iir.coeff_set1[index + 1] << in h3a_af_setup_regs() 96 isp_reg_writel(af->isp, conf->iir.coeff_set0[10], in h3a_af_setup_regs() 99 isp_reg_writel(af->isp, conf->iir.coeff_set1[10], in h3a_af_setup_regs() 157 struct omap3isp_h3a_af_iir *iir_cfg = &user_cfg->iir; in h3a_af_validate_params() [all …]
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/linux/drivers/gpu/drm/xe/display/ext/ |
H A D | i915_irq.c | 11 i915_reg_t iir, i915_reg_t ier) in gen3_irq_reset() argument 18 /* IIR can theoretically queue up two events. Be paranoid. */ in gen3_irq_reset() 19 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset() 20 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset() 21 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset() 22 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset() 48 i915_reg_t iir) in gen3_irq_init() argument 50 gen3_assert_iir_is_zero(uncore, iir); in gen3_irq_init()
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/linux/drivers/gpu/drm/i915/pxp/ |
H A D | intel_pxp_irq.c | 23 * @iir: interrupt vector 25 void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) in intel_pxp_irq_handler() argument 36 if (unlikely(!iir)) in intel_pxp_irq_handler() 39 if (iir & (GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT | in intel_pxp_irq_handler() 47 if (iir & GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT) in intel_pxp_irq_handler()
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H A D | intel_pxp_irq.h | 25 void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir); 27 static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) in intel_pxp_irq_handler() argument
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/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_display_irq.h | 55 void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir); 73 void i9xx_pipestat_irq_ack(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); 75 void i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPE… 76 void i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPE… 78 void i8xx_pipestat_irq_handler(struct drm_i915_private *i915, u16 iir, u32 pipe_stats[I915_MAX_PIPE…
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H A D | intel_hotplug_irq.h | 19 void gen11_hpd_irq_handler(struct drm_i915_private *i915, u32 iir); 21 void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir);
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/linux/drivers/gpu/drm/i915/ |
H A D | i915_irq.h | 46 i915_reg_t iir, i915_reg_t ier); 51 i915_reg_t iir); 61 gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER) 76 type##IIR)
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/linux/sound/soc/codecs/ |
H A D | wcd934x.c | 230 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \ 231 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \ 232 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \ 233 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \ 234 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \ 235 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \ 236 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \ 237 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \ 238 {"IIR" #i [all...] |
/linux/drivers/tty/serial/8250/ |
H A D | 8250_fsl.c | 30 unsigned int iir; in fsl8250_handle_irq() local 35 iir = port->serial_in(port, UART_IIR); in fsl8250_handle_irq() 36 if (iir & UART_IIR_NO_INT) { in fsl8250_handle_irq() 54 if (unlikely((iir & UART_IIR_ID) == UART_IIR_RLSI && in fsl8250_handle_irq()
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/linux/drivers/gpu/drm/i915/gvt/ |
H A D | interrupt.c | 61 #define iir_to_regbase(iir) (iir - 0x8) argument 290 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler 296 * This function is used to emulate the generic IIR register behavior. 308 u32 iir = *(u32 *)p_data; in intel_vgpu_reg_iir_handler() local 310 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg), in intel_vgpu_reg_iir_handler() 311 (vgpu_vreg(vgpu, reg) ^ iir)); in intel_vgpu_reg_iir_handler() 316 vgpu_vreg(vgpu, reg) &= ~iir; in intel_vgpu_reg_iir_handler() 385 u32 iir = regbase_to_iir( in update_upstream_irq() local 390 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr)); in update_upstream_irq()
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/linux/drivers/bluetooth/ |
H A D | dtl1_cs.c | 295 int iir, lsr; in dtl1_interrupt() local 306 iir = inb(iobase + UART_IIR) & UART_IIR_ID; in dtl1_interrupt() 307 while (iir) { in dtl1_interrupt() 313 switch (iir) { in dtl1_interrupt() 328 BT_ERR("Unhandled IIR=%#x", iir); in dtl1_interrupt() 336 iir = inb(iobase + UART_IIR) & UART_IIR_ID; in dtl1_interrupt()
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/linux/arch/sh/include/asm/ |
H A D | smc37c93x.h | 74 volatile __u16 iir; member 86 #define tcr iir 92 #define fcr iir
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/linux/drivers/net/hamradio/ |
H A D | baycom_ser_fdx.c | 95 #define IIR(iobase) (iobase+2) macro 252 unsigned char iir, msr; in ser12_interrupt() local 258 if ((iir = inb(IIR(dev->base_addr))) & 1) in ser12_interrupt() 267 switch (iir & 6) { in ser12_interrupt() 302 iir = inb(IIR(dev->base_addr)); in ser12_interrupt() 303 } while (!(iir & 1)); in ser12_interrupt() 360 u = uart_tab[(inb(IIR(iobase)) >> 6) & 3]; in ser12_check_uart()
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H A D | baycom_ser_hdx.c | 81 #define IIR(iobase) (iobase+2) macro 366 unsigned char iir; in ser12_interrupt() local 371 if ((iir = inb(IIR(dev->base_addr))) & 1) in ser12_interrupt() 375 switch (iir & 6) { in ser12_interrupt() 401 iir = inb(IIR(dev->base_addr)); in ser12_interrupt() 402 } while (!(iir & 1)); in ser12_interrupt() 442 u = uart_tab[(inb(IIR(iobase)) >> 6) & 3]; in ser12_check_uart()
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/linux/arch/parisc/include/uapi/asm/ |
H A D | ptrace.h | 36 unsigned long iir; /* CR19 */ member 57 unsigned long iir; /* CR19 */ member
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/linux/drivers/iio/temperature/ |
H A D | mlx90614.c | 46 #define MLX90614_CONFIG_IIR_SHIFT 0 /* IIR coefficient */ 53 #define MLX90615_CONFIG_IIR_SHIFT 12 /* IIR coefficient */ 146 * Find the IIR value inside iir_values array and return its position 320 /* IIR setting with FIR=1024 (MLX90614) or FIR=65536 (MLX90615) */ in mlx90614_read_raw() 372 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: /* IIR Filter setting */ in mlx90614_write_raw() 691 /* IIR value 0 is FORBIDDEN COMBINATION on MLX90615 */
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/linux/arch/parisc/mm/ |
H A D | fault.c | 165 if (parisc_acctyp(0, regs->iir) == VM_READ) { in fixup_exception() 166 int treg = regs->iir & 0x1f; in fixup_exception() 289 acc_type = parisc_acctyp(code, regs->iir); in do_page_fault() 455 unsigned long insn = regs->iir; in handle_nadtlb_fault()
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/linux/drivers/gpu/drm/xe/ |
H A D | xe_heci_gsc.c | 218 void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir) in xe_heci_gsc_irq_handler() 222 if ((iir & GSC_IRQ_INTF(1)) == 0) in xe_heci_gsc_irq_handler() 238 void xe_heci_csc_irq_handler(struct xe_device *xe, u32 iir) 242 if ((iir & CSC_IRQ_INTF(1)) == 0) 216 xe_heci_gsc_irq_handler(struct xe_device * xe,u32 iir) xe_heci_gsc_irq_handler() argument
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/linux/drivers/gpu/drm/i915/gt/uc/ |
H A D | intel_gsc_proxy.h | 16 void intel_gsc_proxy_irq_handler(struct intel_gsc_uc *gsc, u32 iir);
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