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/freebsd/share/man/man4/
H A Dspigen.436 .Bd -ragged -offset indent
45 .Bd -literal -offset indent
54 device is associated with a single chip-select
56 with that chip-select line asserted.
58 SPI data transfers are inherently bi-directional; there are no separate
75 .Bl -tag -width indent
76 .It Dv SPIGENIOC_TRANSFER Pq Vt "struct spigen_transfer"
83 .Bd -literal
89 .It Dv SPIGENIOC_TRANSFER_MMAPPED Pq Vt "spigen_transfer_mmapped"
91 The buffers for the transfer are a previously-mmap'd region.
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H A Dvt.41 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
32 .Nm vt
43 .Cd "device vt"
49 .Cd kern.vty=vt
50 .Cd kern.vt.color.<colornum>.rgb="<colorspec>"
51 .Cd kern.vt.fb.default_mode="<X>x<Y>"
52 .Cd kern.vt.fb.modes.<connector>="<X>x<Y>"
53 .Cd kern.vt.slow_down=<delay>"
60 .Cd kern.vt.kbd_halt=1
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
43 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
58 // Floating-point comparisons. The two operands are the values to compare.
69 // operand 1 is the 4-bit condition-code mask, with bit N in
70 // big-endian order meaning "branch if CC=N"; operand 2 is the
75 // mask of condition-code values for which operand 0 should be
81 // base of the dynamically-allocatable area.
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H A DSystemZISelLowering.cpp1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
35 #define DEBUG_TYPE "systemz-lower"
47 // Chain if this is a strict floating-point comparison.
64 // Classify VT as either 32 or 64 bit.
65 static bool is32Bit(EVT VT) { in is32Bit() argument
66 switch (VT.getSimpleVT().SimpleTy) { in is32Bit()
127 setStackPointerRegisterToSaveRestore(Regs->getStackPointerRegister()); in SystemZTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
18 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "legalize-types"
33 //===----------------------------------------------------------------------===//
35 //===----------------------------------------------------------------------===//
37 /// PromoteIntegerResult - This method is called when a result of a node is
42 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG)); in PromoteIntegerResult()
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H A DLegalizeVectorTypes.cpp1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // Scalarization is the act of changing a computation in an illegal one-element
20 //===----------------------------------------------------------------------===//
35 #define DEBUG_TYPE "legalize-types"
37 //===----------------------------------------------------------------------===//
38 // Result Vector Scalarization: <1 x ty> -> ty.
39 //===----------------------------------------------------------------------===//
43 N->dump(&DAG)); in ScalarizeVectorResult()
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
42 #define DEBUG_TYPE "xcore-lower"
118 // Conversion of i64 -> double produces constantpool nodes in XCoreTargetLowering()
122 for (MVT VT : MVT::integer_valuetypes()) { in XCoreTargetLowering() local
123 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
124 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
125 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
128 bool MemcpyStrSrc; // Indicates whether the memcpy source is an in-register
193 /// This base class for TargetLowering contains the SelectionDAG-independent
215 TypeScalarizeVector, // Replace this one-element vector with its element.
224 // vector, this is non-trivial at SelectionDAG
230 /// in order to type-legalize it.
256 // floating-point to integer type.
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H A DSelectionDAG.h1 //===- llvm/CodeGen/SelectionDAG.h - InstSelection DAG ----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
114 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
115 FastID(ID), VTs(VT), NumVTs(Num) {
179 /// it from the Node-to-DbgValues map.
199 return I->second;
216 /// This is used to represent a portion of an LLVM function in a low-level
222 /// The representation used by the SelectionDAG is a target-independent
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrSIMD.td1 // WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// WebAssembly SIMD operand code-gen constructs.
12 //===----------------------------------------------------------------------===//
29 string asmstr_s = "", bits<32> simdop = -1,
37 string asmstr_s = "", bits<32> simdop = -1> {
44 string asmstr_s = "", bits<32> simdop = -1> {
62 // -2^(n-1) <= Imm < 2^n
63 "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << "#SIZE#");"
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/freebsd/share/man/man3/
H A Dsiginfo.354 .Bl -column ".Vt union signal" ".Va si_overrun"
56 .It Vt int Ta Va si_signo Ta
58 .It Vt int Ta Va si_errno Ta
60 .It Vt int Ta Va si_code Ta
62 .It Vt union sigval Ta Va si_value Ta
64 .It Vt pid_t Ta Va si_pid Ta
66 .It Vt uid_t Ta Va si_uid Ta
68 .It Vt void Ta Va *si_addr Ta
70 .It Vt int Ta Va si_status Ta
72 .It Vt long Ta Va si_band Ta
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
60 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
62 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
64 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
71 CALL_NOLINK, // Function call with branch not branch-and-link.
72 tSECALL, // CMSE non-secure function call.
76 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
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/freebsd/sys/x86/iommu/
H A Dintel_intrmap.c1 /*-
77 if (unit == NULL || !unit->ir_enabled) { in dmar_alloc_msi_intr()
79 cookies[i] = -1; in dmar_alloc_msi_intr()
83 error = vmem_alloc(unit->irtids, count, M_FIRSTFIT | M_NOWAIT, in dmar_alloc_msi_intr()
110 * See VT-d specification, 5.1.6 Remapping Hardware - in dmar_map_msi_intr()
121 if (unit == NULL || !unit->ir_enabled || cookie == -1) in dmar_map_msi_intr()
132 * See VT-d specification, 5.1.5.2 MSI and MSI-X in dmar_map_msi_intr()
147 if (cookie == -1) in dmar_unmap_msi_intr()
165 if (unit == NULL || !unit->ir_enabled) { in dmar_map_ioapic_intr()
166 *cookie = -1; in dmar_map_ioapic_intr()
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/freebsd/share/man/man5/
H A Dmake.conf.534 contains system-wide settings that will apply to every build using
71 if the system-wide settings are not suitable for a particular build.
130 .Bl -tag -width Ar
132 .Pq Vt bool
133 Instructs the top-level makefile in the source tree (normally
137 is up-to-date.
142 .Pq Vt str
150 .Pq Vt str
153 This controls processor-specific optimizations in
172 .Pq Vt str
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H A Drc.conf.593 to store jail-specific configuration options.
120 .Bl -tag -width indent-two
122 .Pq Vt bool
131 .Pq Vt bool
139 .Pq Vt bool
146 .Pq Vt str
181 .Pq Vt bool
194 .Pq Vt str
198 .Pq Vt str
206 .Pq Vt int
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h1 //===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that RISC-V uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
30 // clang-format off
37 /// Select with condition operator - This selects between a true value and
57 // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
60 // Multiply high for signedxunsigned.
68 // RV64I shifts, directly matching the semantics of the named RISC-V
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
65 // Get the Highest (63-48) 16 bits from a 64-bit immediate
68 // Get the Higher (47-32) 16 bits from a 64-bit immediate
71 // Get the High 16 bits from a 32/64-bit immediate
75 // Get the Lower 16 bits from a 32/64-bit immediate
79 // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
82 // Get the High 16 bits from a 32-bit immediate for accessing TLS.
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/freebsd/sbin/conscontrol/
H A Dconscontrol.81 .\"-
2 .\" SPDX-License-Identifer: BSD-2-Clause
56 There are two types of logical consoles; a high level console which
65 while the high level console is used by user programs like
68 the high level console is set to the first device in the console list.
77 .Bl -tag -widt
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "aarch64-isel"
34 //===--------------------------------------------------------------------===//
35 /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine
42 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
60 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
66 template <signed Low, signed High, signed Scale>
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
71 #define DEBUG_TYPE "x86-isel"
74 "x86-experimental-pref-innermost-loop-alignment", cl::init(4),
78 "alignment set by x86-experimental-pref-loop-alignment."),
82 "x86-br-merging-base-cost", cl::init(2),
88 "will be merged, and above which conditionals will be split. Set to -1 "
93 "x86-br-merging-ccmp-bias", cl::init(6),
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H A DX86ISelLowering.h1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
62 /// #0 - The incoming token chain
63 /// #1 - The callee
64 /// #2 - The number of arg bytes the caller pushes on the stack.
65 /// #3 - The number of arg bytes the callee pops off the stack.
66 /// #4 - The value to pass in AL/AX/EAX (optional)
67 /// #5 - The value to pass in DL/DX/EDX (optional)
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H A DX86ISelDAGToDAG.cpp1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
23 #include "llvm/Config/llvm-config.h"
39 #define DEBUG_TYPE "x86-isel"
40 #define PASS_NAME "X86 DAG->DAG Instruction Selection"
44 static cl::opt<bool> AndImmShrink("x86-and-imm-shrink", cl::init(true),
49 "x86-promote-anyext-load", cl::init(true),
54 //===----------------------------------------------------------------------===//
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/freebsd/sys/contrib/device-tree/Bindings/hwmon/
H A Dbaikal,bt1-pvt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/baikal,bt1-pvt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 PVT Sensor
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 SoC provides an embedded process, voltage and temperature
17 which may cause the system instability and even damages. The IP-block
19 control wrapper, which provides a MMIO registers-based access to the
20 sensor core functionality (APB3-bus based) and exposes an additional
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
35 "amdgpu-bypass-slow-div",
36 cl::desc("Skip 64-bit divide for dynamic 32-bit values"),
40 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType() argument
41 unsigned StoreSize = VT.getStoreSizeInBits(); in getEquivalentMemType()
48 return VT; in getEquivalentMemType()
56 // In order for this to be a signed 24-bit value, bit 23, must in numBitsSigned()
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H A DAMDGPUISelLowering.h1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
32 /// legalized from a smaller type VT. Need to match pre-legalized type because
39 /// unsigned integer. Truncating to this size and then zero-extending to the
44 /// signed integer. Truncating to this size and then sign-extending to the
103 bool shouldCombineMemoryType(EVT VT) const;
136 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
141 /// Return 64-bit value Op as two 32-bit integers.
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