| /freebsd/sys/contrib/device-tree/Bindings/iio/addac/ |
| H A D | adi,ad74115.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |
| H A D | adi,ad74413r.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74412R and AD74413R are quad-channel software configurable input/output
18 The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide
20 The AD74413R differentiates itself from the AD74412R by being HART-compatible.
25 compatible:
27 - adi,ad74412r
28 - adi,ad74413r
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/riscv/ |
| H A D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
18 hart: A hardware execution context, which contains all the state
19 mandated by the RISC-V ISA: a PC and some registers. This
[all …]
|
| H A D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
18 This document defines properties that indicate whether a hart supports a
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
[all …]
|
| H A D | riscv,imsics.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
[all …]
|
| H A D | riscv,cpu-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
14 before it interrupts that hart.
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
[all …]
|
| H A D | sifive,plic-1.0.0.txt | 1 SiFive Platform-Level Interrupt Controller (PLIC)
2 -------------------------------------------------
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
7 hart contexts in the system, via the external interrupt source in each hart.
9 A hart context is a privilege mode in a hardware execution thread. For example,
10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
11 privilege modes per hart; machine mode and supervisor mode.
13 Each interrupt can be enabled on per-context basis. Any context can claim
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
[all …]
|
| H A D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
[all …]
|
| H A D | riscv,aplic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
15 in a RISC-V platform. The RISC-V AIA specification can be found at
16 https://github.com/riscv/riscv-aia.
18 The RISC-V APLIC is implemented as hierarchical APLIC domains where all
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/cpu/ |
| H A D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/iio/temperature/ |
| H A D | adi,ltc2983.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices LTC2983, LTC2986, LTM2985 Multi-sensor Temperature system
10 - Nuno Sá <nuno.sa@analog.com>
13 Analog Devices LTC2983, LTC2984, LTC2986, LTM2985 Multi-Sensor Digital
16 https://www.analog.com/media/en/technical-documentation/data-sheets/2983fc.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/2984fb.pdf
18 https://www.analog.com/media/en/technical-documentation/data-sheets/29861fa.pdf
19 https://www.analog.com/media/en/technical-documentation/data-sheets/ltm2985.pdf
[all …]
|
| /freebsd/contrib/ntp/sntp/libevent/ |
| H A D | ChangeLog-2.0 | 1 Changes in version 2.0.21-stable (18 Nov 2012)
6 o dns: Avoid a memory-leak on OOM in evdns. (73e85dd, f2bff75 George Danchev)
9 o build: Fix compilation on mingw64 with -DUSE_DEBUG (62bd2c4)
18 Changes in version 2.0.20-stable (23 Aug 2012)
44 o Fix various check-after-dereference issues in unit tests: found by coverity (4f3732d)
54 Changes in version 2.0.19-stable (3 May 2012)
58 …o If a higher-priority event becomes active, don't continue running events of the current priority…
61 o Fixed potential double-readcb execution with openssl bufferevents. (4e62cd1 Mark Ellzey)
66 o When retransmitting a timed-out DNS request, pick a fresh nameserver. (3d9e52a)
76 o Generate event-config.h with a single sed script (30b6f88 Zack Weinberg)
[all …]
|
| H A D | ChangeLog | 1 Changes in version 2.1.12-stable (05 Jul 2020)
18 o Merge branch 'event_rpcgen.py-cleanup' (f0ded5f3, 48e04887 Enji Cooper)
23 o Merge branch 'osx-clock' (e85afbe3 Azat Khuzhin)
24 …o test-ratelim: calculate timers bias (for slow CPUs) to avoid false-positive (8ad26d0b Azat Khuzh…
28 o http: fix undefined-shift in EVUTIL_IS*_ helpers (6b8d02a7 Azat Khuzhin)
32 …po in GetAdaptersAddresses windows library. It should be iphlpapi.dll (891adda9 Aleksandr-Melnikov)
33 o Merge branch 'EV_CLOSED-and-EV_ET-fixes' (db2efdf5 Azat Khuzhin)
41 o Merge branch 'fix-signal-leak' (poll/select now needs reinit) (1c9cc07b Azat Khuzhin)
56 o https-client: load certificates from the system cert store on Windows (e9478640 yuangongji)
71 o Merge branch 'http-connect' (e2424229 Azat Khuzhin)
[all …]
|
| /freebsd/contrib/libevent/ |
| H A D | ChangeLog-2.0 | 1 Changes in version 2.0.21-stable (18 Nov 2012)
6 o dns: Avoid a memory-leak on OOM in evdns. (73e85dd, f2bff75 George Danchev)
9 o build: Fix compilation on mingw64 with -DUSE_DEBUG (62bd2c4)
18 Changes in version 2.0.20-stable (23 Aug 2012)
44 o Fix various check-after-dereference issues in unit tests: found by coverity (4f3732d)
54 Changes in version 2.0.19-stable (3 May 2012)
58 …o If a higher-priority event becomes active, don't continue running events of the current priority…
61 o Fixed potential double-readcb execution with openssl bufferevents. (4e62cd1 Mark Ellzey)
66 o When retransmitting a timed-out DNS request, pick a fresh nameserver. (3d9e52a)
76 o Generate event-config.h with a single sed script (30b6f88 Zack Weinberg)
[all …]
|
| H A D | ChangeLog | 1 Changes in version 2.1.12-stable (05 Jul 2020)
18 o Merge branch 'event_rpcgen.py-cleanup' (f0ded5f3, 48e04887 Enji Cooper)
23 o Merge branch 'osx-clock' (e85afbe3 Azat Khuzhin)
24 …o test-ratelim: calculate timers bias (for slow CPUs) to avoid false-positive (8ad26d0b Azat Khuzh…
28 o http: fix undefined-shift in EVUTIL_IS*_ helpers (6b8d02a7 Azat Khuzhin)
32 …po in GetAdaptersAddresses windows library. It should be iphlpapi.dll (891adda9 Aleksandr-Melnikov)
33 o Merge branch 'EV_CLOSED-and-EV_ET-fixes' (db2efdf5 Azat Khuzhin)
41 o Merge branch 'fix-signal-leak' (poll/select now needs reinit) (1c9cc07b Azat Khuzhin)
56 o https-client: load certificates from the system cert store on Windows (e9478640 yuangongji)
71 o Merge branch 'http-connect' (e2424229 Azat Khuzhin)
[all …]
|
| /freebsd/contrib/ntp/ |
| H A D | NEWS | 1 ---
10 - changes crypto (OpenSSL or compatible) detection and default build behavior.
11 Previously, crypto was supported if available unless the --without-crypto
13 falling back to a crypto-free build if usable libcrypto was not found has
15 The -
[all...] |
| H A D | ChangeLog | 1 ---
6 stepped. <hart@ntp.org>
7 * [Bug 3913] Avoid duplicate IPv6 link-local manycast associations.
8 <hart@ntp.org>
10 * [Bug 3910] Memory leak using openssl-3 <hart@ntp.org>
12 <hart@ntp.org>
13 * [Bug 3903] lib/isc/win32/strerror.c NTstrerror() is not thread-saf
[all...] |
| H A D | CommitLog | 1 ChangeSet@1.4062, 2024-05-25 00:06:49-07:00, ntpreleng@ntp-build.tal1.ntfo.org
5 ChangeLog@1.2103 +1 -0
8 ntpd/invoke-ntp.conf.texi@1.231 +1 -1
11 ntpd/invoke-ntp.keys.texi@1.214 +1 -1
14 ntpd/invoke-ntp
[all...] |
| /freebsd/contrib/ntp/ntpd/ |
| H A D | refclock_nmea.c | 2 * refclock_nmea.c - clock driver for an NMEA GPS CLOCK
15 * Dave Hart July 1, 2009
16 * hart@ntp.org, davehart@davehart.com
51 * This driver supports NMEA-compatible GPS receivers
71 * bit 0 - enables RMC (1)
72 * bit 1 - enables GGA (2)
73 * bit 2 - enables GLL (4)
74 * bit 3 - enables ZDA (8) - Standar
[all...] |
| /freebsd/contrib/sendmail/ |
| H A D | RELEASE_NOTES | 13 - Prevent transaction stuffing by ensuring SMTP clients
19 - Accept only CRLF . CRLF as end of an SMTP message
22 - Do not accept a CR or LF except in the combination
31 are used, i.e., TLSA RR 2-x-y and 3-x-y are supported
76 because the -a. option has been removed (as it only
79 VACATION: Add support for Return-Path header to set sender
81 VACATION: Honor RFC3834 and avoid an auto-reply if
82 'Auto-Submitted: no' is found in the headers to
84 VACATION: Avoid an auto-reply if a 'List-Id:' is found in
119 When EAI is enabled, mailq prints UTF-8 addresses as such
[all …]
|
| /freebsd/contrib/one-true-awk/testdir/ |
| H A D | funstack.in | 2 %%% BibTeX-file{
23 %%% (incompletely) 1970 -- 1979.
50 %%% covering 1958--1996 became too large (about
65 %%% Algorithms 1--492. For Algorithms 493--686,
72 %%% cross-referenced in both directions, so
75 %%% Corrigenda. Cross-referenced entries are
77 %%% that each is completely self-contained.
83 %%% ftp://netlib.bell-labs.com/netlib/toms.
88 %%% http://ciir.cs.umass.edu/cgi-bin/web_query_form/public/cacm2.1.
90 %%% The initial draft of entries for 1981 --
[all …]
|
| /freebsd/share/dict/ |
| H A D | web2 | 40279 compatible
82654 hart
99810 Jean-Christophe
99811 Jean-Pierre
|