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Searched full:dsb (Results 1 – 25 of 140) sorted by relevance

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/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellde/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 17 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o… 52 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 58 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc… 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 69 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc… 80 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 91 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 96 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 102 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwell/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 17 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o… 52 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 58 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc… 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 69 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc… 80 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 91 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 96 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 102 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/broadwellx/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 17 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o… 52 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 58 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc… 63 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 69 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc… 80 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 91 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 96 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 102 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A D	frontend.json	13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 18 "PublicDescription": "Number of DSB to MITE switches.", 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 28 "PublicDescription": "Cycles DSB to MITE switches caused delay.", 33 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff… 38 "PublicDescription": "DSB Fill encountered > 3 DSB lines.", 73 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 79 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 84 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 90 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A D	frontend.json	13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 18 "PublicDescription": "Number of DSB to MITE switches.", 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 28 "PublicDescription": "Cycles DSB to MITE switches caused delay.", 33 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff… 38 "PublicDescription": "DSB Fill encountered > 3 DSB lines.", 73 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 79 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 84 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 90 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", [all …]
/freebsd/sys/arm/include/
H A D	cpu.h	`320 dsb(); in _WF0() 322 dsb(); in _WF0() 330 dsb(); in tlb_flush_all_ng_local() 332 dsb(); in tlb_flush_all_ng_local() 342 dsb(); in tlb_flush_local() 344 dsb(); in tlb_flush_local() 357 dsb(); in tlb_flush_range_local() 360 dsb(); in tlb_flush_range_local() 370 dsb(); in tlb_flush_all() 375 dsb(); in tlb_flush_all() [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/skylake/
H A D	frontend.json	13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 18 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o… 33 "BriefDescription": "Retired Instructions who experienced DSB miss.", 41 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 47 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 55 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 326 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 332 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/
H A D	frontend.json	13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 18 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o… 33 "BriefDescription": "Retired Instructions who experienced DSB miss.", 41 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 47 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 55 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 326 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 332 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A D	frontend.json	13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 18 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec… 23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 28 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o… 33 "BriefDescription": "Retired Instructions who experienced DSB miss.", 41 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 47 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 55 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 326 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 332 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ… [all …]
/freebsd/sys/arm64/arm64/
H A D	cpufunc_asm.S	`76 dsb ish 83 dsb ish 97 dsb ishst 103 dsb ish 137 * When the CTR_EL0.IDC bit is set cleaning to PoU becomes a dsb. 141 dsb ishst 148 * When the CTR_EL0.IDC bit is set cleaning to PoU becomes a dsb. 151 dsb ishst 153 dsb ish 169 dsb ish [all …]`
H A D	bus_space_asm.S	`409 dsb sy 419 dsb sy 429 dsb sy 439 dsb sy 449 dsb sy 458 dsb sy 467 dsb sy 476 dsb sy`
/freebsd/lib/libpmc/pmu-events/arch/x86/icelake/
H A D	frontend.json	15 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 23 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 35 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b… 41 "BriefDescription": "Retired Instructions who experienced DSB miss.", 50 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 56 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 65 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 344 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 351 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/
H A D	frontend.json	14 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 22 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 27 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 33 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b… 38 "BriefDescription": "Retired Instructions who experienced DSB miss.", 47 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 53 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 62 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 337 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 344 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 26 …t counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decod… 31 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce… 40 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff… 49 … "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", 77 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 87 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 117 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 127 …ion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A D	frontend.json	12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", 21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 26 …t counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decod… 31 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce… 40 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff… 49 … "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", 77 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", 87 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", 117 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 127 …ion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/
H A D	frontend.json	15 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 23 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe… 29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 35 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b… 41 "BriefDescription": "Retired Instructions who experienced DSB miss.", 50 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 56 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 65 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 344 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 351 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A D	frontend.json	14 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 20 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b… 25 "BriefDescription": "Retired Instructions who experienced DSB miss.", 34 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. … 40 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 49 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we… 330 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 337 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", 342 "BriefDescription": "Cycles DSB is delivering optimal number of Uops", 349 …line) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswell/
H A D	frontend.json	13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 59 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 65 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 70 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 76 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 103 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 113 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 118 …"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = … 175 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered … 185 …eries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Se… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/haswellx/
H A D	frontend.json	13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", 59 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 65 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 70 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 76 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 103 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 113 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 118 …"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = … 175 …"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered … 185 …eries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Se… [all …]
/freebsd/sys/arm/arm/
H A D	locore.S	`141 DSB 145 DSB 303 DSB 313 DSB 317 DSB 347 DSB 356 DSB 365 DSB 368 DSB 373 DSB [all …]`
H A D	cpu_asm-v6.S	`90 4: dsb /* wait for stores to finish / 139 4: dsb / wait for stores to finish / 190 4: dsb / wait for stores to finish */ 210 DSB 235 DSB 246 DSB`
/freebsd/stand/arm64/libarm64/
H A D	cache.c	`87 dsb(ishst); in cpu_flush_dcache() 100 /* Full system DSB */ in cpu_flush_dcache() 101 dsb(ish); in cpu_flush_dcache() 118 "dsb ish \n" in cpu_inval_icache()`
/freebsd/sys/arm64/vmm/
H A D	vmm_nvhe.c	`57 dsb(ishst); in vmm_dc_civac() 61 dsb(ish); in vmm_dc_civac() 70 dsb(ishst); in vmm_el2_tlbi() 84 dsb(ish); in vmm_el2_tlbi()`
H A D	vmm_nvhe_exception.S	`81 dsb ish 83 dsb ishst 113 dsb sy`
/freebsd/lib/libpmc/pmu-events/arch/x86/alderlake/
H A D	frontend.json	47 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 58 "BriefDescription": "Retired Instructions who experienced DSB miss.", 73 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 350 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 362 "BriefDescription": "Cycles DSB is delivering optimal number of Uops", 374 …tion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 432 "BriefDescription": "Number of switches from DSB or MITE to the MS",

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