| /linux/drivers/char/agp/ |
| H A D | intel-agp.h | 94 #define GFX_FLSH_CNTL 0x2170 /* 915+ */
116 /* intel 915G registers */
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| H A D | intel-gtt.c | 1083 /* Setup chipset flush for 915 */ in intel_i9xx_setup_flush()
1291 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1293 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | intel_bios.h | 124 /* pre-915 */
130 /* Pre 915 */
136 /* On 915+ */
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| /linux/net/mac802154/ |
| H A D | main.c | 135 /* 915 MHz BPSK 802.15.4-2003: 40 ksym/s */ in ieee802154_configure_durations()
146 /* 915 MHz O-QPSK 802.15.4-2006: 62.5 ksym/s */ in ieee802154_configure_durations()
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| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_engine.h | 160 * 0x05: ring 1 head pointer (915-class)
161 * 0x06: ring 2 head pointer (915-class)
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| /linux/drivers/gpu/drm/i915/ |
| H A D | intel_pci_config.h | 69 #define GCFGC 0xf0 /* 915+ only */
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| H A D | i915_reg.h | 418 #define SCPD0 _MMIO(0x209c) /* 915+ only */
457 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */
470 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
478 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
861 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
862 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
863 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
864 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
865 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
866 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
[all …]
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_tv_regs.h | 45 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
48 * Enables a fix for the 915GM only.
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| H A D | intel_vbt_defs.h | 253 /* pre-915 */
273 /* Pre 915 */
279 /* On 915+ */
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| /linux/drivers/hid/ |
| H A D | hid-sensor-hub.c | 592 rdesc[915] == 0x81 && rdesc[916] == 0x08 && in sensor_hub_report_fixup()
597 rdesc[915] = rdesc[936] = rdesc[957] = 0x7e; in sensor_hub_report_fixup()
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| /linux/drivers/clk/renesas/ |
| H A D | r8a7792-cpg-mssr.c | 137 DEF_MOD("can1", 915, R8A7792_CLK_P),
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| H A D | r8a77470-cpg-mssr.c | 130 DEF_MOD("can1", 915, R8A77470_CLK_P),
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| H A D | r8a779f0-cpg-mssr.c | 164 DEF_MOD("pfc0", 915, R8A779F0_CLK_CPEX),
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| H A D | r8a77995-cpg-mssr.c | 181 DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
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| H A D | r8a7745-cpg-mssr.c | 144 DEF_MOD("can1", 915, R8A7745_CLK_P),
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| H A D | r8a7794-cpg-mssr.c | 154 DEF_MOD("can1", 915, R8A7794_CLK_P),
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| H A D | r8a7791-cpg-mssr.c | 168 DEF_MOD("can1", 915, R8A7791_CLK_P),
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| H A D | r8a7790-cpg-mssr.c | 175 DEF_MOD("can1", 915, R8A7790_CLK_P),
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| H A D | r8a7742-cpg-mssr.c | 166 DEF_MOD("can1", 915, R8A7742_CLK_P),
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| H A D | r8a774c0-cpg-mssr.c | 209 DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
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| H A D | r8a7743-cpg-mssr.c | 155 DEF_MOD("can1", 915, R8A7743_CLK_P),
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| H A D | r8a779a0-cpg-mssr.c | 232 DEF_MOD("pfc0", 915, R8A779A0_CLK_CP),
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| H A D | r8a77990-cpg-mssr.c | 222 DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
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| /linux/arch/powerpc/kvm/ |
| H A D | book3s_emulate.c | 38 #define OP_31_XOP_SLBMFEE 915
58 #define SPRN_GQR3 915
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | r8a779h0.dtsi | 216 clocks = <&cpg CPG_MOD 915>;
218 resets = <&cpg 915>;
231 clocks = <&cpg CPG_MOD 915>;
233 resets = <&cpg 915>;
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