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/linux/Documentation/devicetree/bindings/iio/pressure/
H A Dhoneywell,hsc030pa.yaml52 1 - B, 5% to 95% of 2^14
53 2 - C, 5% to 85% of 2^14
65 400MD, 600MD, 001BD, 1.6BD, 2.5BD, 004BD, 2.5MG, 004MG, 006MG,
66 010MG, 016MG, 025MG, 040MG, 060MG, 100MG, 160MG, 250MG, 400MG,
67 600MG, 001BG, 1.6BG, 2.5BG, 004BG, 006BG, 010BG, 100KA, 160KA,
91 Provide VDD power to the sensor (either 3.3V or 5V depending on the chip)
/linux/Documentation/input/devices/
H A Dcma3000_d0x.rst116 5: 100 Hz Free fall mode
122 2000: 2000 mg or 2G Range
123 8000: 8000 mg or 8G Range
127 X: X * 71mg (8G Range)
128 X: X * 18mg (2G Range)
138 X: (X >> 2) * 18mg (2G Range)
139 X: (X & 0x0F) * 71 mg (8G Range)
/linux/include/linux/input/
H A Dadxl34x.h22 * form with a scale factor of 15.6 mg/LSB (i.e. 0x7F = +2 g)
49 * The data format is unsigned. The scale factor is 62.5 mg/LSB
114 #define ADXL_ACT_Y_EN (1 << 5)
127 * 62.5 mg/LSB. A zero value may result in undesirable behavior if
137 * factor is 62.5 mg/LSB. A zero value may result in undesirable
166 * occurring. The scale factor is 62.5 mg/LSB. A zero value may
168 * enabled. Values between 300 and 600 mg (0x05 to 0x09) are
179 * scale factor is 5 ms/LSB. A zero value may result in
202 * with RANGE to maintain a 4 mg/LSB scale factor. When this
240 #define ADXL_LINK (1 << 5)
[all …]
/linux/drivers/iio/pressure/
H A Dhsc030pa.c42 #define HSC_TEMPERATURE_MASK GENMASK(15, 5)
52 * function B: 5% - 95% of 2^14
53 * function C: 5% - 85% of 2^14
105 [HSC2_5MG] = "2.5MG", [HSC004MG] = "004MG", [HSC006MG] = "006MG",
106 [HSC010MG] = "010MG", [HSC016MG] = "016MG", [HSC025MG] = "025MG",
107 [HSC040MG] = "040MG", [HSC060MG] = "060MG", [HSC100MG] = "100MG",
108 [HSC160MG] = "160MG", [HSC250MG] = "250MG", [HSC400MG] = "400MG",
109 [HSC600MG] = "600MG", [HSC001BG] = "001BG", [HSC1_6BG] = "1.6BG",
429 .shift = 5,
H A Dmprls0025pa.c35 #define MPR_ST_BUSY BIT(5) /* device is busy */
97 [MPR0060MG] = "0060MG", [MPR0100MG] = "0100MG", [MPR0160MG] = "0160MG",
98 [MPR0250MG] = "0250MG", [MPR0400MG] = "0400MG", [MPR0600MG] = "0600MG",
221 * datasheet only says to wait at least 5 ms for the in mpr_read_pressure()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_ddi_buf_trans.c59 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } }, /* 5: 600 900 3.5 */
132 { .hsw = { 0x00D7FFFF, 0x00140006, 0x0 } }, /* 5: 600 800 2.5 */
368 { .bxt = { 116, 0x9A, 0, 85, } }, /* 5: 600 3.5 */
387 { .bxt = { 48, 0, 0, 104, } }, /* 5: 250 1.5 */
409 { .bxt = { 77, 0x9A, 0, 85, } }, /* 5: 600 3.5 */
594 { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */
595 { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */
596 { .mg = { 0x24, 0x00, 0x0C } }, /* 0 2 */
597 { .mg = { 0x2B, 0x00, 0x14 } }, /* 0 3 */
598 { .mg = { 0x21, 0x00, 0x00 } }, /* 1 0 */
[all …]
H A Dintel_dpll_mgr.h91 DPLL_ID_LCPLL_2700 = 5,
129 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
134 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
139 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
142 DPLL_ID_ICL_MGPLL3 = 5,
144 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
149 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
H A Dintel_ddi.c87 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
312 return DDI_BUF_PHY_LINK_RATE(5); in ddi_buf_phy_link_rate()
1223 /* 5. Program swing and de-emphasis */ in icl_combo_phy_set_signal_levels()
1262 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); in icl_mg_phy_set_signal_levels()
1268 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); in icl_mg_phy_set_signal_levels()
1280 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | in icl_mg_phy_set_signal_levels()
1281 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | in icl_mg_phy_set_signal_levels()
1289 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | in icl_mg_phy_set_signal_levels()
1290 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | in icl_mg_phy_set_signal_levels()
1298 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the in icl_mg_phy_set_signal_levels()
[all …]
H A Dintel_dpll_mgr.c306 if (DISPLAY_VER(i915) < 5) in intel_disable_shared_dpll()
1012 * code only cares about 5% accuracy, and spread is a max of in hsw_ddi_wrpll_get_freq()
1392 if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5)) in skl_ddi_pll_enable()
1542 if (half == 1 || half == 2 || half == 3 || half == 5) { in skl_wrpll_get_multipliers()
1559 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ in skl_wrpll_get_multipliers()
1563 } else if (p == 5 || p == 7) { in skl_wrpll_get_multipliers()
1570 *p2 = 5; in skl_wrpll_get_multipliers()
1578 *p2 = 5; in skl_wrpll_get_multipliers()
1629 case 5: in skl_wrpll_params_populate()
1673 static const u8 odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; in skl_ddi_calculate_wrpll()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-mvebu-comphy.txt31 consequently: MG clock, MG Core clock, AXI clock.
49 clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
/linux/net/mac80211/
H A Drc80211_minstrel_ht.c31 ((syms) * 18000 + 4000) / 5 : /* syms * 3.6 us */ \
282 * e.g for MCS9@20MHzx1Nss: Ndbps=8x52*(5/6) Nes=1
576 struct minstrel_mcs_group_data *mg; in minstrel_ht_set_best_prob_rate() local
586 mg = &mi->groups[cur_group]; in minstrel_ht_set_best_prob_rate()
587 mrs = &mg->rates[cur_idx]; in minstrel_ht_set_best_prob_rate()
609 max_gpr_group = MI_RATE_GROUP(mg->max_group_prob_rate); in minstrel_ht_set_best_prob_rate()
610 max_gpr_idx = MI_RATE_IDX(mg->max_group_prob_rate); in minstrel_ht_set_best_prob_rate()
623 mg->max_group_prob_rate = index; in minstrel_ht_set_best_prob_rate()
628 mg->max_group_prob_rate = index; in minstrel_ht_set_best_prob_rate()
673 struct minstrel_mcs_group_data *mg; in minstrel_ht_prob_rate_reduce_streams() local
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmarvell,pp2.yaml39 - description: MG clock
40 - description: MG Core clock
111 - 5gbase-r
159 minItems: 5
162 minItems: 5
241 <&cp0_clk 1 5>, <&cp0_clk 1 6>, <&cp0_clk 1 18>;
/linux/drivers/clk/mvebu/
H A Dcp110-system-controller.c18 * - SDIO (2/5 PLL0)
22 * - 2/5 PLL0
58 #define CP110_CORE_SDIO 5
66 #define CP110_GATE_MG 5
92 [CP110_GATE_MG] = "mg-domain",
93 [CP110_GATE_MG_CORE] = "mg-core",
293 pll0_name, 0, 2, 5); in cp110_syscon_common_probe()
307 pll0_name, 0, 2, 5); in cp110_syscon_common_probe()
/linux/drivers/staging/rts5208/
H A Drtsx_scsi.h89 #define KC_MG_R_PRO 0xBE /* MG-R PRO*/
107 #define SENSE_TYPE_MEDIA_WRITE_PROTECT 5
/linux/Documentation/driver-api/media/drivers/
H A Dtuners.rst38 5: With FM
73 MG: BG DKI M (?)
81 4[01][0136][269]F[HYNR]5
82 40x2: Tuner (5V/33V), TEMIC_API.
83 40x6: Tuner 5V
91 F[HYNR]5
/linux/drivers/iio/imu/inv_icm42600/
H A Dinv_icm42600_accel.c484 * Value is limited to +/-1g coded on 12 bits signed. Step is 0.5mg.
550 * 12 bits signed raw step 0.5mg to g: 5 / 10000 in inv_icm42600_accel_read_offset()
553 * (offset * 5 * 9.806650 * 1000000) / 10000 in inv_icm42600_accel_read_offset()
555 val64 = (int64_t)offset * 5LL * 9806650LL; in inv_icm42600_accel_read_offset()
600 inv_icm42600_accel_calibbias[5]; in inv_icm42600_accel_write_offset()
608 * g to raw 12 bits signed, step 0.5mg: 10000 / 5 in inv_icm42600_accel_write_offset()
610 * val * 10000 / (9.806650 * 1000000 * 5) in inv_icm42600_accel_write_offset()
613 /* for rounding, add + or - divisor (9806650 * 5) divided by 2 */ in inv_icm42600_accel_write_offset()
615 val64 += 9806650 * 5 / 2; in inv_icm42600_accel_write_offset()
617 val64 -= 9806650 * 5 / 2; in inv_icm42600_accel_write_offset()
[all …]
/linux/drivers/staging/iio/accel/
H A Dadis16240.c157 #define ADIS16240_DIAG_STAT_PWRON_FAIL_BIT 5
267 *val2 = IIO_G_TO_M_S_2(51400); /* 51.4 mg */ in adis16240_read_raw()
275 *val2 = IIO_G_TO_M_S_2(51400); /* 51.4 mg */ in adis16240_read_raw()
/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dcp110-system-controller.txt40 - 0 5 SDIO core
47 - 1 5 MG Domain
48 - 1 6 MG Core
96 mpp5 5 gpio, dev(ad12), au(i2sdi), ge0(rxclk), tdm(intn), mss_uart(txd), uart1(rts), pcie1(clkreq),…
/linux/arch/sparc/include/uapi/asm/
H A Dpstate.h10 * | Resv | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG |
12 * 63 12 11 10 9 8 7 6 5 4 3 2 1 0
39 * 63 43 42 40 39 32 31 24 23 20 19 8 7 5 4 0
94 * 63 48 47 32 31 24 23 16 15 8 7 5 4 0
/linux/drivers/iio/accel/
H A Dadis16209.c67 #define ADIS16209_STAT_SELFTEST_FAIL_BIT 5
167 * 1 LSB represents 0.244 mg. in adis16209_read_raw()
/linux/drivers/input/misc/
H A Dadxl34x.c66 #define DOUBLE_TAP (1 << 5)
76 #define ACT_Y_EN (1 << 5)
91 #define ACT_Y_SRC (1 << 5)
103 #define PCTL_LINK (1 << 5)
112 #define INT_INVERT (1 << 5)
139 #define TRIGGER (1 << 5)
148 #define YSIGN (1 << 5)
171 #define ADXL346_3D_LEFT 5 /* -Y */
379 * completely popped, there must be at least 5 us between in adxl34x_irq()
388 * total of 5 us, which is at most 3.4 us at 5 MHz in adxl34x_irq()
[all …]
/linux/drivers/acpi/
H A Dresource.c611 DMI_MATCH(DMI_PRODUCT_NAME, "MG-VCP2-15A3070T"),
618 DMI_MATCH(DMI_PRODUCT_NAME, "MG-VCP2-17A3070T"),
640 /* Infinity E15-5A165-BM */
646 /* Infinity E15-5A305-1M */
652 /* Lunnen Ground 15 / AMD Ryzen 5 5500U */
766 * resource (the legacy ISA resources). With modern ACPI 5 devices in acpi_dev_get_irqresource()
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pci-defs.h307 uint32_t lbase:5;
317 uint32_t lbase:5;
392 uint32_t erbarz:5;
398 uint32_t erbarz:5;
422 uint32_t mg:8; member
428 uint32_t mg:8;
518 uint32_t tdomc:5;
520 uint32_t tdomc:5;
625 uint32_t dn:5;
629 uint32_t dn:5;
[all …]
/linux/include/uapi/linux/
H A Domap3isp.h55 _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct omap3isp_h3a_af_config)
213 #define OMAP3ISP_HIST_MEM_SIZE_BINS(n) ((1 << ((n)+5))*4*4)
274 OMAP3ISP_AF_RB_GG_CUSTOM = 5 /* RB and GG as custom pattern */
327 #define OMAP3ISP_CCDC_CULL (1 << 5)
400 * @b_mg: B/Mg pixels. 2's complement. -128 to +127.
453 #define OMAP3ISP_PREV_WB (1 << 5)
/linux/Documentation/admin-guide/media/
H A Dgspca-cardlist.rst133 se401 047d:5002 Kensington6701(5/7)
178 sunplus 052b:1507 Megapixel 5 Pretec DC-1007
318 vc032x 0ac8:0328 A4Tech PK-130MG

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