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/linux/drivers/clk/qcom/
H A Dipq-cmn-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock
14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
17 * with 31.25 MHZ.
19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ,
20 * and an output clock to NSS (network subsystem) at 300 MHZ. The other output
[all …]
/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-hp300.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 ** asm/bootinfo-hp300.h -- HP9000/300-specific boot information definitions
11 * HP9000/300-specific tags
25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
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/linux/Documentation/scsi/
H A Daic7xxx.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec Aic7xxx Fast -> Ultra160 Family Manager Set v7.0
26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
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/linux/net/wireless/tests/
H A Dchan.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2023-2024 Intel Corporation
35 .desc = "identical non-HT",
44 .desc = "identical 20 MHz",
53 .desc = "identical 40 MHz",
62 .desc = "identical 80 MHz",
71 .desc = "identical 160 MHz",
80 .desc = "identical 320 MHz",
89 .desc = "20 MHz in 320 MHz\n",
103 .desc = "different 20 MHz",
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/linux/drivers/phy/intel/
H A Dphy-intel-keembay-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
59 unsigned int mhz; in keembay_emmc_phy_power() local
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
69 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
85 if (mhz <= 200 && mhz >= 170) in keembay_emmc_phy_power()
87 else if (mhz <= 170 && mhz >= 140) in keembay_emmc_phy_power()
89 else if (mhz <= 140 && mhz >= 110) in keembay_emmc_phy_power()
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/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
5 * Copyright (C) 2005-2009 Texas Instruments, Inc.
6 * Copyright (C) 2004-2009 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
34 * struct prcm_config - define clock rates on a per-OPP basis (24xx)
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
64 /*-------------------------------------------------------------------------
66 *-------------------------------------------------------------------------*/
68 /* 2430 Ratio's, 2430-Ratio Config 1 */
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/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "clk-uniphier.h"
12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
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/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
28 mode "640x480-60"
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
52 mode "640x480-75"
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
73 mode "640x480-85"
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/linux/drivers/ata/
H A Dpata_ftide010.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * struct ftide010 - state container for the Faraday FTIDE010
48 /* Gemini-specific properties */
79 /* 0 = 50 MHz, 1 = 66 MHz */
94 * reference clock which is 30 nanoseconds per unit at 66MHz and 20
95 * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
103 * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
105 * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
107 * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
109 * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
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H A Dpata_hpt37x.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
12 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
200 * hpt37x_find_mode - reset the hpt37x bus
210 struct hpt_clock *clocks = ap->host->private_data; in hpt37x_find_mode()
212 while (clocks->xfer_speed) { in hpt37x_find_mode()
213 if (clocks->xfer_speed == speed) in hpt37x_find_mode()
214 return clocks->timing; in hpt37x_find_mode()
227 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); in hpt_dma_broken()
229 i = match_string(list, -1, model_num); in hpt_dma_broken()
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/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Drfi.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2020 - 2022 Intel Corporation
8 #include "fw/api/phy-ctxt.h"
11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
16 {cpu_to_le16(160), {50, 58, 60, 62, 64, 52, 54, 56},
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
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/linux/Documentation/devicetree/bindings/net/
H A Dnxp,tja11xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
23 - ethernet-phy-id0180.dd00
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/linux/arch/arm/mach-pxa/
H A Dsleep.S2 * Low-level PXA250/210 sleep/wakeUp support
17 #include "pxa2xx-regs.h"
28 * pxa3xx_finish_suspend() - forces CPU into sleep state (S2D3C4)
59 @ enable SDRAM self-refresh mode
62 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
67 @ with core operating above 91 MHz
68 @ (see Errata 50, ...processor does not exit from sleep...)
100 @ enable SDRAM self-refresh mode
104 @ about suspending with PXBus operating above 133MHz
107 @ We keep the change-down close to the actual suspend on SDRAM
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/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7100-clkgen.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
11 - Emil Renner Berthing <kernel@esmil.dk>
15 const: starfive,jh7100-clkgen
22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
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/linux/Documentation/admin-guide/media/
H A Dvivid.rst1 .. SPDX-License-Identifier: GPL-2.0
13 Each input can be a webcam, TV capture device, S-Video capture device or an HDMI
14 capture device. Each output can be an S-Video output device or an HDMI output
23 - Support for read()/write(), MMAP, USERPTR and DMABUF streaming I/O.
24 - A large list of test patterns and variations thereof
25 - Working brightness, contrast, saturation and hue controls
26 - Support for the alpha color component
27 - Full colorspace support, including limited/full RGB range
28 - All possible control types are present
29 - Support for various pixel aspect ratios and video aspect ratios
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/linux/drivers/gpu/drm/tests/
H A Ddrm_kunit_edid.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * edid-decode (hex):
18 * ----------------
41 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
46 * Monitor ranges (GTF): 50-70 Hz V, 30-70 kHz H, max dotclock 150 MHz
50 * ----------------
52 * edid-decode 1.30.0-5367
53 * edid-decode SHA: 41ebf7135691 2025-05-01 10:19:22
73 * This edid is intentionally broken with the 100MHz limit. It's meant
76 * edid-decode (hex):
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H A Ddrm_modes_test.c1 // SPDX-License-Identifier: GPL-2.0
26 priv->dev = drm_kunit_helper_alloc_device(test); in drm_test_modes_init()
27 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, priv->dev); in drm_test_modes_init()
29 priv->drm = __drm_kunit_helper_alloc_drm_device(test, priv->dev, in drm_test_modes_init()
30 sizeof(*priv->drm), 0, in drm_test_modes_init()
32 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, priv->drm); in drm_test_modes_init()
34 test->priv = priv; in drm_test_modes_init()
41 struct drm_test_modes_priv *priv = test->priv; in drm_test_modes_analog_tv_ntsc_480i()
45 mode = drm_analog_tv_mode(priv->drm, in drm_test_modes_analog_tv_ntsc_480i()
55 KUNIT_EXPECT_EQ(test, mode->hdisplay, 720); in drm_test_modes_analog_tv_ntsc_480i()
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/linux/drivers/cpufreq/
H A Dpxa2xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * 31-Jul-2002 : Initial version [FB]
7 * 29-Jan-2003 : added PXA255 support [FB]
8 * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
42 MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
62 { 99500, -1, -1}, /* 99, 99, 50, 50 */
63 {132700, -1, -1}, /* 133, 133, 66, 66 */
64 {199100, -1, -1}, /* 199, 199, 99, 99 */
65 {265400, -1, -1}, /* 265, 265, 133, 66 */
66 {331800, -1, -1}, /* 331, 331, 166, 83 */
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/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2016-2018 NXP
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
108 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
109 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
110 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
116 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_idiv_config()
117 struct device *dev = priv->ds->dev; in sja1105_cgu_idiv_config()
121 if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR) in sja1105_cgu_idiv_config()
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/linux/Documentation/devicetree/bindings/mfd/
H A Dst,stmpe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Linus Walleij <linus.walleij@linaro.org>
18 - $ref: /schemas/spi/spi-peripheral-props.yaml#
23 - st,stmpe601
24 - st,stmpe801
25 - st,stmpe811
26 - st,stmpe1600
27 - st,stmpe1601
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/linux/drivers/scsi/
H A Ddc395x.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 /* (SCSI chip set used Tekram ASIC TRM-S1040) */
31 #define DC395x_SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
175 /* cmd->result */
296 /* --------- ------------- ---------------------------- */
297 /* 07-05 0 RSVD Reversed. Always 0. */
299 /* 03-00 0 OFFSET[03:00] Offset number from 0 to 15 */
306 #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */
315 /* --------- ------------- --------------------------- */
316 /* 07-06 0 RSVD Reversed. Always read 0 */
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/linux/drivers/media/pci/mantis/
H A Dmantis_vp3030.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Mantis VP-3030 driver
31 .name = "ENV57H12D5 (ET-50DT)",
33 .frequency_min = 47 * MHz,
34 .frequency_max = 862 * MHz,
36 .ref_multiplier = 6, /* 1/6 MHz */
37 .ref_divider = 100000, /* 1/6 MHz */
40 #define MANTIS_MODEL_NAME "VP-3030"
41 #define MANTIS_DEV_TYPE "DVB-T"
46 struct i2c_adapter *adapter = &mantis->adapter; in vp3030_frontend_init()
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/linux/arch/arm/boot/dts/ti/omap/
H A Dam5729-beagleboneai.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2019 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
9 #include "am57xx-commercial-grade.dtsi"
10 #include "dra74x-mmc-iodelay.dtsi"
11 #include "dra74-ipu-dsp-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/dra.h>
18 compatible = "beagle,am5729-beagleboneai", "ti,am5728",
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/linux/drivers/clk/
H A Dkunit_clk_parent_data_test.dtso1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 fixed_50: kunit-clock-50MHz {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <50000000>;
12 clock-output-names = CLK_PARENT_DATA_50MHZ_NAME;
15 fixed_parent: kunit-clock-1MHz {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
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/linux/drivers/clk/versatile/
H A Dclk-icst.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (C) 2012-2015 Linus Walleij
17 #include <linux/clk-provider.h>
23 #include "clk-icst.h"
37 * struct clk_icst - ICST VCO clock wrapper
59 * vco_get() - get ICST VCO settings from a certain ICST
68 ret = regmap_read(icst->map, icst->vcoreg_off, &val); in vco_get()
77 * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and in vco_get()
78 * CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14. in vco_get()
80 if (icst->ctype == ICST_INTEGRATOR_AP_CM) { in vco_get()
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