| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-srggb10-ipu3.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _v4l2-pix-fmt-ipu3-sbggr10:
5 .. _v4l2-pix-fmt-ipu3-sgbrg10:
6 .. _v4l2-pix-fmt-ipu3-sgrbg10:
7 .. _v4l2-pix-fmt-ipu3-srggb10:
14 10-bit Bayer formats
21 sRGB / Bayer formats with 10 bits per sample with every 25 pixels packed
22 to 32 bytes leaving 6 most significant bits padding in the last byte.
25 In other respects this format is similar to :ref:`V4L2-PIX-FMT-SRGGB10`.
37 .. flat-table::
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| H A D | pixfmt-srggb14p.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _V4L2-PIX-FMT-SRGGB14P:
5 .. _v4l2-pix-fmt-sbggr14p:
6 .. _v4l2-pix-fmt-sgbrg14p:
7 .. _v4l2-pix-fmt-sgrbg14p:
18 14-bit packed Bayer formats
25 bits per colour. Every four consecutive samples are packed into seven
26 bytes. Each of the first four bytes contain the eight high order bits
28 significant bits of each pixel, in the same order.
30 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
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| H A D | pixfmt-packed-yuv.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _packed-yuv:
16 - In all the tables that follow, bit 7 is the most significant bit in a byte.
17 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
19 denotes bits of the alpha component (if supported by the format), and 'X'
20 denotes padding bits.
23 4:4:4 Subsampling
29 The next table lists the packed YUV 4:4:4 formats with less than 8 bits per
31 seen in a 16-bit word, which is then stored in memory in little endian byte
32 order, and on the number of bits for each component. For instance the YUV565
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| H A D | pixfmt-srggb12p.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _V4L2-PIX-FMT-SRGGB12P:
5 .. _v4l2-pix-fmt-sbggr12p:
6 .. _v4l2-pix-fmt-sgbrg12p:
7 .. _v4l2-pix-fmt-sgrbg12p:
14 12-bit packed Bayer formats
15 ---------------------------
22 bits per colour. Every two consecutive samples are packed into three
23 bytes. Each of the first two bytes contain the 8 high order bits of
25 bits of each pixel, in the same order.
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| /linux/include/rdma/ |
| H A D | ib_smi.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
71 u8 linkspeed_portstate; /* 4 bits, 4 bits */
72 u8 portphysstate_linkdown; /* 4 bits, 4 bits */
73 u8 mkeyprot_resv_lmc; /* 2 bits, 3, 3 */
74 u8 linkspeedactive_enabled; /* 4 bits, 4 bits */
75 u8 neighbormtu_mastersmsl; /* 4 bits, 4 bits */
76 u8 vlcap_inittype; /* 4 bits, 4 bits */
80 u8 inittypereply_mtucap; /* 4 bits, 4 bits */
81 u8 vlstallcnt_hoqlife; /* 3 bits, 5 bits */
82 u8 operationalvl_pei_peo_fpi_fpo; /* 4 bits, 1, 1, 1, 1 */
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| H A D | opa_port_info.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright (c) 2014-2020 Intel Corporation. All rights reserved.
12 #define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */
17 #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */
21 #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
22 #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
23 #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
24 #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
31 #define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4
61 /* 34 -reserved */
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| /linux/drivers/pci/ |
| H A D | pci-bridge-emul.c | 1 // SPDX-License-Identifier: GPL-2.0
21 #include "pci-bridge-emul.h"
28 * struct pci_bridge_reg_behavior - register bits behaviors
29 * @ro: Read-Only bits
30 * @rw: Read-Write bits
31 * @w1c: Write-1-to-Clear bits
33 * Reads and Writes will be filtered by specified behavior. All other bits not
36 * multi-bit fields) when read".
39 /* Read-only bits */
42 /* Read-write bits */
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | oaktrail.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2007-2011, Intel Corporation.
16 u8 hblank_hi:4;
17 u8 hactive_hi:4;
20 u8 vblank_hi:4;
21 u8 vactive_hi:4;
24 u8 vsync_pulse_width_lo:4;
25 u8 vsync_offset_lo:4;
32 u8 height_mm_hi:4;
33 u8 width_mm_hi:4;
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| /linux/include/drm/display/ |
| H A D | drm_dsc.h | 1 /* SPDX-License-Identifier: MIT
28 #define DSC_PPS_VERSION_MAJOR_SHIFT 4
29 #define DSC_PPS_BPC_SHIFT 4
35 #define DSC_PPS_CONVERT_RGB_SHIFT 4
39 #define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4
45 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
61 * Bits/group offset to apply to target for this group
67 * struct drm_dsc_config - Parameters required to configure DSC
75 * Bits per component for previous reconstructed line buffer
79 * @bits_per_component: Bits per component to code (8/10/12)
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dp_types.h | 36 LANE_COUNT_FOUR = 4,
50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane
51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane
52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane
53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane
54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane
55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane
56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane
57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane
58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane
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| /linux/Documentation/devicetree/bindings/nvmem/ |
| H A D | socionext,uniphier-efuse.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/socionext,uniphier-efuse.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Keiji Hayashibara <hayashibara.keiji@socionext.com>
11 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
14 - $ref: nvmem.yaml#
15 - $ref: nvmem-deprecated-cells.yaml#
19 const: socionext,uniphier-efuse
25 - compatible
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| /linux/drivers/iio/dac/ |
| H A D | ad5686.c | 1 // SPDX-License-Identifier: GPL-2.0
33 return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1; in ad5686_get_powerdown_mode()
42 st->pwr_down_mode &= ~(0x3 << (chan->channel * 2)); in ad5686_set_powerdown_mode()
43 st->pwr_down_mode |= ((mode + 1) << (chan->channel * 2)); in ad5686_set_powerdown_mode()
60 return sysfs_emit(buf, "%d\n", !!(st->pwr_down_mask & in ad5686_read_dac_powerdown()
61 (0x3 << (chan->channel * 2)))); in ad5686_read_dac_powerdown()
81 st->pwr_down_mask |= (0x3 << (chan->channel * 2)); in ad5686_write_dac_powerdown()
83 st->pwr_down_mask &= ~(0x3 << (chan->channel * 2)); in ad5686_write_dac_powerdown()
85 switch (st->chip_info->regmap_type) { in ad5686_write_dac_powerdown()
98 if (chan->channel > 0x7) in ad5686_write_dac_powerdown()
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| /linux/include/linux/irqchip/ |
| H A D | irq-bcm2836.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
13 * next 2 bits identify the CPU that the GPU FIQ goes to.
16 /* When setting bits 0-3, enables PMU interrupts on that CPU. */
18 /* When setting bits 0-3, disables PMU interrupts on that CPU. */
21 * The low 4 bits of this are the CPU's timer IRQ enables, and the
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
23 * bits).
27 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
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| /linux/lib/xz/ |
| H A D | xz_lzma2.h | 1 /* SPDX-License-Identifier: 0BSD */
7 * Igor Pavlov <https://7-zip.org/>
23 * number of bits of the current uncompressed offset. In some places there
26 #define POS_STATES_MAX (1 << 4)
33 * - Literal: One 8-bit byte
34 * - Match: Repeat a chunk of data at some distance
35 * - Long repeat: Multi-byte match at a recently seen distance
36 * - Short repeat: One-byte repeat at a recently seen distance
39 * either short or long repeated match, and NONLIT means any non-literal.
68 *state -= 3; in lzma_state_literal()
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| /linux/drivers/net/ipa/reg/ |
| H A D | ipa_reg-v4.2.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
17 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
31 /* Bits 21-31 reserved */
41 [RAM_ARB] = BIT(4),
67 /* Bits 30-31 reserved */
78 /* Bits 22-23 reserved */
80 /* Bits 25-31 reserved */
94 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
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| H A D | ipa_reg-v3.5.1.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
17 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
18 /* Bits 5-31 reserved */
28 [RAM_ARB] = BIT(4),
46 /* Bits 22-31 reserved */
57 /* Bits 22-23 reserved */
59 /* Bits 25-31 reserved */
73 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
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| H A D | ipa_reg-v4.5.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
17 /* Bit 4 reserved */
32 /* Bits 22-31 reserved */
42 [RAM_ARB] = BIT(4),
80 /* Bits 22-23 reserved */
82 /* Bits 25-31 reserved */
96 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
97 /* Bits 8-31 reserved */
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| H A D | ipa_reg-v4.7.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
17 /* Bit 4 reserved */
32 /* Bits 22-31 reserved */
42 [RAM_ARB] = BIT(4),
80 /* Bits 22-23 reserved */
82 /* Bits 25-31 reserved */
96 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
97 /* Bits 8-31 reserved */
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| H A D | ipa_reg-v4.11.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
17 /* Bit 4 reserved */
36 /* Bits 24-29 reserved */
48 [RAM_ARB] = BIT(4),
86 /* Bits 22-23 reserved */
88 /* Bits 25-31 reserved */
102 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
103 /* Bits 8-31 reserved */
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| H A D | ipa_reg-v4.9.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
17 /* Bit 4 reserved */
35 /* Bits 25-29 reserved */
47 [RAM_ARB] = BIT(4),
85 /* Bits 22-23 reserved */
87 /* Bits 25-31 reserved */
101 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
102 /* Bits 8-31 reserved */
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| H A D | ipa_reg-v5.0.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
6 #include <linux/bits.h>
26 /* Bit 4 reserved */
45 /* Bits 28-29 reserved */
57 [RAM_ARB] = BIT(4),
96 /* Bits 29-31 reserved */
110 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
111 /* Bits 8-31 reserved */
118 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
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| /linux/drivers/net/ieee802154/ |
| H A D | mcr20a.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
50 /*------------------ 0x27 */
69 /*----------------------- 0x3A */
118 /*-------------------- 0x29 */
124 /*------------------ 0x2F */
128 /*------------------- 0x33 */
147 /*-------------------- 0x46 */
163 /*------------------- 0x56 */
164 /*------------------- 0x57 */
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| /linux/drivers/dma/idxd/ |
| H A D | registers.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
30 #define GET_IDXD_VER_MAJOR(x) (((x) & IDXD_VER_MAJOR_MASK) >> 4)
47 u64 max_batch_shift:4;
52 u64 bits; member
60 u64 wqcfg_size:4;
72 u64 bits; member
86 u64 bits; member
95 u64 bits; member
104 u64 bits[4]; member
121 u64 bits[2]; member
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| /linux/include/linux/mfd/ |
| H A D | rohm-bd71815.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * Author: yanglsh@embest-tech.com
32 /* LDO for Low-Power State Retention */
229 /* BD71815_REG_BUCK1_MODE bits */
236 #define BD71815_BUCK_PWM_FIXED BIT(4)
242 /* BD71815_REG_BUCK1_VOLT_H bits */
249 /* BD71815_REG_BUCK2_VOLT_H bits */
256 /* LED enable bits at LED_CTRL reg */
257 #define LED_CHGDONE_EN BIT(4)
262 /* BD71815_REG_LDO1_CTRL bits */
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| /linux/drivers/net/wireless/zydas/zd1211rw/ |
| H A D | zd_rf_rf2959.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ZD1211 USB-WLAN driver for Linux
4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
18 RF_CHANNEL( 4) = { 0x1819a9, 0x1e6666 },
32 static int bits(u32 rw, int from, int to)
41 return bits(rw, bit, bit);
46 int reg = bits(rw, 18, 22);
47 int rw_flag = bits(rw, 23, 23);
54 bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
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