| /freebsd/sys/arm/freescale/imx/ |
| H A D | imx6_ccmreg.h | 34 #define CBCDR_MMDC_CH1_AXI_PODF_SHIFT 3
35 #define CBCDR_MMDC_CH1_AXI_PODF_MASK (7 << 3)
40 #define SSI_CLK_SEL_M 0x3
57 #define LDB_DI0_CLK_SEL_MASK (3 << LDB_DI0_CLK_SEL_SHIFT)
61 #define CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
62 #define CHSCCDR_IPU1_DI0_PODF_SHIFT 3
66 #define CHSCCDR_CLK_SEL_LDB_DI0 3
80 #define CCGR0_AIPS_TZ1 (0x3 << 0)
81 #define CCGR0_AIPS_TZ2 (0x3 << 2)
82 #define CCGR0_ABPHDMA (0x3 << 4)
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| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | ecore_hsi_roce.h | 134 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */
139 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
163 __le16 local_mac_addr[3] /* BE order */;
164 __le16 remote_mac_addr[3] /* BE order */;
184 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */
189 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
223 __le16 local_mac_addr[3] /* BE order */;
224 __le16 remote_mac_addr[3] /* BE order */;
349 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
366 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3
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| H A D | ecore_hsi_rdma.h | 61 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
63 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
65 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */
79 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
118 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
120 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
122 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */
136 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
186 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */
189 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */
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| H A D | ecore_hsi_eth.h | 72 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
89 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
99 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
101 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
103 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
105 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
108 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
110 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
112 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
114 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
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| H A D | ecore_hsi_iscsi.h | 79 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
96 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
106 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
108 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
110 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
112 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
115 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
117 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
119 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
121 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
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| H A D | ecore_hsi_fcoe.h | 68 u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */;
158 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3
189 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
190 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3
225 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3
250 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
267 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
277 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
279 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
281 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
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| H A D | ecore_hsi_iwarp.h | 81 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
98 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
108 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
110 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
112 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
114 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
117 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
119 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
121 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
123 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
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| H A D | ecore_hsi_common.h | 186 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3 /* ll2 how to handle error packet_too_big …
188 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3 /* ll2 how to handle error with no_buff (…
210 __le16 reserved[3];
255 __le32 reserved1[3];
272 __le32 reserved[3];
347 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
380 #define CORE_TX_BD_TX_DST_MASK 0x3 /* Packet destination - Network, Loopback or Drop (use…
411 u8 resrved[3];
486 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
503 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
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| H A D | fcoe_common.h | 43 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3 /* 0=none, 1=DIF, 2=DIX */
48 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
98 __le32 opaque[3] /* The FCP_XFER payload */;
125 #define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
233 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
235 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
237 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */
251 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
294 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 /* timer0cf */
296 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 /* timer1cf */
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| /freebsd/contrib/bearssl/src/symcipher/ |
| H A D | aes_x86ni_ctr.c | 69 __m128i x0, x1, x2, x3; in br_aes_x86ni_ctr_run() local
71 x0 = _mm_insert_epi32(ivx, br_bswap32(cc + 0), 3); in br_aes_x86ni_ctr_run()
72 x1 = _mm_insert_epi32(ivx, br_bswap32(cc + 1), 3); in br_aes_x86ni_ctr_run()
73 x2 = _mm_insert_epi32(ivx, br_bswap32(cc + 2), 3); in br_aes_x86ni_ctr_run()
74 x3 = _mm_insert_epi32(ivx, br_bswap32(cc + 3), 3); in br_aes_x86ni_ctr_run()
78 x3 = _mm_xor_si128(x3, sk[0]); in br_aes_x86ni_ctr_run()
82 x3 = _mm_aesenc_si128(x3, sk[1]); in br_aes_x86ni_ctr_run()
86 x3 = _mm_aesenc_si128(x3, sk[2]); in br_aes_x86ni_ctr_run()
87 x0 = _mm_aesenc_si128(x0, sk[3]); in br_aes_x86ni_ctr_run()
88 x1 = _mm_aesenc_si128(x1, sk[3]); in br_aes_x86ni_ctr_run()
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| H A D | aes_pwr8_ctrcbc.c | 106 vcipher(x, x, 3) \
119 vcipher(x, x, 3) \
134 vcipher(x, x, 3) \
154 vcipher(x, x, 3) \
155 vcipher(y, y, 3) \
178 vcipher(x, x, 3) \
179 vcipher(y, y, 3) \
206 vcipher(x, x, 3) \
207 vcipher(y, y, 3) \
231 #define BLOCK_ENCRYPT_X4_128(x0, x1, x2, x3) \ argument
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| H A D | aes_x86ni_cbcdec.c | 66 __m128i x0, x1, x2, x3, e0, e1, e2, e3; in br_aes_x86ni_cbcdec_run() local
72 x3 = _mm_loadu_si128((void *)(buf + 48)); in br_aes_x86ni_cbcdec_run()
80 x3 = x2; in br_aes_x86ni_cbcdec_run()
83 x3 = x1; in br_aes_x86ni_cbcdec_run()
88 x3 = x0; in br_aes_x86ni_cbcdec_run()
94 e3 = x3; in br_aes_x86ni_cbcdec_run()
98 x3 = _mm_xor_si128(x3, sk[0]); in br_aes_x86ni_cbcdec_run()
102 x3 = _mm_aesdec_si128(x3, sk[1]); in br_aes_x86ni_cbcdec_run()
106 x3 = _mm_aesdec_si128(x3, sk[2]); in br_aes_x86ni_cbcdec_run()
107 x0 = _mm_aesdec_si128(x0, sk[3]); in br_aes_x86ni_cbcdec_run()
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| H A D | aes_ct64.c | 41 uint64_t x0, x1, x2, x3, x4, x5, x6, x7; in br_aes_ct64_bitslice_Sbox() local
59 x3 = q[4]; in br_aes_ct64_bitslice_Sbox()
60 x4 = q[3]; in br_aes_ct64_bitslice_Sbox()
68 y14 = x3 ^ x5; in br_aes_ct64_bitslice_Sbox()
70 y9 = x0 ^ x3; in br_aes_ct64_bitslice_Sbox()
74 y4 = y1 ^ x3; in br_aes_ct64_bitslice_Sbox()
198 q[3] = s4; in br_aes_ct64_bitslice_Sbox()
221 SWAP2(q[2], q[3]); in br_aes_ct64_ortho()
226 SWAP4(q[1], q[3]); in br_aes_ct64_ortho()
233 SWAP8(q[3], q[7]); in br_aes_ct64_ortho()
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| H A D | aes_x86ni_ctrcbc.c | 70 erev = _mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, in br_aes_x86ni_ctrcbc_ctr()
92 __m128i x0, x1, x2, x3; in br_aes_x86ni_ctrcbc_ctr() local
101 x3 = _mm_shuffle_epi8(ivx3, erev); in br_aes_x86ni_ctrcbc_ctr()
106 x3 = _mm_xor_si128(x3, sk[0]); in br_aes_x86ni_ctrcbc_ctr()
110 x3 = _mm_aesenc_si128(x3, sk[1]); in br_aes_x86ni_ctrcbc_ctr()
114 x3 = _mm_aesenc_si128(x3, sk[2]); in br_aes_x86ni_ctrcbc_ctr()
115 x0 = _mm_aesenc_si128(x0, sk[3]); in br_aes_x86ni_ctrcbc_ctr()
116 x1 = _mm_aesenc_si128(x1, sk[3]); in br_aes_x86ni_ctrcbc_ctr()
117 x2 = _mm_aesenc_si128(x2, sk[3]); in br_aes_x86ni_ctrcbc_ctr()
118 x3 = _mm_aesenc_si128(x3, sk[3]); in br_aes_x86ni_ctrcbc_ctr()
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| /freebsd/contrib/libcbor/src/cbor/internal/ |
| H A D | unicode.c | 20 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 20..3f */
36 0xa, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3,
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| /freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
| H A D | mpc8572ds.dtsi | 55 partition@3e00000 {
167 phy3: ethernet-phy@3 {
169 reg = <0x3>;
184 sgmii_phy3: sgmii-phy@3 {
251 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
252 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
257 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
258 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
263 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
264 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
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| H A D | mpc8548cds.dtsi | 121 phy3: ethernet-phy@3 {
123 reg = <0x3>;
174 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
175 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
177 /* IDSEL 0x5 (PCIX Slot 3) */
180 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
185 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
186 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
192 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
193 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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| /freebsd/lib/libpmc/pmu-events/arch/x86/broadwellde/ |
| H A D | uncore-cache.json | 4 "Counter": "0,1,2,3",
11 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
32 "Counter": "0,1,2,3",
38 "UMask": "0x3",
43 "Counter": "0,1,2,3",
49 "UMask": "0x3",
54 "Counter": "0,1,2,3",
60 "UMask": "0x3",
65 "Counter": "0,1,2,3",
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| /freebsd/lib/libpmc/pmu-events/arch/x86/broadwellx/ |
| H A D | uncore-cache.json | 4 "Counter": "0,1,2,3",
11 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
32 "Counter": "0,1,2,3",
38 "UMask": "0x3",
43 "Counter": "0,1,2,3",
49 "UMask": "0x3",
54 "Counter": "0,1,2,3",
60 "UMask": "0x3",
65 "Counter": "0,1,2,3",
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| /freebsd/lib/libpmc/pmu-events/arch/x86/haswellx/ |
| H A D | uncore-cache.json | 4 "Counter": "0,1,2,3",
11 "Counter": "0,1,2,3",
22 "Counter": "0,1,2,3",
32 "Counter": "0,1,2,3",
38 "UMask": "0x3",
43 "Counter": "0,1,2,3",
49 "UMask": "0x3",
54 "Counter": "0,1,2,3",
60 "UMask": "0x3",
65 "Counter": "0,1,2,3",
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| /freebsd/crypto/openssl/crypto/rc2/ |
| H A D | rc2_cbc.c | 98 register RC2_INT x0, x1, x2, x3, t; in RC2_encrypt() local
106 x3 = (RC2_INT) (l >> 16L); in RC2_encrypt()
108 n = 3; in RC2_encrypt()
113 t = (x0 + (x1 & ~x3) + (x2 & x3) + *(p0++)) & 0xffff; in RC2_encrypt()
115 t = (x1 + (x2 & ~x0) + (x3 & x0) + *(p0++)) & 0xffff; in RC2_encrypt()
117 t = (x2 + (x3 & ~x1) + (x0 & x1) + *(p0++)) & 0xffff; in RC2_encrypt()
118 x2 = (t << 3) | (t >> 13); in RC2_encrypt()
119 t = (x3 + (x0 & ~x2) + (x1 & x2) + *(p0++)) & 0xffff; in RC2_encrypt()
120 x3 = (t << 5) | (t >> 11); in RC2_encrypt()
127 x0 += p1[x3 & 0x3f]; in RC2_encrypt()
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| /freebsd/contrib/googletest/googlemock/test/ |
| H A D | gmock-pp-string_test.cc | 67 EXPECT_EXPANSION("3", GMOCK_PP_NARG(x, y, z)); in TEST()
99 EXPECT_EXPANSION("1", GMOCK_PP_HEAD(1, 2, 3)); in TEST()
103 EXPECT_EXPANSION("2", GMOCK_PP_HEAD(GMOCK_PP_TAIL(1, 2, 3))); in TEST()
125 EXPECT_EXPANSION("3", GMOCK_PP_INC(2)); in TEST()
126 EXPECT_EXPANSION("4", GMOCK_PP_INC(3)); in TEST()
139 EXPECT_EXPANSION("X0= X1= X2=", GMOCK_PP_REPEAT(JOINER, X, 3)); in TEST()
140 EXPECT_EXPANSION("X0= X1= X2= X3=", GMOCK_PP_REPEAT(JOINER, X, 4)); in TEST()
141 EXPECT_EXPANSION("X0= X1= X2= X3= X4=", GMOCK_PP_REPEAT(JOINER, X, 5)); in TEST()
142 EXPECT_EXPANSION("X0= X1= X2= X3= X4= X5=", GMOCK_PP_REPEAT(JOINER, X, 6)); in TEST()
143 EXPECT_EXPANSION("X0= X1= X2= X3= X4= X5= X6=", in TEST()
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| /freebsd/contrib/bearssl/src/rsa/ |
| H A D | rsa_pkcs1_sig_pad.c | 33 size_t u, x3, xlen; in br_rsa_pkcs1_sig_pad() local
37 * 00 01 FF .. FF 00 30 x1 30 x2 06 x3 OID 05 00 04 x4 HASH in br_rsa_pkcs1_sig_pad()
48 * -- x3 is equal to the encoded OID value length (hash_oid[0]). in br_rsa_pkcs1_sig_pad()
50 * -- x2 = x3 + 4. in br_rsa_pkcs1_sig_pad()
52 * -- x1 = x2 + x4 + 4 = x3 + x4 + 8. in br_rsa_pkcs1_sig_pad()
60 xlen = (n_bitlen + 7) >> 3; in br_rsa_pkcs1_sig_pad()
69 memset(x + 2, 0xFF, u - 3); in br_rsa_pkcs1_sig_pad()
72 x3 = hash_oid[0]; in br_rsa_pkcs1_sig_pad()
78 if (xlen < (x3 + hash_len + 21)) { in br_rsa_pkcs1_sig_pad()
83 u = xlen - x3 - hash_len - 11; in br_rsa_pkcs1_sig_pad()
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| /freebsd/sys/contrib/libsodium/src/libsodium/crypto_pwhash/scryptsalsa208sha256/sse/ |
| H A D | pwhash_scryptsalsa208sha256_sse.c | 67 ARX(X1, X0, X3, 7) \
69 ARX(X3, X2, X1, 13) \
70 ARX(X0, X3, X2, 18) \
75 X3 = _mm_shuffle_epi32(X3, 0x39); \
78 ARX(X3, X0, X1, 7) \
79 ARX(X2, X3, X0, 9) \
80 ARX(X1, X2, X3, 13) \
86 X3 = _mm_shuffle_epi32(X3, 0x93);
89 * Apply the salsa20/8 core to the block provided in (X0 ... X3) ^ (Z0 ... Z3).
96 __m128i Y3 = X3 = _mm_xor_si128(X3, (in)[3]); \
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| /freebsd/contrib/bearssl/src/ec/ |
| H A D | ec_c25519_m62.c | 91 w = m & (a[3] ^ b[3]); a[3] ^= w; b[3] ^= w; in f255_cswap()
104 d[3] = a[3] + b[3]; in f255_add()
140 w = a[3] - b[3] - cc; in f255_sub()
141 d[3] = w & MASK51; in f255_sub()
209 UMUL51(t[3], lo, a[2], b[0]); t[2] += lo; in f255_mul()
210 UMUL51(hi, lo, a[1], b[1]); t[2] += lo; t[3] += hi; in f255_mul()
211 UMUL51(hi, lo, a[0], b[2]); t[2] += lo; t[3] += hi; in f255_mul()
213 UMUL51(t[4], lo, a[3], b[0]); t[3] += lo; in f255_mul()
214 UMUL51(hi, lo, a[2], b[1]); t[3] += lo; t[4] += hi; in f255_mul()
215 UMUL51(hi, lo, a[1], b[2]); t[3] += lo; t[4] += hi; in f255_mul()
[all …]
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