| /freebsd/share/man/man4/ |
| H A D | pms.4 | 30 .Nd "PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 SAS/SATA HBA Controller driver"
35 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
48 driver provides support for the PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077
55 .Bl -bullet -compact
57 Tachyon TS Fibre Channel Card
59 Tachyon TL Fibre Channel Card
61 Tachyon XL2 Fibre Channel Card
63 Tachyon DX2 Fibre Channel Card
65 Tachyon DX2+ Fibre Channel Card
[all …]
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| H A D | snd_hdsp.4 | 35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
57 .Bl -bullet -compact
59 RME HDSP 9632 (optional AO4S-192 and AIS-192 extension boards)
67 For ADAT ports, 8 channel, 4 channel and 2 channel formats are supported.
69 (32kHz-48kHz) and 4 channels at double speed (64kHz-96kHz).
70 Only the HDSP 9632 can operate at quad speed (128kHz-192kHz), ADAT is
72 Depending on sample rate and channel format selected, not all pcm channels can
79 .Bl -tag -width indent
82 When opened in multi-channel audio software, this makes all ports available
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| H A D | snd_hdspe.4 | 34 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
56 .Bl -bullet -compact
58 RME HDSPe AIO (optional AO4S-192 and AI4S-192 extension boards)
66 For ADAT ports, 8 channel, 4 channel and 2 channel formats are supported.
68 (32kHz-48kHz), 4 channels at double speed (64kHz-96kHz), and 2 channels at
69 quad speed (128kHz-192kHz).
70 Depending on sample rate and channel format selected, not all pcm channels can
77 .Bl -tag -width indent
80 When opened in multi-channel audio software, this makes all ports available
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| /freebsd/contrib/file/magic/Magdir/ |
| H A D | playdate | 2 #------------------------------------------------------------------------------
8 # https://github.com/jaames/playdate-reverse-engineering
16 >12 belong&0x80 0x80 (compressed)
19 >12 belong&0x80 0x00 (uncompressed)
25 >12 belong&0x80 0x80 (compressed)
29 >12 belong&0x80 0x00 (uncompressed)
35 >12 belong&0x80 0x80 (compressed)
36 >12 belong&0x80 0x00 (uncompressed)
40 >12 lelong&0xffffff x %d Hz,
41 >15 byte 0 unsigned, 8-bit PCM, 1 channel
[all …]
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| H A D | sun | 2 #------------------------------------------------------------------------------
6 # Values for big-endian Sun (MC680x0, SPARC) binaries on pre-5.x
8 # architecture type, used before the 68020-based Sun-3's came out,
9 # are in aout, as they're indistinguishable from other big-endian
10 # 32-bit a.out files.
83 >>116 belong =12 (bad argument to system call)
97 # https://www.iana.org/assignments/snoop-datalink-types/snoop-datalink-types.xml,
101 >8 belong >0 - version %d
102 >12 belong 0 (IEEE 802.3)
103 >12 belong 1 (IEEE 802.4)
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | stm32mp157c-lxa-tac-gen1.dts | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
8 /dts-v1/;
11 #include "stm32mp15xc-lxa-tac.dtsi"
15 compatible = "lxa,stm32mp157c-tac-gen1", "oct,stm32mp15xx-osd32", "st,stm32mp157";
18 compatible = "pwm-backlight";
19 power-supply = <&v3v3>;
21 brightness-levels = <0 31 63 95 127 159 191 223 255>;
22 default-brightness-level = <7>;
26 reg_iobus_12v: regulator-iobus-12v {
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| H A D | stm32mp157c-lxa-tac-gen2.dts | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
8 /dts-v1/;
11 #include "stm32mp15xc-lxa-tac.dtsi"
15 compatible = "lxa,stm32mp157c-tac-gen2", "oct,stm32mp15xx-osd32", "st,stm32mp157";
18 compatible = "pwm-backlight";
19 power-supply = <&v3v3>;
21 brightness-levels = <0 31 63 95 127 159 191 223 255>;
22 default-brightness-level = <7>;
26 reg_iobus_12v: regulator-iobus-12v {
[all …]
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| H A D | stm32mp153c-lxa-tac-gen3.dts | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
8 /dts-v1/;
11 #include "stm32mp15xc-lxa-tac.dtsi"
15 compatible = "lxa,stm32mp153c-tac-gen3", "oct,stm32mp153x-osd32", "st,stm32mp153";
18 compatible = "pwm-backlight";
19 power-supply = <&v3v3>;
21 brightness-levels = <0 31 63 95 127 159 191 223 255>;
22 default-brightness-level = <7>;
26 reg_iobus_12v: regulator-iobus-12v {
[all …]
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| /freebsd/contrib/ofed/librdmacm/man/ |
| H A D | rdma_create_id.3 | 1 .\" Licensed under the OpenIB.org BSD license (FreeBSD Variant) - See COPYING.md
2 .TH "RDMA_CREATE_ID" 3 "2010-07-19" "librdmacm" "Librdmacm Programmer's Manual" librdmacm
4 rdma_create_id \- Allocate a communication identifier.
9 .BI "(struct rdma_event_channel *" channel ","
14 .IP "channel" 12
15 The communication channel that events associated with the
17 .IP "id" 12
20 .IP "context" 12
22 .IP "ps" 12
27 Returns 0 on success, or -1 on error. If an error occurs, errno will be
[all …]
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| H A D | rdma_migrate_id.3 | 1 .\" Licensed under the OpenIB.org BSD license (FreeBSD Variant) - See COPYING.md
2 .TH "RDMA_MIGRATE_ID" 3 "2007-11-13" "librdmacm" "Librdmacm Programmer's Manual" librdmacm
4 rdma_migrate_id \- Move a communication identifier to a different event channel.
10 .BI "struct rdma_event_channel *" channel ");"
12 .IP "id" 12
14 .IP "channel" 12
15 The communication channel that events associated with the
18 Migrates a communication identifier to a different event channel.
20 Returns 0 on success, or -1 on error. If an error occurs, errno will be
24 channel and moves any pending events associated with the rdma_cm_id
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| H A D | rdma_get_cm_event.3 | 1 .\" Licensed under the OpenIB.org BSD license (FreeBSD Variant) - See COPYING.md
2 .TH "RDMA_GET_CM_EVENT" 3 "2007-10-31" "librdmacm" "Librdmacm Programmer's Manual" librdmacm
4 rdma_get_cm_event \- Retrieves the next pending communication event.
9 .BI "(struct rdma_event_channel *" channel ","
12 .IP "channel" 12
13 Event channel to check for events.
14 .IP "event" 12
20 Returns 0 on success, or -1 on error. If an error occurs, errno will be
24 modifying the file descriptor associated with the given channel. All
33 .IP "id" 12
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| /freebsd/sys/contrib/dev/rtw88/ |
| H A D | rtw8821c.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
21 -20, -24, -28, -31, -34, -37, -40, -44};
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8821ce_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8821cu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8821cs_efuse_parsing()
50 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_read_efuse()
51 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_read_efuse()
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| H A D | rtw8822b.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8822be_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8822bu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8822bs_efuse_parsing()
43 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_read_efuse()
49 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7)); in rtw8822b_read_efuse()
50 efuse->rfe_option = map->rfe_option; in rtw8822b_read_efuse()
51 efuse->rf_board_option = map->rf_board_option; in rtw8822b_read_efuse()
52 efuse->crystal_cap = map->xtal_k; in rtw8822b_read_efuse()
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | ste-dma40.txt | 4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
19 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
[all …]
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| H A D | sirfsoc-dma.txt | 6 - compatible: Should be "sirf,prima2-dmac", "sirf,atlas7-dmac" or
7 "sirf,atlas7-dmac-v2"
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Should contain one interrupt shared by all channel
10 - #dma-cells: must be <1>. used to represent the number of integer
12 - clocks: clock required
17 dmac0: dma-controller@b00b0000 {
18 compatible = "sirf,prima2-dmac";
20 interrupts = <12>;
22 #dma-cells = <1>;
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| H A D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsso
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| H A D | ti-edma.txt | 3 The eDMA3 consists of two components: Channel controller (CC) and Transfer
5 responsible for the DMA channel handling, while the TCs are responsible to
8 ------------------------------------------------------------------------------
9 eDMA3 Channel Controller
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
17 channel controller(s) on 66AK2G.
18 - #dma-cells: Should be set to <2>. The first number is the DMA request
[all …]
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| H A D | snps-dma.txt | 4 - compatible: "snps,dma-spear1340"
5 - reg: Address range of the DMAC registers
6 - interrupt: Should contain the DMAC interrupt number
7 - dma-channels: Number of channels supported by hardware
8 - dma-requests: Number of DMA request lines supported, up to 16
9 - dma-masters: Number of AHB masters supported by the controller
10 - #dma-cells: must be <3>
11 - chan_allocation_order: order of allocation of channel, 0 (default): ascending,
13 - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
14 increase from chan n->0
[all …]
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| /freebsd/usr.sbin/virtual_oss/virtual_oss/ |
| H A D | virtual_oss.8 | 2 .\" Copyright (c) 2017-2022 Hans Petter Selasky <hselasky@freebsd.org>
52 All channel numbers start at zero.
53 Left channel is zero and right channel is one.
56 .Bl -tag -width indent
69 Set default sample-rate for the subsequent commands.
75 The buffer size specified is per channel.
78 Set real-time priority to
87 Valid values range from -63 to 63 inclusivly.
96 Valid values range from -63 to 63 inclusivly.
101 Valid values range from -63 to 63 inclusivly.
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| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | st,stm32-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
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| H A D | ti,ads7924.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI ADS7924 4 channels 12 bits I2C analog to digital converter
10 - Hugo Villeneuve <hvilleneuve@dimonoff.com>
13 Texas Instruments ADS7924 4 channels 12 bits I2C analog to digital converter
25 vref-supply:
29 reset-gpios:
35 "#address-cells":
38 "#size-cells":
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| /freebsd/sys/contrib/device-tree/Bindings/iio/dac/ |
| H A D | st,stm32-dac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/dac/st,stm32-dac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DAC is a 12-bit voltage output digital-to-analog converter. The DAC
11 may be configured in 8 or 12-bit mode. It has two output channels, each with
13 It has built-in noise and triangle waveform generator and supports external
18 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
23 - st,stm32f4-dac-core
24 - st,stm32h7-dac-core
[all …]
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| /freebsd/sys/contrib/dev/iwlwifi/ |
| H A D | iwl-fh.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2021, 2023-2025 Intel Corporation
4 * Copyright (C) 2015-2017 Intel Deutschland GmbH
12 #include "iwl-trans.h"
28 * Keep-Warm (KW) buffer base address.
31 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
33 * from going into a power-savings mode that would cause higher DRAM latency,
34 * and possible data over/under-runs, before all Tx/Rx is complete.
38 * automatically invokes keep-warm accesses when normal accesses might not
42 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | amlogic,meson-gpio-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/amlogic,meson-gpio-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiner Kallweit <hkallweit1@gmail.com>
15 a 256 pads to 8 or 12 GIC interrupt multiplexer, with a filter block to select
21 - $ref: /schemas/interrupt-controller.yaml#
26 - const: amlogic,meson-gpio-intc
27 - items:
28 - enum:
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/microchip/ |
| H A D | at91-tse850-3.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-tse850-3.dts - Device Tree file for the Axentia TSE-850 3.0 board
9 /dts-v1/;
10 #include <dt-bindings/pwm/pwm.h>
11 #include "at91-linea.dtsi"
14 model = "Axentia TSE-850 3.0";
19 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <16000000>;
23 clock-output-names = "sck";
[all …]
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