| /linux/drivers/iio/adc/ |
| H A D | max1363.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2008-2010 Jonathan Cameron
7 * Copyright (C) 2002-2004 Stefan Eletzhofer
53 /* think about including max11600 etc - more settings */
60 /* max1363 only - though don't care on others.
81 /* max123{6-9} only */
84 /* max1363 only - merely part of channel selects or don't care for others */
89 /* max1363 strictly 0x06 - but doesn't matter */
96 * struct max1363_mode - scan mode information
124 * struct max1363_chip_info - chip specifc information
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-yuv-planar.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. planar-yuv:
13 - Semi-planar formats use two planes. The first plane is the luma plane and
17 - Fully planar formats use three planes to store the Y, Cb and Cr components
27 and applications that support the multi-planar API, described in
28 :ref:`planar-apis`. Unless explicitly documented as supporting non-contiguous
32 Semi-Planar YUV Formats
47 For non-contiguous formats, no constraints are enforced by the format on the
50 All components are stored with the same number of bits per component.
58 .. flat-table:: Overview of Semi-Planar YUV Formats
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| H A D | pixfmt-srggb10p.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
4 .. _V4L2-PIX-FMT-SRGGB10P:
5 .. _v4l2-pix-fmt-sbggr10p:
6 .. _v4l2-pix-fmt-sgbrg10p:
7 .. _v4l2-pix-fmt-sgrbg10p:
17 10-bit packed Bayer formats
23 These four pixel formats are packed raw sRGB / Bayer formats with 10
24 bits per sample. Every four consecutive samples are packed into 5
25 bytes. Each of the first 4 bytes contain the 8 high order bits
27 bits of each pixel, in the same order.
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| /linux/arch/arm/mach-omap2/ |
| H A D | prcm-common.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
9 * Copyright (C) 2007-2009 Nokia Corporation
30 /* Chip-specific module offsets */
37 #define OMAP3430_IVA2_MOD -0x800
66 /* 24XX register bits shared between CM & PRM registers */
68 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
91 #define OMAP24XX_EN_GPT8_SHIFT 10
92 #define OMAP24XX_EN_GPT8_MASK (1 << 10)
108 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
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| /linux/arch/arc/include/asm/ |
| H A D | disasm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
32 #define BITS(word, s, e) (((word) >> (s)) & (~((-2) << ((e) - (s))))) macro
34 #define MAJOR_OPCODE(word) (BITS((word), 27, 31))
35 #define MINOR_OPCODE(word) (BITS((word), 16, 21))
36 #define FIELD_A(word) (BITS((word), 0, 5))
37 #define FIELD_B(word) ((BITS((word), 12, 14)<<3) | \
38 (BITS((word), 24, 26)))
39 #define FIELD_C(word) (BITS((word), 6, 11))
41 #define FIELD_s12(word) sign_extend(((BITS((word), 0, 5) << 6) | \
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| /linux/include/uapi/linux/usb/ |
| H A D | ch11.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
16 * From USB 2.0 spec Table 11-13, offset 7, a hub can
17 * have up to 255 ports. The most yet reported is 10.
24 /* See USB 3.1 spec Table 10-5 */
36 * See USB 3.1 spec Table 10-12
44 * See USB 2.0 spec Table 11-16
48 #define HUB_GET_TT_STATE 10
53 * See USB 3.0 spec Table 10-6
60 * See USB 2.0 spec Table 11-17
67 * See USB 2.0 spec Table 11-17
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| /linux/include/uapi/drm/ |
| H A D | drm_fourcc.h | 39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
143 /* 10 bpp Red (direct relationship between channel value and brightness) */
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| /linux/drivers/media/radio/si470x/ |
| H A D | radio-si470x.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * drivers/media/radio/si470x/radio-si470x.h
12 #define DRIVER_NAME "radio-si470x"
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ioctl.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-event.h>
28 #include <media/v4l2-device.h>
41 #define DEVICEID_PN 0xf000 /* bits 15..12: Part Number */
42 #define DEVICEID_MFGID 0x0fff /* bits 11..00: Manufacturer ID */
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| /linux/drivers/gpu/drm/exynos/ |
| H A D | regs-mixer.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Cloned from drivers/media/video/s5p-tv/regs-mixer.h
6 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
65 /* generates mask for range of bits */
67 (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))
72 /* bits for MXR_STATUS */
82 /* bits for MXR_CFG */
87 #define MXR_CFG_RGB601 (0 << 10)
88 #define MXR_CFG_RGB709 (1 << 10)
110 /* bits for MXR_VIDEO_CFG */
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| /linux/arch/x86/math-emu/ |
| H A D | README | 1 +---------------------------------------------------------------------------+
2 | wm-FPU-emu an FPU emulator for 80386 and 80486SX microprocessors. |
6 | Australia. E-mail billm@melbpc.org.au |
21 +---------------------------------------------------------------------------+
25 wm-FPU-emu is an FPU emulator for Linux. It is derived from wm-emu387
27 msdos); wm-emu387 was in turn based upon emu387 which was written by
31 My target FPU for wm-FPU-emu is that described in the Intel486
40 wm-FPU-emu does not implement all of the behaviour of the 80486 FPU,
52 --Bill Metzenthen
56 ----------------------- Internals of wm-FPU-emu -----------------------
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| /linux/drivers/net/ethernet/dec/tulip/ |
| H A D | pnic2.c | 5 Written/copyright 1994-2001 by Donald Becker.
15 /* Understanding the PNIC_II - everything is this file is based
18 * As I understand things, here are the registers and bits that
23 * CSR 6 (mask = 0xfe3bd1fd of bits not to change)
24 * -----
25 * Bit 24 - SCR
26 * Bit 23 - PCS
27 * Bit 22 - TTM (Trasmit Threshold Mode)
28 * Bit 18 - Port Select
29 * Bit 13 - Start - 1, Stop - 0 Transmissions
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| /linux/drivers/net/ipa/reg/ |
| H A D | ipa_reg-v5.5.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
6 #include <linux/bits.h>
32 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
39 /* Bits 17-18 reserved */
44 /* Bits 28-29 reserved */
62 [HPS_DPS_CMDQS] = BIT(10),
95 /* Bits 29-31 reserved */
110 /* Bits 8-31 reserved */
118 /* Bits 8-15 reserved */
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| H A D | ipa_reg-v4.2.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
6 #include <linux/bits.h>
23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
31 /* Bits 21-31 reserved */
47 [HPS_DPS_CMDQS] = BIT(10),
67 /* Bits 30-31 reserved */
78 /* Bits 22-23 reserved */
80 /* Bits 25-31 reserved */
95 /* Bits 8-31 reserved */
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| H A D | ipa_reg-v5.0.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
6 #include <linux/bits.h>
32 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
45 /* Bits 28-29 reserved */
63 [HPS_DPS_CMDQS] = BIT(10),
96 /* Bits 29-31 reserved */
111 /* Bits 8-31 reserved */
119 /* Bits 8-15 reserved */
126 /* Valid bits defined by ipa->available */
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| /linux/drivers/ras/amd/atl/ |
| H A D | reg_fields.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
28 * Rev Fieldname Bits
46 * Rev Fieldname Bits
69 * Rev Fieldname Bits
94 * Rev Fieldname Bits
119 * Rev Fieldname Bits
137 * Rev Fieldname Bits
158 * Rev Fieldname Bits
180 * Rev Fieldname Bits
199 * Rev Fieldname Bits
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| H A D | denormalize.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * denormalize.c : Functions to account for interleaving bits
22 case DF2: return FIELD_GET(DF2_DST_FABRIC_ID, ctx->map.limit); in get_dst_fabric_id()
23 case DF3: return FIELD_GET(DF3_DST_FABRIC_ID, ctx->map.limit); in get_dst_fabric_id()
24 case DF3p5: return FIELD_GET(DF3p5_DST_FABRIC_ID, ctx->map.limit); in get_dst_fabric_id()
25 case DF4: return FIELD_GET(DF4_DST_FABRIC_ID, ctx->map.ctl); in get_dst_fabric_id()
26 case DF4p5: return FIELD_GET(DF4p5_DST_FABRIC_ID, ctx->map.ctl); in get_dst_fabric_id()
34 * Make a contiguous gap in address for N bits starting at bit P.
37 * address bits: [20:0]
38 * # of interleave bits (n): 3
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| /linux/drivers/hwmon/pmbus/ |
| H A D | mp2888.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
27 #define MP2888_TEMP_UNIT 10
28 #define MP2888_MAX_PHASE 10
46 return -ENODATA; in mp2888_read_byte_data()
57 * , bits 0-2. The value is selected as below: in mp2888_current_sense_gain_and_resolution_get()
58 * 00b - 5µA/A, 01b - 8.5µA/A, 10b - 9.7µA/A, 11b - 10µA/A. Other in mp2888_current_sense_gain_and_resolution_get()
67 data->curr_sense_gain = 85; in mp2888_current_sense_gain_and_resolution_get()
70 data->curr_sense_gain = 97; in mp2888_current_sense_gain_and_resolution_get()
73 data->curr_sense_gain = 100; in mp2888_current_sense_gain_and_resolution_get()
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| /linux/drivers/net/ethernet/emulex/benet/ |
| H A D | be_hw.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
17 * it writes the register with hi=1 and the upper bits of the physical address
20 * bits in the address. It must poll the ready bit until the command is
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
90 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
127 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
128 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
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| /linux/include/rdma/ |
| H A D | opa_port_info.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright (c) 2014-2020 Intel Corporation. All rights reserved.
17 #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */
21 #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
22 #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
23 #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
24 #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
37 #define OPA_LINKDOWN_REASON_BAD_MID_TAIL 10
61 /* 34 -reserved */
64 /* 37-38 reserved */
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| /linux/arch/m68k/fpsp040/ |
| H A D | bindec.S | 12 | value in memory; d0 contains the k-factor sign-extended
13 | to 32-bits. The input may be either normalized,
18 | Saves and Modifies: D2-D7,A2,FP2
23 | The k-factor is saved for use in d7. Clear the
31 | ILOG is the log base 10 of the input value. It is
45 | k-factor can dictate either the total number of digits,
53 | SCALE is equal to 10^ISCALE, where ISCALE is the number
57 | 10^^(abs(ISCALE)) using a rounding mode which is a
64 | only one rounding error. The grs bits are collected in
67 | A9. Scale X -> Y.
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| H A D | do_func.S | 5 | to be performed is determined from the lower 7 bits of the
7 | The opcode and tag bits form an index into a jump table in
16 | functions can find FPTEMP at -12(a0).
51 MONE: .long 0xbfff0000,0x80000000,0x00000000 |-1
53 MZERO: .long 0x80000000,0x00000000,0x00000000 |-0
55 MINF: .long 0xffff0000,0x00000000,0x00000000 |-inf
56 QNAN: .long 0x7fff0000,0xffffffff,0xffffffff |non-signaling nan
58 MPIBY2: .long 0xbFFF0000,0xC90FDAA2,0x2168C235 |-PI/2
65 | unimplemented instructions. The test is on the upper 6 bits;
166 fmovemx (%a0),%fp0-%fp0
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| /linux/drivers/crypto/qce/ |
| H A D | regs-v5.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
105 /* Register bits - REG_VERSION */
113 /* Register bits - REG_STATUS */
126 #define CRYPTO_STATE_SHIFT 10
127 #define CRYPTO_STATE_MASK GENMASK(13, 10)
139 /* Register bits - REG_STATUS2 */
143 /* Register bits - REG_CONFIG */
156 #define REQ_SIZE_ENUM_11_BEAT 10
169 #define IRQ_ENABLES_SHIFT 10
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| /linux/drivers/net/ethernet/apple/ |
| H A D | mace.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * mace.h - definitions for the registers in the Am79C940 MACE
46 /* Bits in XMTFC */
49 #define AUTO_PAD_XMIT 0x01 /* auto-pad short packets on transmission */
51 /* Bits in XMTFS: only valid when XMTSV is set in PR and XMTFS */
53 #define UFLO 0x40 /* underflow - xmit fifo ran dry */
61 /* Bits in XMTRC: only valid when XMTSV is set in PR (and XMTFS) */
63 #define RETRY_MASK 0x0f /* number of retries (0 - 15) */
65 /* Bits in RCVFC */
68 #define AUTO_STRIP_RCV 0x01 /* auto-strip short LLC frames on recv */
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| /linux/drivers/net/wireless/zydas/zd1211rw/ |
| H A D | zd_rf_rf2959.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ZD1211 USB-WLAN driver for Linux
4 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
5 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
24 RF_CHANNEL(10) = { 0x181a09, 0x1e6666 },
32 static int bits(u32 rw, int from, int to)
41 return bits(rw, bit, bit);
46 int reg = bits(rw, 18, 22);
47 int rw_flag = bits(rw, 23, 23);
54 bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
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| /linux/arch/arm64/boot/dts/exynos/google/ |
| H A D | gs101.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include <dt-bindings/clock/google,gs101.h>
10 #include <dt-bindings/clock/google,gs101-acpm.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/samsung,exynos-usi.h>
17 #address-cells = <2>;
18 #size-cells = <1>;
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|