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/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7366.c26 DEFINE_RES_MEM(0xffe00000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0xc00)),
32 .id = 0,
41 [0] = {
43 .start = 0x04470000,
44 .end = 0x04470017,
48 .start = evt2irq(0xe00),
49 .end = evt2irq(0xe60),
56 .id = 0, /* "i2c0" clock */
66 [0] = {
[all …]
H A Dsetup-sh7343.c24 DEFINE_RES_MEM(0xffe00000, 0x100),
25 DEFINE_RES_IRQ(evt2irq(0xc00)),
30 .id = 0,
44 DEFINE_RES_MEM(0xffe10000, 0x100),
45 DEFINE_RES_IRQ(evt2irq(0xc20)),
64 DEFINE_RES_MEM(0xffe20000, 0x100),
65 DEFINE_RES_IRQ(evt2irq(0xc40)),
84 DEFINE_RES_MEM(0xffe30000, 0x100),
85 DEFINE_RES_IRQ(evt2irq(0xc60)),
99 [0] = {
[all …]
H A Dsetup-sh7723.c33 DEFINE_RES_MEM(0xffe00000, 0x100),
34 DEFINE_RES_IRQ(evt2irq(0xc00)),
39 .id = 0,
54 DEFINE_RES_MEM(0xffe10000, 0x100),
55 DEFINE_RES_IRQ(evt2irq(0xc20)),
75 DEFINE_RES_MEM(0xffe20000, 0x100),
76 DEFINE_RES_IRQ(evt2irq(0xc40)),
95 DEFINE_RES_MEM(0xa4e30000, 0x100),
96 DEFINE_RES_IRQ(evt2irq(0x900)),
115 DEFINE_RES_MEM(0xa4e40000, 0x100),
[all …]
H A Dsetup-sh7722.c30 .addr = 0xffe0000c,
32 .mid_rid = 0x21,
35 .addr = 0xffe00014,
37 .mid_rid = 0x22,
40 .addr = 0xffe1000c,
42 .mid_rid = 0x25,
45 .addr = 0xffe10014,
47 .mid_rid = 0x26,
50 .addr = 0xffe2000c,
52 .mid_rid = 0x29,
[all …]
H A Dsetup-sh7724.c37 .addr = 0xffe0000c,
39 .mid_rid = 0x21,
42 .addr = 0xffe00014,
44 .mid_rid = 0x22,
47 .addr = 0xffe1000c,
49 .mid_rid = 0x25,
52 .addr = 0xffe10014,
54 .mid_rid = 0x26,
57 .addr = 0xffe2000c,
59 .mid_rid = 0x29,
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]