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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmarvell-pp2.txt50 "hifX", with X in [0..8], and "link". The names "tx-cpu0",
60 reg = <0xf0000 0xa000>,
61 <0xc0000 0x3060>,
62 <0xc4000 0x100>,
63 <0xc5000 0x100>;
69 port-id = <0>;
84 cpm_ethernet: ethernet@0 {
86 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
104 port-id = <0>;
105 gop-port-id = <0>;
H A Dmarvell,pp2.yaml32 const: 0
59 '^(ethernet-)?port@[0-2]$':
92 "hifX", with X in [0..8], and "link". The names "tx-cpu0",
165 '^(ethernet-)?port@[0-2]$':
187 '^(ethernet-)?port@[0-1]$':
204 #size-cells = <0>;
206 reg = <0xf0000 0xa000>,
207 <0xc0000 0x3060>,
208 <0xc4000 0x100>,
209 <0xc5000 0x100>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-375.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
/freebsd/sys/dev/bxe/
H A Dbxe_dump.h33 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
34 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
35 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
36 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
56 #define BNX2X_DUMP_VERSION 0x61111111
76 static const uint32_t page_vals_e2[] = {0, 128};
79 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
85 static const uint32_t page_vals_e3[] = {0, 128};
88 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
92 { 0x2000, 1, 0x1f, 0xfff},
[all …]
H A D57712_init_values.c54 /* #define ATC_COMMON_START 0 */
55 {OP_WR, 0x1100b8, 0x1},
58 {OP_WR, 0x600dc, 0x1},
59 {OP_WR, 0x60050, 0x180},
60 {OP_SW, 0x61000, 0x1ff0000},
61 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
62 {OP_WR, 0x617fc, 0x3fe001},
63 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
64 {OP_SW, 0x617fc, 0x20101ff},
65 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
[all …]
H A D57711_init_values.c55 {OP_WR, 0x600dc, 0x1},
56 {OP_SW, 0x61000, 0x2000000},
57 {OP_RD, 0x600d8, 0x0},
58 {OP_SW, 0x60200, 0x30200},
59 {OP_WR, 0x600dc, 0x0},
62 {OP_RD, 0x600b8, 0x0},
63 {OP_RD, 0x600c8, 0x0},
64 {OP_WR, 0x6016c, 0x0},
67 {OP_RD, 0x600bc, 0x0},
68 {OP_RD, 0x600cc, 0x0},
[all …]
H A D57710_init_values.c55 {OP_WR, 0x600dc, 0x1},
56 {OP_SW, 0x61000, 0x2000000},
57 {OP_RD, 0x600d8, 0x0},
58 {OP_SW, 0x60200, 0x30200},
59 {OP_WR, 0x600dc, 0x0},
62 {OP_WR, 0x60068, 0xb8},
63 {OP_WR, 0x60078, 0x114},
64 {OP_RD, 0x600b8, 0x0},
65 {OP_RD, 0x600c8, 0x0},
68 {OP_WR, 0x6006c, 0xb8},
[all …]