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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Damlogic,meson8-pinctrl-cbus.yaml32 "^bank@[0-9a-z]+$":
65 reg = <0x80b0 0x28>,
66 <0x80e8 0x18>,
67 <0x8120 0x18>,
68 <0x8030 0x3
[all...]
/freebsd/sys/dev/pci/
H A Dpci_dw_mv.c61 #define MV_GLOBAL_CONTROL_REG 0x8000
64 #define MV_GLOBAL_STATUS_REG 0x8008
68 #define MV_INT_CAUSE1 0x801C
69 #define MV_INT_MASK1 0x8020
75 #define MV_INT_CAUSE2 0x8024
76 #define MV_INT_MASK2 0x8028
77 #define MV_ERR_INT_CAUSE 0x802C
78 #define MV_ERR_INT_MASK 0x8030
80 #define MV_ARCACHE_TRC_REG 0x8050
81 #define MV_AWCACHE_TRC_REG 0x8054
[all …]
/freebsd/sys/dev/bhnd/cores/pci/
H A Dbhnd_pcireg.h32 #define BHND_PCI_DMA32_TRANSLATION 0x40000000 /**< PCI DMA32 address translation (sbtopci2) */
35 #define BHND_PCIE_DMA32_TRANSLATION 0x80000000 /**< PCIe-Gen1 DMA32 address translation (sb2pcitr…
45 #define BHND_PCI_CTL 0x000 /**< PCI core control*/
46 #define BHND_PCI_ARB_CTL 0x010 /**< PCI arbiter control */
47 #define BHND_PCI_CLKRUN_CTL 0x014 /**< PCI clckrun control (>= rev11) */
48 #define BHND_PCI_INTR_STATUS 0x020 /**< Interrupt status */
49 #define BHND_PCI_INTR_MASK 0x024 /**< Interrupt mask */
50 #define BHND_PCI_SBTOPCI_MBOX 0x028 /**< Sonics to PCI mailbox */
51 #define BHND_PCI_BCAST_ADDR 0x050 /**< Sonics broadcast address (pci) */
52 #define BHND_PCI_BCAST_DATA 0x054 /**< Sonics broadcast data (pci) */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h28 #define PCI_VENDOR_ATHEROS 0x168c
30 #define PCI_PRODUCT_ATHEROS_AR5210 0x0007
31 #define PCI_PRODUCT_ATHEROS_AR5210_OLD 0x0004
34 #define AR_TXDP0 0x0000 /* TX queue pointer 0 register */
35 #define AR_TXDP1 0x0004 /* TX queue pointer 1 register */
36 #define AR_CR 0x0008 /* Command register */
37 #define AR_RXDP 0x000c /* RX queue descriptor ptr register */
38 #define AR_CFG 0x0014 /* Configuration and status register */
39 #define AR_ISR 0x001c /* Interrupt status register */
40 #define AR_IMR 0x0020 /* Interrupt mask register */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/amlogic/
H A Dmeson8b.dtsi19 #size-cells = <0>;
25 reg = <0x200>;
37 reg = <0x201>;
49 reg = <0x202>;
61 reg = <0x203>;
169 hwrom@0 {
170 reg = <0x0 0x200000>;
225 reg = <0xc8000000 0x8000>;
228 ranges = <0x0 0xc8000000 0x8000>;
232 reg = <0x400 0x20>;
[all …]
H A Dmeson8.dtsi21 #size-cells = <0>;
27 reg = <0x200>;
39 reg = <0x201>;
51 reg = <0x202>;
63 reg = <0x203>;
177 hwrom@0 {
178 reg = <0x0 0x200000>;
193 reg = <0x4f00000 0x100000>;
248 reg = <0xc8000000 0x8000>;
251 ranges = <0x0 0xc8000000 0x8000>;
[all …]
/freebsd/share/i18n/csmapper/GB/
H A DISO-IR-165EXT%UCS.src5 SRC_ZONE 0x26-0x7E / 0x21-0x7E / 8
7 DST_INVALID 0xFFFE
20 # Unicode version: 5.0.0
56 #0x265C - 0x2671 = 0xFFFD
59 0x283B = 0x0251
60 0x283C = 0xE7C7
61 0x283D = 0x0144
62 0x283E = 0x0148
63 0x283F = 0x01F9 # 0xE7C8
64 0x2840 = 0x0261
[all …]
H A DUCS%ISO-IR-165EXT.src5 SRC_ZONE 0x0021-0xE7C8
7 DST_INVALID 0xFFFF
20 # Unicode version: 5.0.0
56 #0x0021 = 0x2A21
57 #0x0022 = 0x2A22
58 #0x0023 = 0x2A23
59 #0x0025 = 0x2A25
60 #0x0026 = 0x2A26
61 #0x0027 = 0x2A27
62 #0x0028 = 0x2A28
[all …]
/freebsd/sys/dev/isp/
H A Dispmbox.h41 #define MBOX_NO_OP 0x0000
42 #define MBOX_LOAD_RAM 0x0001
43 #define MBOX_EXEC_FIRMWARE 0x0002
44 #define MBOX_LOAD_FLASH_FIRMWARE 0x0003
45 #define MBOX_WRITE_RAM_WORD 0x0004
46 #define MBOX_READ_RAM_WORD 0x0005
47 #define MBOX_MAILBOX_REG_TEST 0x0006
48 #define MBOX_VERIFY_CHECKSUM 0x0007
49 #define MBOX_ABOUT_FIRMWARE 0x0008
50 #define MBOX_LOAD_RISC_RAM_2100 0x0009
[all …]
/freebsd/share/i18n/csmapper/CP/
H A DCP932UDA%UCS.src5 SRC_ZONE 0x7F-0x92 / 0x21-0x7E / 8
7 DST_INVALID 0xFFFE
27 # Column #2 is the Unicode (in hex as 0xXXXX)
32 0x7F21 = 0xE000
33 0x7F22 = 0xE001
34 0x7F23 = 0xE002
35 0x7F24 = 0xE003
36 0x7F25 = 0xE004
37 0x7F26 = 0xE005
38 0x7F27 = 0xE006
[all …]
H A DUCS%CP932UDA.src5 SRC_ZONE 0xE000-0xE757
7 DST_INVALID 0xFFFF
27 # Column #2 is the Unicode (in hex as 0xXXXX)
32 0xE000 = 0x7F21
33 0xE001 = 0x7F22
34 0xE002 = 0x7F23
35 0xE003 = 0x7F24
36 0xE004 = 0x7F25
37 0xE005 = 0x7F26
38 0xE006 = 0x7F27
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211reg.h32 #define AR_CR 0x0008 /* control register */
33 #define AR_RXDP 0x000C /* receive queue descriptor pointer */
34 #define AR_CFG 0x0014 /* configuration and status register */
35 #define AR_IER 0x0024 /* Interrupt enable register */
36 #define AR_RTSD0 0x0028 /* RTS Duration Parameters 0 */
37 #define AR_RTSD1 0x002c /* RTS Duration Parameters 1 */
38 #define AR_TXCFG 0x0030 /* tx DMA size config register */
39 #define AR_RXCFG 0x0034 /* rx DMA size config register */
40 #define AR5211_JUMBO_LAST 0x0038 /* Jumbo descriptor last address */
41 #define AR_MIBC 0x0040 /* MIB control register */
[all …]
/freebsd/share/i18n/csmapper/JIS/
H A DJISX0213-2%UCS@BMP.src5 SRC_ZONE 0x21-0x7E / 0x21-0x7E / 8
7 DST_INVALID 0xFFFE
34 0x2122 = 0x4E02
35 0x2123 = 0x4E0F
36 0x2124 = 0x4E12
37 0x2125 = 0x4E29
38 0x2126 = 0x4E2B
39 0x2127 = 0x4E2E
40 0x2128 = 0x4E40
41 0x2129 = 0x4E47
[all …]
H A DUCS@BMP%JISX0213-2.src5 SRC_ZONE 0x3406 - 0xFA66
7 DST_INVALID 0xFFFF
30 0x3406 = 0x212D
31 0x342C = 0x2132
32 0x342E = 0x2133
33 0x3468 = 0x215E
34 0x346A = 0x2156
35 0x3492 = 0x217E
36 0x34BC = 0x232B
37 0x34C1 = 0x7468
[all …]
H A DUCS%JISX0212@MS.src5 SRC_ZONE 0x0000 - 0xFFFF
7 DST_INVALID 0xFFFF
11 0x0000 - 0xFFFF = INVALID
15 0x00A1 = 0x2242
16 0x00A4 = 0x2270
17 0x00A9 = 0x226D
18 0x00AA = 0x226C
19 0x00AE = 0x226E
20 0x00AF = 0x2234
21 0x00B8 = 0x2231
[all …]
H A DJISX0212@MS%UCS.src5 SRC_ZONE 0x21-0x7E / 0x21-0x7E / 8
7 DST_ILSEQ 0xFFFE
14 0x222F = 0x02D8
15 0x2230 = 0x02C7
16 0x2231 = 0x00B8
17 0x2232 = 0x02D9
18 0x2233 = 0x02DD
19 0x2234 = 0x00AF
20 0x2235 = 0x02DB
21 0x2236 = 0x02DA
[all …]
H A DJISX0212%UCS.src5 SRC_ZONE 0x21-0x7E / 0x21-0x7E / 8
7 DST_ILSEQ 0xFFFE
57 # Column #1 is the JIS X 0212 code (in hex as 0xXXXX)
58 # Column #2 is the Unicode (in hex as 0xXXXX)
73 # To change hex to EUC form, add 0x8080
74 # To change hex to kuten form, first subtract 0x2020. Then
76 # the kuten form. For example, 0x2121 -> 0x0101 -> 0101;
77 # 0x6D63 -> 0x4D43 -> 7767
88 # into a single character at 0x2922:
94 # the lowercase forms of these two elements at 0x2942 and 0x2943.
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212reg.h27 #define AR_CR 0x0008 /* MAC control register */
28 #define AR_RXDP 0x000C /* MAC receive queue descriptor pointer */
29 #define AR_CFG 0x0014 /* MAC configuration and status register */
30 #define AR_IER 0x0024 /* MAC Interrupt enable register */
31 /* 0x28 is RTSD0 on the 5211 */
32 /* 0x2c is RTSD1 on the 5211 */
33 #define AR_TXCFG 0x0030 /* MAC tx DMA size config register */
34 #define AR_RXCFG 0x0034 /* MAC rx DMA size config register */
35 /* 0x38 is the jumbo descriptor address on the 5211 */
36 #define AR_MIBC 0x0040 /* MAC MIB control register */
[all …]
/freebsd/share/man/man4/
H A Diwlwififw.460 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4070 Ta iwlwifi-7260
63 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4072 Ta iwlwifi-7260
66 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4170 Ta iwlwifi-7260
69 .It 0x808
[all...]
/freebsd/sys/dev/qlxgbe/
H A Dql_os.c50 #define PCI_VENDOR_QLOGIC 0x1077
54 #define PCI_PRODUCT_QLOGIC_ISP8030 0x8030
109 { 0, 0 }
116 DRIVER_MODULE(qla83xx, pci, qla_pci_driver, 0, 0);
123 #define QL_STD_REPLENISH_THRES 0
165 ver_str, 0, "Driver Version"); in qla_add_sysctls()
170 ha->fw_ver_str, 0, "firmware version"); in qla_add_sysctls()
175 (void *)ha, 0, qla_sysctl_get_link_status, "I", "Link Status"); in qla_add_sysctls()
177 ha->dbg_level = 0; in qla_add_sysctls()
266 ha->qla_watchdog_exited = 0; in qla_watchdog()
[all …]
/freebsd/sys/contrib/dev/iwlwifi/pcie/
H A Ddrv.c23 #define TRANS_CFG_MARKER BIT(0)
30 __builtin_choose_expr(_IS_A(cfg, iwl_cfg), 0, _invalid_type)))
41 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
42 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
43 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
44 {IWL_PCI_DEVICE(0x4232, 0x130
[all...]
/freebsd/lib/libpmc/pmu-events/arch/x86/nehalemep/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/westmereex/
H A Dcache.json4 "Counter": "0,1",
5 "EventCode": "0x63",
8 "UMask": "0x2"
12 "Counter": "0,1",
13 "EventCode": "0x63",
16 "UMask": "0x1"
20 "Counter": "0,1",
21 "EventCode": "0x51",
24 "UMask": "0x4"
28 "Counter": "0,1",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/nehalemex/
H A Dcache.json3 "EventCode": "0x63",
4 "Counter": "0,1",
5 "UMask": "0x2",
11 "EventCode": "0x63",
12 "Counter": "0,1",
13 "UMask": "0x1",
19 "EventCode": "0x51",
20 "Counter": "0,1",
21 "UMask": "0x4",
27 "EventCode": "0x51",
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300reg.h34 #define AR_CR_LP_RXE 0x00000004 // Receive LPQ enable
35 #define AR_CR_HP_RXE 0x00000008 // Receive HPQ enable
36 #define AR_CR_RXD 0x00000020 // Receive disable
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
42 #define AR_CFG_SWTD 0x00000001 // byteswap tx descriptor words
43 #define AR_CFG_SWTB 0x00000002 // byteswap tx data buffer words
44 #define AR_CFG_SWRD 0x00000004 // byteswap rx descriptor words
45 #define AR_CFG_SWRB 0x00000008 // byteswap rx data buffer words
46 #define AR_CFG_SWRG 0x00000010 // byteswap register access data words
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
[all …]

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