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/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_tpc0_eml_busmon_0_regs.h23 #define mmDCORE0_TPC0_EML_BUSMON_0_CR 0x7000
25 #define mmDCORE0_TPC0_EML_BUSMON_0_REG_RESET 0x7004
27 #define mmDCORE0_TPC0_EML_BUSMON_0_INT_CLR 0x7008
29 #define mmDCORE0_TPC0_EML_BUSMON_0_TRIG_TH 0x700C
31 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S0 0x7020
33 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S0 0x7024
35 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_E0 0x7028
37 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_E0 0x702C
39 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRL_S1 0x7030
41 #define mmDCORE0_TPC0_EML_BUSMON_0_ADDRH_S1 0x7034
[all …]
/linux/sound/soc/codecs/
H A Dcx2072x.h19 #define CX2072X_REG_MAX 0x8a3c
21 #define CX2072X_VENDOR_ID 0x0200
22 #define CX2072X_REVISION_ID 0x0208
23 #define CX2072X_CURRENT_BCLK_FREQUENCY 0x00dc
24 #define CX2072X_AFG_POWER_STATE 0x0414
25 #define CX2072X_UM_RESPONSE 0x0420
26 #define CX2072X_GPIO_DATA 0x0454
27 #define CX2072X_GPIO_ENABLE 0x0458
28 #define CX2072X_GPIO_DIRECTION 0x045c
29 #define CX2072X_GPIO_WAKE 0x0460
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dregs-hdmi.h20 #define HDMI_CTRL_BASE(x) ((x) + 0x00000000)
21 #define HDMI_CORE_BASE(x) ((x) + 0x00010000)
22 #define HDMI_I2S_BASE(x) ((x) + 0x00040000)
23 #define HDMI_TG_BASE(x) ((x) + 0x00050000)
26 #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000)
27 #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004)
28 #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C)
29 #define HDMI_V13_PHY_RSTOUT HDMI_CTRL_BASE(0x0014)
30 #define HDMI_V13_PHY_VPLL HDMI_CTRL_BASE(0x0018)
31 #define HDMI_V13_PHY_CMU HDMI_CTRL_BASE(0x001C)
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/linux/drivers/scsi/qla2xxx/
H A Dqla_sup.c35 wrt_reg_word(&reg->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access()
39 while ((data & BIT_0) == 0) { in qla2x00_lock_nvram_access()
42 wrt_reg_word(&reg->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access()
60 wrt_reg_word(&reg->u.isp2300.host_semaphore, 0); in qla2x00_unlock_nvram_access()
98 * Bit 15-0 = write data
107 uint16_t data = 0; in qla2x00_nvram_request()
112 for (cnt = 0; cnt < 11; cnt++) { in qla2x00_nvram_request()
116 qla2x00_nv_write(ha, 0); in qla2x00_nvram_request()
121 for (cnt = 0; cnt < 16; cnt++) { in qla2x00_nvram_request()
194 qla2x00_nv_write(ha, 0); in qla2x00_write_nvram_word()
[all …]
H A Dqla_dbg.c13 * | Module Init and Probe | 0x0199 | |
14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff |
15 * | Device Discovery | 0x2134 | 0x2112-0x2115 |
16 * | | | 0x2127-0x2128 |
17 * | Queue Command and IO tracing | 0x3074 | 0x300b |
18 * | | | 0x3027-0x3028 |
19 * | | | 0x303d-0x3041 |
20 * | | | 0x302e,0x3033 |
21 * | | | 0x3036,0x3038 |
22 * | | | 0x303a |
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi36 #clock-cells = <0>;
43 #clock-cells = <0>;
51 #size-cells = <0>;
56 reg = <0x0 0x100>;
76 reg = <0x0 0x101>;
91 reg = <0x0 0x102>;
106 reg = <0x0 0x103>;
118 cpu4: cpu@0 {
121 reg = <0x0 0x0>;
141 reg = <0x0 0x1>;
[all …]
/linux/drivers/gpu/drm/radeon/
H A Devergreend.h33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
[all …]
/linux/fs/nls/
H A Dnls_cp936.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x4E02,0x4E04,0x4E05,0x4E06,0x4E0F,0x4E12,0x4E17,0x4E1F,/* 0x40-0x47 */
26 0x4E20,0x4E21,0x4E23,0x4E26,0x4E29,0x4E2E,0x4E2F,0x4E31,/* 0x48-0x4F */
[all …]