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/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Demev2.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
34 reg = <0>;
49 reg = <0xe0028000 0x1000>,
50 <0xe0020000 0x0100>;
62 reg = <0xe0110000 0x10000>;
64 #size-cells = <0>;
69 #clock-cells = <0>;
71 iic0_sclkdiv: iic0_sclkdiv@624,0 {
73 reg = <0x624 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra72x-mmc-iodelay.dtsi37 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
38 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
39 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
40 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
41 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
42 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
48 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
49 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
50 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
51 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Ddra74x-mmc-iodelay.dtsi35 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
36 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
37 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
38 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
39 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
40 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
46 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
47 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
48 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
49 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Ddra76x-mmc-iodelay.dtsi32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imx35-pinctrl.yaml74 PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13)
78 PAD_CTL_PUS_100K_DOWN (0 << 4)
82 PAD_CTL_ODE_CMOS (0 << 3)
84 PAD_CTL_DSE_NOMINAL (0 << 1)
87 PAD_CTL_SRE_FAST (1 << 0)
88 PAD_CTL_SRE_SLOW (0 << 0)
94 PAD_CTL_PUS_100K_DOWN (0 << 4)
99 PAD_CTL_DSE_LOW (0 << 1)
103 PAD_CTL_SRE_FAST (1 << 0)
104 PAD_CTL_SRE_SLOW (0 << 0)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-apq8064-asus-nexus7-flo.dts6 #include "qcom-apq8064-v2.0.dtsi"
31 reg = <0x88d00000 0x100000>;
32 record-size = <0x00020000>;
33 console-size = <0x00020000>;
34 ftrace-size = <0x00020000>;
43 startup-delay-us = <0>;
66 reg = <0x2a03f000 0x1000>;
70 offset = <0x65c>;
72 mode-normal = <0x77665501>;
73 mode-bootloader = <0x77665500>;
[all …]
H A Dqcom-msm8226.dtsi28 #clock-cells = <0>;
34 #clock-cells = <0>;
41 #size-cells = <0>;
43 cpu0: cpu@0 {
47 reg = <0>;
110 memory@0 {
112 reg = <0x0 0x0>;
161 mboxes = <&apcs 0>;
213 reg = <0x3000000 0x100000>;
218 reg = <0x08000000 0x5100000>;
[all …]
H A Dqcom-msm8974.dtsi23 #clock-cells = <0>;
29 #clock-cells = <0>;
36 #size-cells = <0>;
39 cpu0: cpu@0 {
43 reg = <0>;
109 memory@0 {
111 reg = <0x0 0x0>;
136 mboxes = <&apcs 0>;
159 reg = <0x08000000 0x5100000>;
164 reg = <0x0d100000 0x100000>;
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_car.h38 #define RST_DEVICES_L 0x004
39 #define RST_DEVICES_H 0x008
40 #define RST_DEVICES_U 0x00C
41 #define CLK_OUT_ENB_L 0x010
42 #define CLK_OUT_ENB_H 0x014
43 #define CLK_OUT_ENB_U 0x018
44 #define CCLK_BURST_POLICY 0x020
45 #define SUPER_CCLK_DIVIDER 0x024
46 #define SCLK_BURST_POLICY 0x028
47 #define SUPER_SCLK_DIVIDER 0x02c
[all …]
/freebsd/sys/dev/usb/net/
H A Dif_mugereg.h40 #define UVR_WRITE_REG 0xA0
41 #define UVR_READ_REG 0xA1
42 #define UVR_GET_STATS 0xA2
45 #define ETH_ID_REV 0x000
46 #define ETH_ID_REV_CHIP_ID_MASK_ 0xFFFF0000UL
47 #define ETH_ID_REV_CHIP_REV_MASK_ 0x0000FFFFUL
48 #define ETH_ID_REV_CHIP_ID_7800_ 0x7800
49 #define ETH_ID_REV_CHIP_ID_7801_ 0x7801
50 #define ETH_ID_REV_CHIP_ID_7850_ 0x7850
53 #define ETH_INT_STS 0x00C
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_car.h39 #define RST_SOURCE 0x000
40 #define RST_DEVICES_L 0x004
41 #define RST_DEVICES_H 0x008
42 #define RST_DEVICES_U 0x00C
43 #define CLK_OUT_ENB_L 0x010
44 #define CLK_OUT_ENB_H 0x014
45 #define CLK_OUT_ENB_U 0x018
46 #define SUPER_CCLK_DIVIDER 0x024
47 #define SCLK_BURST_POLICY 0x028
48 #define SUPER_SCLK_DIVIDER 0x02c
[all …]
/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmureg.h29 (((_value) & _flag) != 0)
43 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
55 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
56 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
57 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
58 #define BHND_CCS_FORCE_MASK 0x0000000F
60 #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
61 #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
62 #define BHND_CCS_AREQ_MASK 0x00000018
64 #define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */
[all …]
/freebsd/sys/dev/ti/
H A Dif_tireg.h45 #define TI_PCI_ID 0x000 /* PCI device/vendor ID */
46 #define TI_PCI_CMDSTAT 0x004
47 #define TI_PCI_CLASSCODE 0x008
48 #define TI_PCI_BIST 0x00C
49 #define TI_PCI_LOMEM 0x010 /* Shared memory base address */
50 #define TI_PCI_SUBSYS 0x02C
51 #define TI_PCI_ROMBASE 0x030
52 #define TI_PCI_INT 0x03C
55 #define PCIM_CMD_MWIEN 0x0010
61 #define ALT_VENDORID 0x12AE
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dregs.h130 #define MT_MCU_WFDMA0_BASE 0x2000
133 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
136 #define MT_MCU_WFDMA1_BASE 0x3000
140 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
146 #define MT_PLE_BASE 0x820c0000
149 #define MT_PLE_HOST_RPT0 MT_PLE(0x030)
154 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
155 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
165 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
167 #define MT_PSE_BASE 0x820c8000
[all …]
/freebsd/tools/tools/cxgbtool/
H A Dreg_defs_t3.c8 { "SG_CONTROL", 0x0, 0 },
22 { "GlobalEnable", 0, 1 },
23 { "SG_KDOORBELL", 0x4, 0 },
25 { "EgrCntx", 0, 16 },
26 { "SG_GTS", 0x8, 0 },
29 { "NewIndex", 0, 16 },
30 { "SG_CONTEXT_CMD", 0xc, 0 },
38 { "Context", 0, 16 },
39 { "SG_CONTEXT_DATA0", 0x10, 0 },
40 { "SG_CONTEXT_DATA1", 0x14, 0 },
[all …]
H A Dreg_defs_t3b.c7 { "SG_CONTROL", 0x0, 0 },
26 { "GlobalEnable", 0, 1 },
27 { "SG_KDOORBELL", 0x4, 0 },
29 { "EgrCntx", 0, 16 },
30 { "SG_GTS", 0x8, 0 },
33 { "NewIndex", 0, 16 },
34 { "SG_CONTEXT_CMD", 0xc, 0 },
42 { "Context", 0, 16 },
43 { "SG_CONTEXT_DATA0", 0x10, 0 },
44 { "SG_CONTEXT_DATA1", 0x14, 0 },
[all …]
H A Dreg_defs_t3c.c7 { "SG_CONTROL", 0x0, 0 },
29 { "GlobalEnable", 0, 1 },
30 { "SG_KDOORBELL", 0x4, 0 },
32 { "EgrCntx", 0, 16 },
33 { "SG_GTS", 0x8, 0 },
36 { "NewIndex", 0, 16 },
37 { "SG_CONTEXT_CMD", 0xc, 0 },
45 { "Context", 0, 16 },
46 { "SG_CONTEXT_DATA0", 0x10, 0 },
47 { "SG_CONTEXT_DATA1", 0x14, 0 },
[all …]

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