/linux/arch/powerpc/boot/dts/fsl/ |
H A D | qoriq-fman3-1.dtsi | 2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x500000 ] 40 ranges = <0 0x500000 0xfe000>; 41 reg = <0x500000 0xfe000>; 42 interrupts = <97 2 0 0>, <16 2 1 0>; 45 fsl,qman-channel-range = <0x820 0x10>; 48 muram@0 { 50 reg = <0x0 0x60000>; 54 cell-index = <0x2>; 56 reg = <0x82000 0x1000>; 60 cell-index = <0x3>; [all …]
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H A D | qoriq-fman-1.dtsi | 2 * QorIQ FMan device tree stub [ controller @ offset 0x500000 ] 40 ranges = <0 0x500000 0xfe000>; 41 reg = <0x500000 0xfe000>; 42 interrupts = <97 2 0 0>, <16 2 1 0>; 45 fsl,qman-channel-range = <0x60 0xc>; 48 muram@0 { 50 reg = <0x0 0x28000>; 54 cell-index = <0x1>; 56 reg = <0x81000 0x1000>; 60 cell-index = <0x2>; [all …]
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H A D | qoriq-fman-1-10g-0.dtsi | 2 * QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x500000 ] 37 cell-index = <0x10>; 39 reg = <0x90000 0x1000>; 43 cell-index = <0x30>; 45 reg = <0xb0000 0x1000>; 49 cell-index = <0x8>; 51 reg = <0xf0000 0x1000>; 57 #size-cells = <0>; 59 reg = <0xf1000 0x1000>;
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H A D | qoriq-fman3-1-1g-0.dtsi | 2 * QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x500000 ] 37 cell-index = <0x8>; 39 reg = <0x88000 0x1000>; 43 cell-index = <0x28>; 45 reg = <0xa8000 0x1000>; 49 cell-index = <0>; 51 reg = <0xe0000 0x1000>; 60 #size-cells = <0>; 62 reg = <0xe1000 0x1000>; 65 pcsphy8: ethernet-phy@0 { [all …]
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H A D | qoriq-fman-1-1g-0.dtsi | 2 * QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x500000 ] 37 cell-index = <0x8>; 39 reg = <0x88000 0x1000>; 43 cell-index = <0x28>; 45 reg = <0xa8000 0x1000>; 49 cell-index = <0>; 51 reg = <0xe0000 0x1000>; 59 #size-cells = <0>; 61 reg = <0xe1120 0xee0>; 64 reg = <0x8>;
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H A D | qoriq-fman3-1-1g-4.dtsi | 2 * QorIQ FMan v3 1g port #4 device tree stub [ controller @ offset 0x500000 ] 37 cell-index = <0xc>; 39 reg = <0x8c000 0x1000>; 43 cell-index = <0x2c>; 45 reg = <0xac000 0x1000>; 51 reg = <0xe8000 0x1000>; 60 #size-cells = <0>; 62 reg = <0xe9000 0x1000>; 65 pcsphy12: ethernet-phy@0 { 66 reg = <0x0>;
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H A D | qoriq-fman-1-1g-1.dtsi | 2 * QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x500000 ] 37 cell-index = <0x9>; 39 reg = <0x89000 0x1000>; 43 cell-index = <0x29>; 45 reg = <0xa9000 0x1000>; 51 reg = <0xe2000 0x1000>; 59 #size-cells = <0>; 61 reg = <0xe3120 0xee0>; 64 reg = <0x8>;
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H A D | qoriq-fman-1-1g-3.dtsi | 2 * QorIQ FMan 1g port #3 device tree stub [ controller @ offset 0x500000 ] 37 cell-index = <0xb>; 39 reg = <0x8b000 0x1000>; 43 cell-index = <0x2b>; 45 reg = <0xab000 0x1000>; 51 reg = <0xe6000 0x1000>; 59 #size-cells = <0>; 61 reg = <0xe7120 0xee0>; 64 reg = <0x8>;
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/linux/arch/arm/boot/dts/marvell/ |
H A D | kirkwood-dnskw.dtsi | 11 pinctrl-0 = <&pmx_button_power &pmx_button_unmount 35 pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; 39 gpio-fan,speed-map = <0 0>, 46 pinctrl-0 = <&pmx_power_off>; 54 pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 145 pinctrl-0 = <&pmx_sata0 &pmx_sata1>; 155 #size-cells = <0>; 156 pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; 168 gpio = <&gpio1 7 0>; 179 gpio = <&gpio1 8 0>; [all …]
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H A D | kirkwood-db.dtsi | 17 reg = <0x00000000 0x20000000>; /* 512 MB */ 47 pinctrl-0 = <&pmx_sdio_gpios>; 60 partition@0 { 62 reg = <0x0 0x100000>; 67 reg = <0x100000 0x400000>; 72 reg = <0x500000 0x1fb00000>; 86 ethernet0-port@0 {
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H A D | kirkwood-rd88f6281.dtsi | 17 reg = <0x00000000 0x20000000>; 45 pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; 57 partition@0 { 59 reg = <0x0000000 0x100000>; 65 reg = <0x0100000 0x200000>; 70 reg = <0x0300000 0x500000>; 77 switch: switch@0 { 80 #size-cells = <0>; 84 #size-cells = <0>; 86 port@0 { [all …]
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/linux/arch/arm64/boot/dts/qcom/ |
H A D | sc7280-chrome-common.dtsi | 32 CLUSTER_SLEEP_0: cluster-sleep-0 { 34 arm,psci-suspend-param = <0x40003444>; 44 reg = <0x0 0x8ad00000 0x0 0x500000>; 49 reg = <0x0 0x8b200000 0x0 0x500000>; 94 pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; 97 spi_flash: flash@0 { 99 reg = <0>; 127 qcom,halt-regs = <&tcsr_1 0x17000>; 129 firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt"; 140 iommus = <&apps_smmu 0x2180 0x20>, [all …]
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/linux/arch/arm/boot/dts/microchip/ |
H A D | at91-wb50n.dtsi | 21 reg = <0x20000000 0x4000000>; 51 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; 53 slot@0 { 54 reg = <0>; 61 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; 63 atheros@0 { 66 reg = <0>; 76 dmas = <0>, <0>; /* Do not use DMA for dbgu */ 84 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>; 92 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; [all …]
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H A D | aks-cdu.dts | 33 rs485-rts-delay = <0 0>; 39 rs485-rts-delay = <0 0>; 45 rs485-rts-delay = <0 0>; 68 bootstrap@0 { 70 reg = <0x0 0x40000>; 75 reg = <0x40000 0x80000>; 80 reg = <0xc0000 0x40000>; 85 reg = <0x100000 0x400000>; 90 reg = <0x500000 0x7b00000>;
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/linux/drivers/net/ethernet/hisilicon/hns3/ |
H A D | hns3_debugfs.h | 10 #define HNS3_DBG_READ_LEN_128KB 0x20000 11 #define HNS3_DBG_READ_LEN_1MB 0x100000 12 #define HNS3_DBG_READ_LEN_4MB 0x400000 13 #define HNS3_DBG_READ_LEN_5MB 0x500000
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/linux/Documentation/devicetree/bindings/mtd/ |
H A D | samsung-s3c2410.txt | 28 reg = <0x4e000000 0x40>; 31 #size-cells = <0>; 45 partition@0 { 47 reg = <0 0x040000>; 52 reg = <0x040000 0x500000>;
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/linux/arch/arm/boot/dts/nxp/mxs/ |
H A D | imx28-apf28.dts | 15 reg = <0x40000000 0x08000000>; 21 pinctrl-0 = <&duart_pins_a>; 27 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; 30 partition@0 { 32 reg = <0x0 0x300000>; 37 reg = <0x300000 0x80000>; 42 reg = <0x380000 0x80000>; 47 reg = <0x400000 0x80000>; 52 reg = <0x480000 0x80000>; 57 reg = <0x500000 0x800000>; [all …]
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/linux/arch/arm/boot/dts/qcom/ |
H A D | qcom-sdx55-telit-fn980-tlb.dts | 16 qcom,board-id = <0xb010008 0x0>; 33 reg = <0x8ef00000 0x800000>; 38 reg = <0x8fced000 0x10000>; 43 reg = <0x90800000 0xf800000>; 91 states = <1800000 0>, <2850000 1>; 101 regulators-0 { 254 pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default 270 nand@0 { 271 reg = <0>; 277 secure-regions = /bits/ 64 <0x500000 0x500000 [all …]
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H A D | qcom-msm8926-htc-memul.dts | 50 reg = <0x05b00000 0x200000>; 55 reg = <0x07500000 0xb00000>; 60 reg = <0x08000000 0x4f00000>; 65 reg = <0x0cf00000 0x200000>; 70 reg = <0x0d100000 0x3a000>; 75 reg = <0x0d13a000 0xc6000>; 80 reg = <0x0d200000 0x650000>; 85 reg = <0x0d850000 0x3b0000>; 90 reg = <0x0dc00000 0x1400000>; 95 reg = <0x0f000000 0x500000>; [all …]
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H A D | qcom-sdx65-mtp.dts | 20 qcom,board-id = <0x2010008 0x302>; 37 reg = <0x8c400000 0x3200000>; 42 reg = <0x8fced000 0x10000>; 47 reg = <0x90800000 0x10000000>; 72 regulators-0 { 258 pinctrl-0 = <&pcie_ep_clkreq_default 283 nand@0 { 284 reg = <0>; 290 secure-regions = /bits/ 64 <0x500000 0x500000 291 0xa00000 0xb00000>;
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/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx27-apf27.dts | 18 reg = <0xa0000000 0x04000000>; 23 clock-frequency = <0>; 30 MX27_PAD_SD3_CMD__FEC_TXD0 0x0 31 MX27_PAD_SD3_CLK__FEC_TXD1 0x0 32 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 33 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 34 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 35 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 36 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 37 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 [all …]
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/linux/arch/powerpc/boot/ |
H A D | crt0.S | 17 * linked at 0x500000. 21 .long 0x500000, 0, 0, 0 35 p_prom: .8byte 0 60 cmpwi r11,0 70 li r9,0 71 li r0,0 72 9: lwz r8,0(r12) /* get tag */ 73 cmpwi r8,0 94 cmpwi r0,0 96 cmpwi r9,0 [all …]
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/linux/tools/perf/tests/ |
H A D | hists_common.h | 12 #define FAKE_MAP_PERF 0x400000 13 #define FAKE_MAP_BASH 0x400000 14 #define FAKE_MAP_LIBC 0x500000 15 #define FAKE_MAP_KERNEL 0xf00000 16 #define FAKE_MAP_LENGTH 0x100000
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/linux/drivers/clk/imx/ |
H A D | clk-imx8qxp-lpcg.h | 11 #define LSIO_PWM_0_LPCG 0x00000 12 #define LSIO_PWM_1_LPCG 0x10000 13 #define LSIO_PWM_2_LPCG 0x20000 14 #define LSIO_PWM_3_LPCG 0x30000 15 #define LSIO_PWM_4_LPCG 0x40000 16 #define LSIO_PWM_5_LPCG 0x50000 17 #define LSIO_PWM_6_LPCG 0x60000 18 #define LSIO_PWM_7_LPCG 0x70000 19 #define LSIO_GPIO_0_LPCG 0x80000 20 #define LSIO_GPIO_1_LPCG 0x90000 [all …]
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/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/ |
H A D | dma0_core_regs.h | 22 #define mmDMA0_CORE_CFG_0 0x500000 24 #define mmDMA0_CORE_CFG_1 0x500004 26 #define mmDMA0_CORE_LBW_MAX_OUTSTAND 0x500008 28 #define mmDMA0_CORE_SRC_BASE_LO 0x500014 30 #define mmDMA0_CORE_SRC_BASE_HI 0x500018 32 #define mmDMA0_CORE_DST_BASE_LO 0x50001C 34 #define mmDMA0_CORE_DST_BASE_HI 0x500020 36 #define mmDMA0_CORE_SRC_TSIZE_1 0x50002C 38 #define mmDMA0_CORE_SRC_STRIDE_1 0x500030 40 #define mmDMA0_CORE_SRC_TSIZE_2 0x500034 [all …]
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