| /freebsd/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-am62.dtsi | 55 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
56 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
57 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
58 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
59 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
60 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
61 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
62 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
63 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
64 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
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| H A D | k3-am62p.dtsi | 53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
|
| H A D | k3-am62a.dtsi | 54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
|
| H A D | k3-j722s.dtsi | 24 #size-cells = <0>;
46 cpu0: cpu@0 {
48 reg = <0x000>;
51 i-cache-size = <0x8000>;
54 d-cache-size = <0x8000>;
58 clocks = <&k3_clks 135 0>;
63 reg = <0x001>;
66 i-cache-size = <0x8000>;
69 d-cache-size = <0x8000>;
73 clocks = <&k3_clks 136 0>;
[all …]
|
| H A D | k3-am62a-main.dtsi | 11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
22 <0x01 0x00000000 0x00 0x2000>, /* GICC */
23 <0x01 0x00010000 0x00 0x1000>, /* GICH */
24 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
[all …]
|
| H A D | k3-am62-main.dtsi | 11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
27 <0x01 0x00000000 0x00 0x2000>, /* GICC */
28 <0x01 0x00010000 0x00 0x1000>, /* GICH */
29 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
[all …]
|
| H A D | k3-am62p-j722s-common-main.dtsi | 22 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
23 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
24 <0x01 0x00000000 0x00 0x2000>, /* GICC */
25 <0x01 0x00010000 0x00 0x1000>, /* GICH */
26 <0x01 0x00020000 0x00 0x2000>; /* GICV */
35 reg = <0x00 0x01820000 0x00 0x10000>;
36 socionext,synquacer-pre-its = <0x1000000 0x400000>;
44 reg = <0x00 0x00100000 0x00 0x20000>;
47 ranges = <0x00 0x00 0x00100000 0x20000>;
51 reg = <0x4044 0x8>;
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | fujitsu,mb86s70-gpio.txt | 11 - bit 0 specifies polarity (0 for normal, 1 for inverted).
16 reg = <0 0x31000000 0x10000>;
19 clocks = <&clk 0 2 1>;
|
| H A D | fujitsu,mb86s70-gpio.yaml | 45 reg = <0x31000000 0x10000>;
48 clocks = <&clk 0 2 1>;
|
| /freebsd/sys/arm/allwinner/ |
| H A D | aw_machdep.h | 30 #define ALLWINNERSOC_A10 0x10000000
31 #define ALLWINNERSOC_A13 0x13000000
32 #define ALLWINNERSOC_A10S 0x10000001
33 #define ALLWINNERSOC_A20 0x20000000
34 #define ALLWINNERSOC_H3 0x30000000
35 #define ALLWINNERSOC_A31 0x31000000
36 #define ALLWINNERSOC_A31S 0x31000001
37 #define ALLWINNERSOC_A33 0x33000000
38 #define ALLWINNERSOC_A83T 0x83000000
40 #define ALLWINNERSOC_SUN4I 0x40000000
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | arasan,sdhci.txt | 55 - #clock-cells: If specified this should be the value <0> or <1>. With this
66 will assume this as 0.
71 reg = <0xe0100000 0x1000>;
75 interrupts = <0 24 4>;
80 reg = <0xe2800000 0x1000>;
84 interrupts = <0 24 4>;
91 reg = <0x0 0xfe330000 0x0 0x10000>;
101 #clock-cells = <0>;
107 interrupts = <0 48 4>;
108 reg = <0x0 0xff160000 0x0 0x1000>;
[all …]
|
| H A D | arasan,sdhci.yaml | 137 enum: [0, 1]
158 enum: [0, 1, 2]
159 default: 0
185 reg = <0xe0100000 0x1000>;
189 interrupts = <0 24 4>;
195 reg = <0xe2800000 0x1000>;
199 interrupts = <0 24 4>;
210 reg = <0xfe33000
[all...] |
| /freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/ |
| H A D | lpc32xx.dtsi | 20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
|
| /freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/ |
| H A D | aestab2.h | 50 0x00000001, 0x00000002, 0x00000004, 0x00000008,
51 0x00000010, 0x00000020, 0x00000040, 0x00000080,
52 0x0000001b, 0x00000036
58 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
59 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
60 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
61 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
62 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
63 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
64 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
|
| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | mcp_public.h | 51 #define OFFSIZE_OFFSET_OFFSET 0
52 #define OFFSIZE_OFFSET_MASK 0x0000ffff
55 #define OFFSIZE_SIZE_MASK 0xffff0000
70 u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
71 #define ETH_SPEED_AUTONEG 0
72 #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */
75 #define ETH_PAUSE_NONE 0x0
76 #define ETH_PAUSE_AUTONEG 0x1
77 #define ETH_PAUSE_RX 0x2
78 #define ETH_PAUSE_TX 0x4
[all …]
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| H A D | ecore_init_values.h | 35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
|
| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/ |
| H A D | EmulateInstructionARM64.cpp | 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
29 #define GPR_OFFSET_NAME(reg) 0
31 #define FPU_OFFSET_NAME(reg) 0
32 #define EXC_OFFSET_NAME(reg) 0
33 #define DBG_OFFSET_NAME(reg) 0
34 #define DBG_OFFSET_NAME(reg) 0
36 "na", nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \
61 #define No_VFP 0
77 static inline bool IsZero(uint64_t x) { return x == 0; } in IsZero()
85 if (shift == 0) in LSL()
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | imx8mq.dtsi | 47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
[all …]
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| /freebsd/sys/dev/bce/ |
| H A D | if_bcefw.h | 40 int bce_COM_b06FwReleaseMajor = 0x6;
41 int bce_COM_b06FwReleaseMinor = 0x0;
42 int bce_COM_b06FwReleaseFix = 0xf;
43 u32 bce_COM_b06FwStartAddr = 0x08000118;
44 u32 bce_COM_b06FwTextAddr = 0x08000000;
45 int bce_COM_b06FwTextLen = 0x4a68;
46 u32 bce_COM_b06FwDataAddr = 0x00000000;
47 int bce_COM_b06FwDataLen = 0x0;
48 u32 bce_COM_b06FwRodataAddr = 0x08004a68;
49 int bce_COM_b06FwRodataLen = 0x14;
[all …]
|
| /freebsd/sys/dev/bxe/ |
| H A D | ecore_hsi.h | 33 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
39 #define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
40 #define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
41 #define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
47 #define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
48 #define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
49 #define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
61 #define PIN_CFG_NA 0x00000000
62 #define PIN_CFG_GPIO0_P0 0x00000001
63 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]
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| /freebsd/tools/test/iconv/ref/ |
| H A D | UTF-32BE-rev | 1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]
|