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/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dregsnv04.h5 #define NV04_PFIFO_DELAY_0 0x00002040
6 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
7 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
8 #define NV03_PFIFO_INTR_0 0x00002100
9 #define NV03_PFIFO_INTR_EN_0 0x00002140
10 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0)
17 #define NV03_PFIFO_RAMHT 0x00002210
18 #define NV03_PFIFO_RAMFC 0x00002214
19 #define NV03_PFIFO_RAMRO 0x00002218
20 #define NV40_PFIFO_RAMFC 0x00002220
[all …]
/linux/drivers/video/fbdev/mmp/panel/
H A Dtpo_tj032md01bw.c24 0x0801,
25 0x0800,
26 0x0200,
27 0x0304,
28 0x040e,
29 0x0903,
30 0x0b18,
31 0x0c53,
32 0x0d01,
33 0x0ee0,
[all …]
/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm4908.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0x0>;
33 cpu-release-addr = <0x0 0xff8>;
40 reg = <0x1>;
42 cpu-release-addr = <0x0 0xff8>;
49 reg = <0x2>;
51 cpu-release-addr = <0x0 0xff8>;
58 reg = <0x3>;
60 cpu-release-addr = <0x0 0xff8>;
[all …]
/linux/drivers/net/ethernet/cavium/thunder/
H A Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/linux/drivers/staging/fbtft/
H A Dfb_s6d1121.c24 #define DEFAULT_GAMMA "26 09 24 2C 1F 23 24 25 22 26 25 23 0D 00\n" \
25 "1C 1A 13 1D 0B 11 12 10 13 15 36 19 00 0D"
33 write_reg(par, 0x0011, 0x2004); in init_display()
34 write_reg(par, 0x0013, 0xCC00); in init_display()
35 write_reg(par, 0x0015, 0x2600); in init_display()
36 write_reg(par, 0x0014, 0x252A); in init_display()
37 write_reg(par, 0x0012, 0x0033); in init_display()
38 write_reg(par, 0x0013, 0xCC04); in init_display()
39 write_reg(par, 0x0013, 0xCC06); in init_display()
40 write_reg(par, 0x0013, 0xCC4F); in init_display()
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dp1021si-post.dtsi39 interrupts = <19 2 0 0>,
40 <16 2 0 0>;
43 /* controller at 0x9000 */
49 bus-range = <0 255>;
51 interrupts = <16 2 0 0>;
53 pcie@0 {
54 reg = <0 0 0 0 0>;
59 interrupts = <16 2 0 0>;
60 interrupt-map-mask = <0xf800 0 0 7>;
62 /* IDSEL 0x0 */
[all …]
/linux/arch/powerpc/boot/dts/
H A Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
H A Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
H A Dmpc836x_rdk.dts32 #size-cells = <0>;
34 PowerPC,8360@0 {
36 reg = <0>;
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
51 reg = <0 0>;
60 ranges = <0 0xe0000000 0x200000>;
61 reg = <0xe0000000 0x200>;
63 bus-frequency = <0>;
[all …]
H A Dkmeter1.dts29 #size-cells = <0>;
31 PowerPC,8360@0 {
33 reg = <0x0>;
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 bus-frequency = <0>; /* Filled in by U-Boot */
40 clock-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0 0>; /* Filled in by U-Boot */
54 ranges = <0x0 0xe0000000 0x00200000>;
55 reg = <0xe0000000 0x00000200>;
56 bus-frequency = <0>; /* Filled in by U-Boot */
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7757.c33 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */
34 DEFINE_RES_IRQ(evt2irq(0x700)),
39 .id = 0,
53 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */
54 DEFINE_RES_IRQ(evt2irq(0xb80)),
73 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */
74 DEFINE_RES_IRQ(evt2irq(0xf00)),
92 DEFINE_RES_MEM(0xfe430000, 0x20),
93 DEFINE_RES_IRQ(evt2irq(0x580)),
94 DEFINE_RES_IRQ(evt2irq(0x5a0)),
[all …]
/linux/drivers/scsi/fnic/
H A Dfnic_fdls.h65 * bits 0-8: oxid idx - allocated from poool
71 #define FNIC_FRAME_MASK 0xFE00
77 #define FNIC_FDLS_FABRIC_ABORT_ISSUED 0x1
78 #define FNIC_FDLS_FPMA_LEARNT 0x2
81 #define FNIC_FDLS_TPORT_IN_GPN_FT_LIST 0x1
82 #define FNIC_FDLS_TGT_ABORT_ISSUED 0x2
83 #define FNIC_FDLS_TPORT_SEND_ADISC 0x4
84 #define FNIC_FDLS_RETRY_FRAME 0x8
85 #define FNIC_FDLS_TPORT_BUSY 0x10
86 #define FNIC_FDLS_TPORT_TERMINATING 0x20
[all …]
/linux/arch/arm64/boot/dts/airoha/
H A Den7581.dtsi20 reg = <0x0 0x84000000 0x0 0xa00000>;
25 reg = <0x0 0x84b00000 0x0 0x100000>;
30 reg = <0x0 0x85000000 0x0 0x1a00000>;
35 reg = <0x0 0x86b00000 0x0 0x100000>;
40 reg = <0x0 0x86d00000 0x0 0x100000>;
51 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0x0>;
85 reg = <0x1>;
94 reg = <0x2>;
[all …]
/linux/drivers/comedi/drivers/
H A Dni_atmio.c87 RANGE_ext(0, 1)
96 .isapnp_id = 0x0000, /* XXX unknown */
98 .ai_maxdata = 0x0fff,
103 .ao_maxdata = 0x0fff,
111 .isapnp_id = 0x1900,
113 .ai_maxdata = 0x0fff,
118 .ao_maxdata = 0x0fff,
126 .isapnp_id = 0x2400,
128 .ai_maxdata = 0x0fff,
133 .ao_maxdata = 0x0fff,
[all …]
H A Dme_daq.c32 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
37 #define ME_CTRL1_REG 0x00 /* R (ai start) | W */
48 #define ME_CTRL1_ADC_MODE(x) (((x) & 0x3) << 0)
49 #define ME_CTRL1_ADC_MODE_DISABLE ME_CTRL1_ADC_MODE(0)
54 #define ME_CTRL2_REG 0x02 /* R (dac update) | W */
62 #define ME_CTRL2_BUFFERED_DAC BIT(0)
63 #define ME_STATUS_REG 0x04 /* R | W (clears interrupts) */
73 #define ME_STATUS_FST_ACTIVE BIT(0)
74 #define ME_DIO_PORT_A_REG 0x06 /* R | W */
75 #define ME_DIO_PORT_B_REG 0x08 /* R | W */
[all …]
/linux/drivers/media/usb/pwc/
H A Dpwc.h46 #define PWC_DEBUG_LEVEL_MODULE BIT(0)
74 } while (0)
86 #define PWC_TRACE(fmt, args...) do { } while(0)
87 #define PWC_DEBUG(level, fmt, args...) do { } while(0)
89 #define pwc_trace 0
97 #define FEATURE_MOTOR_PANTILT 0x0001
98 #define FEATURE_CODEC1 0x0002
99 #define FEATURE_CODEC2 0x0004
127 #define SET_LUM_CTL 0x01
128 #define GET_LUM_CTL 0x02
[all …]
/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/linux/include/linux/soc/samsung/
H A Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/linux/drivers/phy/renesas/
H A Dr8a779f0-ether-serdes.c18 #define R8A779F0_ETH_SERDES_OFFSET 0x0400
19 #define R8A779F0_ETH_SERDES_BANK_SELECT 0x03fc
85 for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { in r8a779f0_eth_serdes_common_init_ram()
87 ret = r8a779f0_eth_serdes_reg_wait(channel, 0x026c, 0x180, BIT(0), 0x01); in r8a779f0_eth_serdes_common_init_ram()
92 r8a779f0_eth_serdes_write32(dd->addr, 0x026c, 0x180, 0x03); in r8a779f0_eth_serdes_common_init_ram()
103 r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x00d7); in r8a779f0_eth_serdes_common_setting()
104 r8a779f0_eth_serdes_write32(dd->addr, 0x01cc, 0x180, 0xc200); in r8a779f0_eth_serdes_common_setting()
105 r8a779f0_eth_serdes_write32(dd->addr, 0x01c4, 0x180, 0x0042); in r8a779f0_eth_serdes_common_setting()
106 r8a779f0_eth_serdes_write32(dd->addr, 0x01c8, 0x180, 0x0000); in r8a779f0_eth_serdes_common_setting()
107 r8a779f0_eth_serdes_write32(dd->addr, 0x01dc, 0x180, 0x002f); in r8a779f0_eth_serdes_common_setting()
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h12 #define MT_ASIC_VERSION 0x0000
14 #define MT76XX_REV_E3 0x22
15 #define MT76XX_REV_E4 0x33
17 #define MT_CMB_CTRL 0x0020
21 #define MT_EFUSE_CTRL 0x0024
22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
30 #define MT_EFUSE_DATA_BASE 0x0028
33 #define MT_COEXCFG0 0x0040
34 #define MT_COEXCFG0_COEX_EN BIT(0)
36 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_viu.c46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_regs.h9 #define MT_ASIC_VERSION 0x0000
11 #define MT76XX_REV_E3 0x22
12 #define MT76XX_REV_E4 0x33
14 #define MT_CMB_CTRL 0x0020
18 #define MT_EFUSE_CTRL 0x0024
19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
27 #define MT_EFUSE_DATA_BASE 0x0028
30 #define MT_COEXCFG0 0x0040
31 #define MT_COEXCFG0_COEX_EN BIT(0)
33 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/linux/drivers/pci/controller/
H A Dpci-xgene.c27 #define PCIECORE_CTLANDSTATUS 0x50
28 #define PIM1_1L 0x80
29 #define IBAR2 0x98
30 #define IR2MSK 0x9c
31 #define PIM2_1L 0xa0
32 #define IBAR3L 0xb4
33 #define IR3MSKL 0xbc
34 #define PIM3_1L 0xc4
35 #define OMR1BARL 0x100
36 #define OMR2BARL 0x118
[all …]

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