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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ull-jozacp.dts25 led-0 {
28 function-enumerator = <0>;
29 pwms = <&pwm1 0 10000000 0>;
37 pwms = <&pwm3 0 10000000 0>;
45 pwms = <&pwm5 0 10000000 0>;
59 pwms = <&pwm2 0 10000000 0>;
67 pwms = <&pwm4 0 10000000 0>;
75 pwms = <&pwm6 0 10000000 0>;
98 pinctrl-0 = <&pinctrl_vbus>;
110 pinctrl-0 = <&pinctrl_wifi_npd>;
[all …]
H A Dimx6sl-tolino-vision.dts29 pwms = <&ec 0 50000>;
36 pinctrl-0 = <&pinctrl_backlight_power>;
49 pinctrl-0 = <&pinctrl_gpio_keys>;
77 pinctrl-0 = <&pinctrl_leds>;
79 led-0 {
97 reg = <0x80000000 0x20000000>;
103 pinctrl-0 = <&pinctrl_wifi_power>;
114 pinctrl-0 = <&pinctrl_wifi_reset>;
116 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
122 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arc/
H A Dvdk_axs10x_mb.dtsi13 ranges = <0x00000000 0xe0000000 0x10000000>;
20 #clock-cells = <0>;
26 #clock-cells = <0>;
30 #clock-cells = <0>;
39 reg = < 0x18000 0x2000 >;
43 snps,phy-addr = < 0 >; // VDK model phy address is 0
51 reg = < 0x40000 0x100 >;
57 reg = <0x20000 0x100>;
67 reg = <0x21000 0x100>;
77 reg = <0x22000 0x100>;
[all …]
H A Daxs10x_mb.dtsi17 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
23 reg = <0x11220 0x4>;
28 reg = <0x100a0 0x10>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
62 #clock-cells = <0>;
68 reg = <0x10080 0x10>, <0x110 0x10>;
69 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnvidia,tegra194-pinmux.txt31 0: none, 1: down, 2: up.
33 0: drive, 1: tristate.
50 - nvidia,drive-type: Integer. Valid range 0...3.
51 - nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
54 - nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
90 reg = <0x2430000 0x17000
91 0xc300000 0x4000>;
94 pinctrl-0 = <&pex_rst_c5_out_state>;
H A Dnvidia,tegra234-pinmux.yaml126 reg = <0x2430000 0x17000>;
129 pinctrl-0 = <&pex_rst_c5_out_state>;
H A Dnvidia,tegra194-pinmux.yaml266 reg = <0x2430000 0x17000>;
269 pinctrl-0 = <&pex_rst_c5_out_state>;
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc7280-chrome-common.dtsi32 CLUSTER_SLEEP_0: cluster-sleep-0 {
34 arm,psci-suspend-param = <0x40003444>;
44 reg = <0x0 0x8ad00000 0x0 0x500000>;
49 reg = <0x0 0x8b200000 0x0 0x500000>;
94 pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
97 spi_flash: flash@0 {
99 reg = <0>;
127 qcom,halt-regs = <&tcsr_1 0x17000>;
129 firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
140 iommus = <&apps_smmu 0x2180 0x20>,
[all …]
H A Dqcs404.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #size-cells = <0>;
42 reg = <0x100>;
56 reg = <0x101>;
70 reg = <0x102>;
84 reg = <0x103>;
104 CPU_SLEEP_0: cpu-sleep-0 {
107 arm,psci-suspend-param = <0x40000003>;
161 reg = <0 0x80000000 0 0>;
[all …]
H A Dmsm8976.dtsi26 #clock-cells = <0>;
32 #size-cells = <0>;
34 CPU0: cpu@0 {
37 reg = <0x0>;
48 reg = <0x1>;
59 reg = <0x2>;
70 reg = <0x3>;
81 reg = <0x100>;
92 reg = <0x101>;
103 reg = <0x102>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dinterlaken-lac-portals.dtsi34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
49 compatible = "fsl,interlaken-lac-portal-v1.0";
50 reg = <0x2000 0x1000>;
54 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra74x.dtsi49 reg = <0x41500000 0x100>;
55 reg = <0x41501000 0x4>,
56 <0x41501010 0x4>,
57 <0x41501014 0x4>;
65 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
69 ranges = <0x0 0x41501000 0x1000>;
73 mmu0_dsp2: mmu@0 {
75 reg = <0x0 0x100>;
77 #iommu-cells = <0>;
78 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
[all …]
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/freebsd/contrib/less/
H A Dwide.uni2 { 0x1100, 0x115f }, /* W */
3 { 0x231a, 0x231b }, /* W */
4 { 0x2329, 0x232a }, /* W */
5 { 0x23e9, 0x23ec }, /* W */
6 { 0x23f0, 0x23f0 }, /* W */
7 { 0x23f3, 0x23f3 }, /* W */
8 { 0x25fd, 0x25fe }, /* W */
9 { 0x2614, 0x2615 }, /* W */
10 { 0x2630, 0x2637 }, /* W */
11 { 0x2648, 0x2653 }, /* W */
[all …]
/freebsd/sys/contrib/device-tree/src/x86/
H A Dfalconfalls.dts16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
26 soc@0 {
36 reg = <0xfec00000 0x1000>;
41 reg = <0xfed00000 0x200>;
46 reg = <0xfee00000 0x1000>;
54 bus-range = <0 0>;
55 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
56 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dinterlaken-lac.txt31 There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor"
32 version), and a subset at 0x1000-0x1FFF. The former is a superset of the
45 IP Block Revision Register (IPBRR0) at offset 0x0BF8.
51 0x02000100 T4240
78 reg = <0x229000 0x1000>;
84 reg = <0x228000 0x1000>;
136 Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version
161 #address-cells = <0x1>;
162 #size-cells = <0x1>;
164 ranges = <0x0 0xf 0xf4400000 0x20000>;
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dcoredump.c18 {0x800, 0x810},
19 {0x820, 0x82C},
20 {0x830, 0x8F4},
21 {0x90C, 0x91C},
22 {0xA14, 0xA18},
23 {0xA84, 0xA94},
24 {0xAA8, 0xAD4},
25 {0xADC, 0xB40},
26 {0x1000, 0x10A4},
27 {0x10BC, 0x111C},
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2m.dtsi27 ranges = <0x40000000 0x40000000 0x10000000>,
28 <0x10000000 0x10000000 0x00020000>;
31 interrupt-map-mask = <0 63>;
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DUnicodeNameToCodepoint.cpp4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
33 char32_t Value = 0xFFFFFFFF;
34 uint32_t ChildrenOffset = 0;
36 uint32_t Size = 0;
41 return !Name.empty() || Value == 0xFFFFFFFF; in isValid()
43 constexpr bool hasChildren() const { return ChildrenOffset != 0 || IsRoot; } in hasChildren()
70 if (Offset == 0) in readNode()
80 bool LongName = NameInfo & 0x40; in readNode()
81 bool HasValue = NameInfo & 0x80; in readNode()
82 std::size_t Size = NameInfo & ~0xC in readNode()
[all...]
H A DUnicode.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
28 // https://unicode.org/Public/15.1.0/ucdxml/ in isPrintable()
30 {0x0020, 0x007E}, {0x00A0, 0x00AC}, {0x00AE, 0x0377}, in isPrintable()
31 {0x037A, 0x037 in isPrintable()
[all...]
/freebsd/sys/dev/mmc/
H A Dmmcreg.h72 #define MMC_RSP_PRESENT (1ul << 0) /* Response */
77 #define MMC_RSP_MASK 0x1ful
78 #define MMC_CMD_AC (0ul << 5) /* Addressed Command, no data */
86 #define MMC_RSP_NONE (0)
99 #define MMC_ERR_NONE 0
144 #define R1_CURRENT_STATE_MASK (0xfu << 9) /* sx, b */
149 #define R1_STATUS(x) ((x) & 0xFFFFE000)
151 #define R1_STATE_IDLE 0
162 #define R4_IO_NUM_FUNCTIONS(ocr) (((ocr) >> 28) & 0x3)
163 #define R4_IO_MEM_PRESENT (0x1 << 27)
[all …]
/freebsd/contrib/bc/src/
H A Ddata.c173 { NULL, 0, 0 },
286 "divide by 0",
346 "POSIX requires 0 or 1 comparison operators per condition",
417 { 0x1100, 0x115F }, { 0x231A, 0x231B }, { 0x2329, 0x232A },
418 { 0x23E9, 0x23EC }, { 0x23F0, 0x23F0 }, { 0x23F3, 0x23F3 },
419 { 0x25FD, 0x25FE }, { 0x2614, 0x2615 }, { 0x2648, 0x2653 },
420 { 0x267F, 0x267F }, { 0x2693, 0x2693 }, { 0x26A1, 0x26A1 },
421 { 0x26AA, 0x26AB }, { 0x26BD, 0x26BE }, { 0x26C4, 0x26C5 },
422 { 0x26CE, 0x26CE }, { 0x26D4, 0x26D4 }, { 0x26EA, 0x26EA },
423 { 0x26F2, 0x26F3 }, { 0x26F5, 0x26F5 }, { 0x26FA, 0x26FA },
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x
[all...]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_reset.c43 #if 0
83 volatile u_int32_t *usb_ctrl_r1 = (u_int32_t *) 0xb8116c84; \
84 volatile u_int32_t *usb_ctrl_r2 = (u_int32_t *) 0xb8116c88; \
85 *usb_ctrl_r1 = (*usb_ctrl_r1 & 0xffefffff); \
86 *usb_ctrl_r2 = (*usb_ctrl_r2 & 0xfc1fffff) | (1 << 21) | (3 << 22); \
88 } while (0)
111 (1 << 21) | (0xf << 22), in ar9300_disable_pll_lock_detect()
112 (1 << 21) | (0x3 << 22)); in ar9300_disable_pll_lock_detect()
178 ath_hal_getcapability(ah, HAL_CAP_MFP, 0, &mfpcap); in ar9300_init_mfp()
197 * Cisco spec defined bits 0-3 as mask in ar9300_init_mfp()
[all …]