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/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dmarvell,armada-3700-uart.yaml82 reg = <0x12000 0x18>;
83 clocks = <&uartclk 0>;
96 reg = <0x12200 0x30>;
H A Dmvebu-uart.txt39 reg = <0x12000 0x18>;
40 clocks = <&uartclk 0>;
50 reg = <0x12200 0x30>;
/freebsd/sys/dts/arm/
H A Ddb78460.dts43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0x0>;
51 d-cache-size = <0x8000>; // L1, 32K
52 i-cache-size = <0x8000>; // L1, 32K
53 timebase-frequency = <0>;
55 clock-frequency = <0>;
61 reg = <0x0 0x80000000>; // 2G at 0x0
68 ranges = <0x0 0xd0000000 0x00100000>;
69 bus-frequency = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp.dtsi35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
41 reg = <0x1400 0x500>;
46 reg = <0x08000 0x1000>;
47 cache-id-part = <0x100>;
55 pinctrl-0 = <&uart2_pins>;
57 reg = <0x12200 0x100>;
61 clocks = <&coreclk 0>;
67 pinctrl-0 = <&uart3_pins>;
69 reg = <0x12300 0x100>;
73 clocks = <&coreclk 0>;
[all …]
H A Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
H A Ddove.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
28 reg = <0>;
34 marvell,tauros2-cache-features = <0>;
46 #size-cells = <0>;
51 pinctrl-0 = <&pmx_i2cmux_0>;
55 i2c0: i2c@0 {
56 reg = <0>;
58 #size-cells = <0>;
65 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Dac5-98dx25xx.dtsi21 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0 0x0>;
45 reg = <0x0 0x100>;
85 /* 16M internal register @ 0x7f00_0000 */
86 ranges = <0x0 0x0 0x7f000000 0x1000000>;
91 reg = <0x12000 0x100>;
101 reg = <0x12100 0x100>;
111 reg = <0x12200 0x100>;
121 reg = <0x12300 0x100>;
[all …]
H A Darmada-37xx.dtsi33 reg = <0 0x4000000 0 0x200000>;
38 reg = <0 0x4400000 0 0x1000000>;
45 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0>;
83 /* 32M internal register @ 0xd000_0000 */
84 ranges = <0x0 0x0 0xd0000000 0x2000000>;
88 reg = <0x8300 0x40>;
96 reg = <0xd000 0x1000>;
102 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm8550.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
67 #size-cells = <0>;
69 cpu0: cpu@0 {
72 reg = <0 0>;
73 clocks = <&cpufreq_hw 0>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0 0x100>;
[all …]
H A Dsm8650.dtsi42 #clock-cells = <0>;
47 #clock-cells = <0>;
52 #clock-cells = <0>;
61 #clock-cells = <0>;
71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0 0>;
78 clocks = <&cpufreq_hw 0>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
118 reg = <0 0x100>;
[all …]
/freebsd/usr.sbin/cxgbetool/
H A Dreg_defs_t7.c3 /* Directory name: t7_sw_reg.txt, Changeset: 5946:0b60ff298e7d */
6 { "SGE_PF_KDOORBELL", 0x1e000, 0 },
10 { "PIDX", 0, 13 },
11 { "SGE_PF_GTS", 0x1e004, 0 },
15 { "CIDXInc", 0, 12 },
16 { "SGE_PF_KTIMESTAMP_LO", 0x1e008, 0 },
17 { "SGE_PF_KTIMESTAMP_HI", 0x1e00c, 0 },
18 { "SGE_PF_KDOORBELL", 0x1e400, 0 },
22 { "PIDX", 0, 13 },
23 { "SGE_PF_GTS", 0x1e404, 0 },
[all …]
/freebsd/sys/dev/cxgbe/common/
H A Dt4_regs.h34 /* Directory name: t7_sw_reg.txt, Changeset: 5946:0b60ff298e7d */
36 #define MYPF_BASE 0x1b000
39 #define PF0_BASE 0x1e000
42 #define PF1_BASE 0x1e400
45 #define PF2_BASE 0x1e800
48 #define PF3_BASE 0x1ec00
51 #define PF4_BASE 0x1f000
54 #define PF5_BASE 0x1f400
57 #define PF6_BASE 0x1f800
60 #define PF7_BASE 0x1fc00
[all …]