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Searched +full:0 +full:x0810 (Results 1 – 25 of 53) sorted by relevance

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/freebsd/sys/dev/sound/pci/
H A Dallegro_code.h55 0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980,
56 0x00DD, 0x7980, 0x03B4, 0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4,
57 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x031A, 0x7980,
58 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
59 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980,
60 0x03B4, 0x7980, 0x03B4, 0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20,
61 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08, 0x0053, 0x695A, 0xEB08,
62 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
63 0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40,
64 0x7980, 0x0038, 0xBE41, 0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddm8148-evm.dts13 reg = <0x80000000 0x40000000>; /* 1 GB */
36 ethphy0: ethernet-phy@0 {
37 reg = <0>;
46 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
48 nand@0,0 {
50 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
52 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
60 gpmc,sync-clk-ps = <0>;
61 gpmc,cs-on-ns = <0>;
67 gpmc,we-on-ns = <0>;
[all …]
H A Ddra62x-j5eco-evm.dts13 reg = <0x80000000 0x40000000>; /* 1 GB */
36 ethphy0: ethernet-phy@0 {
37 reg = <0>;
46 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
48 nand@0,0 {
50 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
52 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
60 gpmc,sync-clk-ps = <0>;
61 gpmc,cs-on-ns = <0>;
67 gpmc,we-on-ns = <0>;
[all …]
H A Domap2420-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x0070>;
18 #clock-cells = <0>;
22 reg = <0x0070>;
26 #clock-cells = <0>;
32 #clock-cells = <0>;
37 reg = <0x0070>;
42 #clock-cells = <0>;
46 reg = <0x0810>;
50 #clock-cells = <0>;
[all …]
H A Dam3874-iceboard.dts31 reg = <0x80000000 0x40000000>; /* 1 GB */
47 * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the
65 ethphy0: ethernet-phy@0 {
66 reg = <0x2>;
69 rxdv-skew-ps = <0>;
71 rxd3-skew-ps = <0>;
72 rxd2-skew-ps = <0>;
73 rxd1-skew-ps = <0>;
74 rxd0-skew-ps = <0>;
80 reg = <0x1>;
[all …]
/freebsd/sys/dev/ichiic/
H A Dig4_reg.h63 * 22.2 Default Values on device reset are 0 except as specified here:
64 * TAR_ADD 0x00000055
65 * SS_SCL_HCNT 0x00000264
66 * SS_SCL_LCNT 0x000002C2
67 * FS_SCL_HCNT 0x0000006E
68 * FS_SCL_LCNT 0x000000CF
69 * INTR_MASK 0x000008FF
70 * I2C_STA 0x00000006
71 * SDA_HOLD 0x00000001
72 * SDA_SETUP 0x0000006
[all...]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dqcom,sdm845-camss.yaml96 port@0:
321 iommus = <&apps_smmu 0x0808 0x0>,
322 <&apps_smmu 0x0810 0x8>,
323 <&apps_smmu 0x0c08 0x0>,
324 <&apps_smmu 0x0c10 0x8>;
330 reg = <0 0xacb3000 0 0x1000>,
331 <0 0xacba000 0 0x1000>,
332 <0 0xacc8000 0 0x1000>,
333 <0 0xac65000 0 0x1000>,
334 <0 0xac66000 0 0x1000>,
[all …]
/freebsd/sys/dev/eqos/
H A Dif_eqos_reg.h38 #define GMAC_MAC_CONFIGURATION 0x0000
49 #define GMAC_MAC_CONFIGURATION_RE (1U << 0)
50 #define GMAC_MAC_EXT_CONFIGURATION 0x0004
51 #define GMAC_MAC_PACKET_FILTER 0x0008
59 #define GMAC_MAC_PACKET_FILTER_PR (1U << 0)
60 #define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C
61 #define GMAC_MAC_HASH_TABLE_REG0 0x0010
62 #define GMAC_MAC_HASH_TABLE_REG1 0x0014
63 #define GMAC_MAC_VLAN_TAG 0x0050
64 #define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070
[all …]
/freebsd/sys/arm/xilinx/
H A Dzy7_slcr.h43 #define ZY7_SCLR_SCL 0x0000
44 #define ZY7_SLCR_LOCK 0x0004
45 #define ZY7_SLCR_LOCK_MAGIC 0x767b
46 #define ZY7_SLCR_UNLOCK 0x0008
47 #define ZY7_SLCR_UNLOCK_MAGIC 0xdf0d
48 #define ZY7_SLCR_LOCKSTA 0x000c
51 #define ZY7_SLCR_ARM_PLL_CTRL 0x0100
52 #define ZY7_SLCR_DDR_PLL_CTRL 0x0104
53 #define ZY7_SLCR_IO_PLL_CTRL 0x0108
54 #define ZY7_SLCR_PLL_CTRL_RESET (1 << 0)
[all …]
/freebsd/sys/dev/usb/input/
H A Duhid_snes.c53 #define UREQ_GET_PORT_STATUS 0x01
54 #define UREQ_SOFT_RESET 0x02
56 #define UP 0x7f00
57 #define DOWN 0x7fff
58 #define LEFT 0x00ff
59 #define RIGHT 0xff7f
60 #define X 0x1f
61 #define Y 0x8f
62 #define A 0x2f
63 #define B 0x4f
[all …]
/freebsd/sys/dev/safe/
H A Dsafereg.h37 #define BS_BAR 0x10 /* DMA base address register */
38 #define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */
39 #define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */
41 #define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */
44 #define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */
46 #define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */
47 #define SAFE_PE_SRC 0x0004 /* Packet Engine Source */
48 #define SAFE_PE_DST 0x0008 /* Packet Engine Destination */
49 #define SAFE_PE_SA 0x000c /* Packet Engine SA */
50 #define SAFE_PE_LEN 0x0010 /* Packet Engine Length */
[all …]
/freebsd/tests/sys/netpfil/pf/
H A Dether.sh53 atf_check -s exit:0 -o ignore ping -c 1 -t 1 192.0.2.2
68 atf_check -s exit:0 -o ignore ping -c 1 -t 1 192.0.2.2
72 "ether block to { ${epair_a_mac}, 00:01:02:0:04:05 }"
83 atf_check -s exit:0 -o ignore ping -c 1 -t 1 192.0.2.2
88 atf_check -s exit:0 -o ignore ping -c 1 -t 1 192.0.2.2
92 atf_check -s exit:0 -o ignore ping -c 1 -t 1 192.0.2.2
97 atf_check -s exit:0 -o ignore ping -c 1 -t 1 192.0.2.2
121 atf_check -s exit:0 -o ignore ping -c 1 -t 1 192.0.2.2
149 "ether block proto 0x0810"
152 atf_check -s exit:0 -o ignore ping -c 1 -t 1 192.0.2.2
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/freebsd/sys/dev/glxsb/
H A Dglxsb.c56 #define PCI_VENDOR_AMD 0x1022 /* AMD */
57 #define PCI_PRODUCT_AMD_GEODE_LX_CRYPTO 0x2082 /* Geode LX Crypto */
59 #define SB_GLD_MSR_CAP 0x58002000 /* RO - Capabilities */
60 #define SB_GLD_MSR_CONFIG 0x58002001 /* RW - Master Config */
61 #define SB_GLD_MSR_SMI 0x58002002 /* RW - SMI */
62 #define SB_GLD_MSR_ERROR 0x58002003 /* RW - Error */
63 #define SB_GLD_MSR_PM 0x58002004 /* RW - Power Mgmt */
64 #define SB_GLD_MSR_DIAG 0x58002005 /* RW - Diagnostic */
65 #define SB_GLD_MSR_CTRL 0x58002006 /* RW - Security Block Cntrl */
68 #define SB_GMC_DIV0 0x0000 /* AES update divisor values */
[all …]
/freebsd/sys/dev/bwi/
H A Dbwirf.c106 #define SAVE_RF_REG(mac, regs, n) (regs)->rf_##n = RF_READ((mac), 0x##n)
107 #define RESTORE_RF_REG(mac, regs, n) RF_WRITE((mac), 0x##n, (regs)->rf_##n)
109 #define SAVE_PHY_REG(mac, regs, n) (regs)->phy_##n = PHY_READ((mac), 0x##n)
110 #define RESTORE_PHY_REG(mac, regs, n) PHY_WRITE((mac), 0x##n, (regs)->phy_##n)
165 val = (int16_t)__SHIFTOUT(PHY_READ(mac, 0x47f), NRSSI_11G_MASK); in bwi_nrssi_11g()
191 KASSERT(idx >= 0 && idx < BWI_RFLO_MAX, ("idx %d", idx)); in bwi_rf_lo_isused()
214 if (ctrl < 0x70) in bwi_rf_read()
215 ctrl += 0x80; in bwi_rf_read()
216 else if (ctrl < 0x80) in bwi_rf_read()
217 ctrl += 0x70; in bwi_rf_read()
[all …]
/freebsd/sys/contrib/dev/iwlwifi/pcie/
H A Ddrv.c32 0, _invalid_type))
43 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5000_mac_cfg)}, /* Mini Card */
44 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5000_mac_cfg)}, /* Half Mini Card */
45 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5000_mac_cfg)}, /* Mini Card */
46 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5000_mac_cfg)}, /* Half Mini Card */
47 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5000_mac_cfg)}, /* Mini Card */
48 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5000_mac_cfg)}, /* Half Mini Card */
49 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5000_mac_cfg)}, /* Mini Card */
50 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5000_mac_cfg)}, /* Half Mini Card */
51 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5000_mac_cfg)}, /* Mini Card */
[all …]
/freebsd/sys/dev/usb/controller/
H A Ddwc_otgreg.h32 #define DOTG_GOTGCTL 0x0000
33 #define DOTG_GOTGINT 0x0004
34 #define DOTG_GAHBCFG 0x0008
35 #define DOTG_GUSBCFG 0x000C
36 #define DOTG_GRSTCTL 0x0010
37 #define DOTG_GINTSTS 0x0014
38 #define DOTG_GINTMSK 0x0018
39 #define DOTG_GRXSTSRD 0x001C
40 #define DOTG_GRXSTSRH 0x001C
41 #define DOTG_GRXSTSPD 0x0020
[all …]
/freebsd/sys/dev/bwn/
H A Dif_bwn_phy_g.c143 if (mac->mac_phy.hwpctl == 0 || mac->mac_phy.use_hwpctl == NULL) in bwn_has_hwpctl()
144 return (0); in bwn_has_hwpctl()
169 } while(0) in bwn_phy_g_attach()
180 pg->pg_flags = 0; in bwn_phy_g_attach()
181 if (pab0 == 0 || pab1 == 0 || pab2 == 0 || pab0 == -1 || pab1 == -1 || in bwn_phy_g_attach()
185 return (0); in bwn_phy_g_attach()
188 pg->pg_idletssi = (bg == 0 || bg == -1) ? 62 : bg; in bwn_phy_g_attach()
194 for (i = 0; i < 64; i++) { in bwn_phy_g_attach()
196 int8_t j = 0; in bwn_phy_g_attach()
221 return (0); in bwn_phy_g_attach()
[all …]
H A Dif_bwnreg.h36 #define BWN_IOCTL_PHYCLOCK_ENABLE 0x0004
37 #define BWN_IOCTL_PHYRESET 0x0008
38 #define BWN_IOCTL_MACPHYCLKEN 0x0010 /* MAC PHY Clock Control Enable (rev >= 5) */
39 #define BWN_IOCTL_PLLREFSEL 0x0020 /* PLL Frequency Reference Select (rev >= 5) */
41 #define BWN_IOCTL_PHY_BANDWIDTH 0x00C0
42 #define BWN_IOCTL_PHY_BANDWIDTH_10MHZ 0x0000
43 #define BWN_IOCTL_PHY_BANDWIDTH_20MHZ 0x0040
44 #define BWN_IOCTL_PHY_BANDWIDTH_40MHZ 0x0080
45 #define BWN_IOCTL_SUPPORT_G 0x2000
48 #define BWN_IOST_HAVE_2GHZ 0x0001
[all …]
/freebsd/sys/dev/jme/
H A Dif_jmereg.h36 #define VENDORID_JMICRON 0x197B
41 #define DEVICEID_JMC250 0x0250
42 #define DEVICEREVID_JMC250_A0 0x00
43 #define DEVICEREVID_JMC250_A2 0x11
48 #define DEVICEID_JMC260 0x0260
49 #define DEVICEREVID_JMC260_A0 0x00
51 #define DEVICEID_JMC2XX_MASK 0x0FF0
54 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */
56 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */
58 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */
[all …]
/freebsd/share/man/man4/
H A Diwlwififw.472 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4070 Ta 7000 Ta iwlwifi-7260
75 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4072 Ta 7000 Ta iwlwifi-7260
78 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4170 Ta 7000 Ta iwlwifi-7260
81 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4c60 Ta 7000 Ta iwlwifi-7260
84 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4c70 Ta 7000 Ta iwlwifi-7260
87 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4060 Ta 7000 Ta iwlwifi-7260
90 .It 0x8086 Ta 0x08b1 Ta any Ta 0x406a Ta 7000 Ta iwlwifi-7260
93 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4160 Ta 7000 Ta iwlwifi-7260
96 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4062 Ta 7000 Ta iwlwifi-7260
99 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4162 Ta 7000 Ta iwlwifi-7260
[all …]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_radio_2055.c84 #define B2055_INITTAB_ENTRY_OK 0x01
85 #define B2055_INITTAB_UPLOAD 0x02
91 [B2055_SP_PINPD] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, },
92 [B2055_C1_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
93 [B2055_C1_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
94 [B2055_C2_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
95 [B2055_C2_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, },
96 [B2055_C1_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
97 [B2055_C1_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
98 [B2055_C2_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, },
[all …]
/freebsd/sys/dev/sk/
H A Dif_skreg.h54 #define SK_GENESIS 0x0A
55 #define SK_YUKON 0xB0
56 #define SK_YUKON_LITE 0xB1
57 #define SK_YUKON_LP 0xB2
58 #define SK_YUKON_FAMILY(x) ((x) & 0xB0)
61 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */
62 #define SK_YUKON_LITE_REV_A1 0x3
63 #define SK_YUKON_LITE_REV_A3 0x7
68 #define VENDORID_SK 0x1148
73 #define VENDORID_MARVELL 0x11AB
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211reg.h32 #define AR_CR 0x0008 /* control register */
33 #define AR_RXDP 0x000C /* receive queue descriptor pointer */
34 #define AR_CFG 0x0014 /* configuration and status register */
35 #define AR_IER 0x0024 /* Interrupt enable register */
36 #define AR_RTSD0 0x0028 /* RTS Duration Parameters 0 */
37 #define AR_RTSD1 0x002c /* RTS Duration Parameters 1 */
38 #define AR_TXCFG 0x0030 /* tx DMA size config register */
39 #define AR_RXCFG 0x0034 /* rx DMA size config register */
40 #define AR5211_JUMBO_LAST 0x0038 /* Jumbo descriptor last address */
41 #define AR_MIBC 0x0040 /* MIB control register */
[all …]
/freebsd/sys/dev/axgbe/
H A Dxgbe-common.h121 #define DMA_MR 0x3000
122 #define DMA_SBMR 0x3004
123 #define DMA_ISR 0x3008
124 #define DMA_AXIARCR 0x3010
125 #define DMA_AXIAWCR 0x3018
126 #define DMA_AXIAWARCR 0x301c
127 #define DMA_DSR0 0x3020
128 #define DMA_DSR1 0x3024
129 #define DMA_DSR2 0x3028
130 #define DMA_DSR3 0x302
[all...]

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