Home
last modified time | relevance | path

Searched +full:0 +full:x0808 (Results 1 – 25 of 67) sorted by relevance

123

/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x
[all...]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/freebsd/sys/dev/sound/pci/
H A Dfm801.c38 #define PCI_VENDOR_FORTEMEDIA 0x1319
39 #define PCI_DEVICE_FORTEMEDIA1 0x08011319 /* Audio controller */
40 #define PCI_DEVICE_FORTEMEDIA2 0x08021319 /* Joystick controller */
42 #define FM_PCM_VOLUME 0x00
43 #define FM_FM_VOLUME 0x02
44 #define FM_I2S_VOLUME 0x04
45 #define FM_RECORD_SOURCE 0x06
47 #define FM_PLAY_CTL 0x08
48 #define FM_PLAY_RATE_MASK 0x0f00
49 #define FM_PLAY_BUF1_LAST 0x0001
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddm8148-evm.dts13 reg = <0x80000000 0x40000000>; /* 1 GB */
36 ethphy0: ethernet-phy@0 {
37 reg = <0>;
46 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
48 nand@0,0 {
50 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
52 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
60 gpmc,sync-clk-ps = <0>;
61 gpmc,cs-on-ns = <0>;
67 gpmc,we-on-ns = <0>;
[all …]
H A Ddra62x-j5eco-evm.dts13 reg = <0x80000000 0x40000000>; /* 1 GB */
36 ethphy0: ethernet-phy@0 {
37 reg = <0>;
46 ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
48 nand@0,0 {
50 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
52 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
60 gpmc,sync-clk-ps = <0>;
61 gpmc,cs-on-ns = <0>;
67 gpmc,we-on-ns = <0>;
[all …]
H A Dam3874-iceboard.dts31 reg = <0x80000000 0x40000000>; /* 1 GB */
47 * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the
65 ethphy0: ethernet-phy@0 {
66 reg = <0x2>;
69 rxdv-skew-ps = <0>;
71 rxd3-skew-ps = <0>;
72 rxd2-skew-ps = <0>;
73 rxd1-skew-ps = <0>;
74 rxd0-skew-ps = <0>;
80 reg = <0x1>;
[all …]
/freebsd/sys/dev/mlx5/
H A Ddiagnostics.h41 m(+1, pxd_ready_bp, 0x0401) \
42 m(+1, pci_write_bp, 0x0402) \
43 m(+1, pci_read_bp, 0x0403) \
44 m(+1, pci_read_stuck_no_completion_buffer, 0x0404) \
45 m(+1, max_pci_bw, 0x0405) \
46 m(+1, used_pci_bw, 0x0406) \
47 m(+1, rx_pci_errors, 0) \
48 m(+1, tx_pci_errors, 0) \
49 m(+1, tx_pci_correctable_errors, 0) \
50 m(+1, tx_pci_non_fatal_errors, 0) \
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dqcom,sdm845-camss.yaml96 port@0:
321 iommus = <&apps_smmu 0x0808 0x0>,
322 <&apps_smmu 0x0810 0x8>,
323 <&apps_smmu 0x0c08 0x0>,
324 <&apps_smmu 0x0c10 0x8>;
330 reg = <0 0xacb3000 0 0x1000>,
331 <0 0xacba000 0 0x1000>,
332 <0 0xacc8000 0 0x1000>,
333 <0 0xac65000 0 0x1000>,
334 <0 0xac66000 0 0x1000>,
[all …]
/freebsd/sys/dev/sdhci/
H A Dsdhci_fdt_rockchip.c70 #define RK3399_GRF_EMMCCORE_CON0 0xf000
71 #define RK3399_CORECFG_BASECLKFREQ 0xff00
73 #define RK3399_CORECFG_TUNINGCOUNT 0x3f
74 #define RK3399_GRF_EMMCCORE_CON11 0xf02c
75 #define RK3399_CORECFG_CLOCKMULTIPLIER 0xff
77 #define RK3568_EMMC_HOST_CTRL 0x0508
78 #define RK3568_EMMC_EMMC_CTRL 0x052c
79 #define RK3568_EMMC_ATCTRL 0x0540
80 #define RK3568_EMMC_DLL_CTRL 0x0800
81 #define DLL_CTRL_SRST 0x00000001
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8723d.h14 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
18 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
20 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
22 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
24 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
26 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
28 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
30 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
[all...]
H A Drtw8723x.h28 IQK_ROUND_INVALID = 0xff,
45 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
53 u8 res4[48]; /* 0xd0 */
54 u8 vendor_id[2]; /* 0x100 */
55 u8 product_id[2]; /* 0x102 */
56 u8 usb_option; /* 0x104 */
57 u8 res5[2]; /* 0x105 */
58 u8 mac_addr[ETH_ALEN]; /* 0x107 */
62 u8 res4[0x4a]; /* 0xd0 */
63 u8 mac_addr[ETH_ALEN]; /* 0x11a */
[all …]
/freebsd/sys/dev/eqos/
H A Dif_eqos_reg.h38 #define GMAC_MAC_CONFIGURATION 0x0000
49 #define GMAC_MAC_CONFIGURATION_RE (1U << 0)
50 #define GMAC_MAC_EXT_CONFIGURATION 0x0004
51 #define GMAC_MAC_PACKET_FILTER 0x0008
59 #define GMAC_MAC_PACKET_FILTER_PR (1U << 0)
60 #define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C
61 #define GMAC_MAC_HASH_TABLE_REG0 0x0010
62 #define GMAC_MAC_HASH_TABLE_REG1 0x0014
63 #define GMAC_MAC_VLAN_TAG 0x0050
64 #define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070
[all …]
/freebsd/crypto/openssl/test/recipes/90-test_sslapi_data/
H A Dssltraceref-zlib.txt3 Version = TLS 1.0 (0x301)
7 client_version=0x303 (TLS 1.2)
9 gmt_unix_time=0x?
13 {0x13, 0x01} TLS_AES_128_GCM_SHA256
15 No Compression (0x00)
18 uncompressed (0)
31 extension_type=session_ticket(35), length=0
32 extension_type=encrypt_then_mac(22), length=0
33 extension_type=extended_master_secret(23), length=0
35 mldsa65 (0x0905)
[all …]
H A Dssltraceref.txt3 Version = TLS 1.0 (0x301)
7 client_version=0x303 (TLS 1.2)
9 gmt_unix_time=0x?
13 {0x13, 0x01} TLS_AES_128_GCM_SHA256
15 No Compression (0x00)
18 uncompressed (0)
31 extension_type=session_ticket(35), length=0
32 extension_type=encrypt_then_mac(22), length=0
33 extension_type=extended_master_secret(23), length=0
35 mldsa65 (0x0905)
[all …]
/freebsd/crypto/openssl/test/recipes/75-test_quicapi_data/
H A Dssltraceref.txt3 Version = TLS 1.0 (0x301)
7 client_version=0x303 (TLS 1.2)
9 gmt_unix_time=0x?
11 session_id (len=0):
13 {0x13, 0x01} TLS_AES_128_GCM_SHA256
15 No Compression (0x00)
18 0000 - 0c 00 0f 00 01 04 80 00-75 30 03 02 44 b0 0e ........u0..D..
19 000f - 01 02 04 04 80 0c 00 00-05 04 80 08 00 00 06 ...............
23 uncompressed (0)
35 extension_type=session_ticket(35), length=0
[all …]
H A Dssltraceref-zlib.txt3 Version = TLS 1.0 (0x301)
7 client_version=0x303 (TLS 1.2)
9 gmt_unix_time=0x?
11 session_id (len=0):
13 {0x13, 0x01} TLS_AES_128_GCM_SHA256
15 No Compression (0x00)
18 0000 - 0c 00 0f 00 01 04 80 00-75 30 03 02 44 b0 0e ........u0..D..
19 000f - 01 02 04 04 80 0c 00 00-05 04 80 08 00 00 06 ...............
23 uncompressed (0)
35 extension_type=session_ticket(35), length=0
[all …]
/freebsd/sys/dev/hdmi/
H A Ddwc_hdmireg.h29 #define HDMI_DESIGN_ID 0x0000
30 #define HDMI_REVISION_ID 0x0001
31 #define HDMI_PRODUCT_ID0 0x0002
32 #define HDMI_PRODUCT_ID1 0x0003
35 #define HDMI_IH_FC_STAT0 0x0100
36 #define HDMI_IH_FC_STAT1 0x0101
37 #define HDMI_IH_FC_STAT2 0x0102
38 #define HDMI_IH_AS_STAT0 0x0103
39 #define HDMI_IH_PHY_STAT0 0x0104
40 #define HDMI_IH_PHY_STAT0_HPD (1 << 0)
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_regs.h9 #define MT_ASIC_VERSION 0x0000
11 #define MT76XX_REV_E3 0x22
12 #define MT76XX_REV_E4 0x33
14 #define MT_CMB_CTRL 0x0020
18 #define MT_EFUSE_CTRL 0x0024
19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
27 #define MT_EFUSE_DATA_BASE 0x0028
30 #define MT_COEXCFG0 0x0040
31 #define MT_COEXCFG0_COEX_EN BIT(0)
33 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/freebsd/sys/dev/safe/
H A Dsafereg.h37 #define BS_BAR 0x10 /* DMA base address register */
38 #define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */
39 #define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */
41 #define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */
44 #define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */
46 #define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */
47 #define SAFE_PE_SRC 0x0004 /* Packet Engine Source */
48 #define SAFE_PE_DST 0x0008 /* Packet Engine Destination */
49 #define SAFE_PE_SA 0x000c /* Packet Engine SA */
50 #define SAFE_PE_LEN 0x0010 /* Packet Engine Length */
[all …]
/freebsd/crypto/openssl/util/perl/TLSProxy/
H A DMessage.pm19 MT_HELLO_REQUEST => 0,
45 AL_DESC_CLOSE_NOTIFY => 0,
75 EXT_SERVER_NAME => 0,
101 EXT_CRYPTOPRO_BUG_EXTENSION => 0xfde8,
102 EXT_UNKNOWN => 0xfffe,
104 EXT_FORCE_LAST => 0xffff
111 SIG_ALG_RSA_PKCS1_SHA256 => 0x0401,
112 SIG_ALG_RSA_PKCS1_SHA384 => 0x0501,
113 SIG_ALG_RSA_PKCS1_SHA512 => 0x0601,
114 SIG_ALG_ECDSA_SECP256R1_SHA256 => 0x0403,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/freebsd/sys/dev/glxsb/
H A Dglxsb.c56 #define PCI_VENDOR_AMD 0x1022 /* AMD */
57 #define PCI_PRODUCT_AMD_GEODE_LX_CRYPTO 0x2082 /* Geode LX Crypto */
59 #define SB_GLD_MSR_CAP 0x58002000 /* RO - Capabilities */
60 #define SB_GLD_MSR_CONFIG 0x58002001 /* RW - Master Config */
61 #define SB_GLD_MSR_SMI 0x58002002 /* RW - SMI */
62 #define SB_GLD_MSR_ERROR 0x58002003 /* RW - Error */
63 #define SB_GLD_MSR_PM 0x58002004 /* RW - Power Mgmt */
64 #define SB_GLD_MSR_DIAG 0x58002005 /* RW - Diagnostic */
65 #define SB_GLD_MSR_CTRL 0x58002006 /* RW - Security Block Cntrl */
68 #define SB_GMC_DIV0 0x0000 /* AES update divisor values */
[all …]
/freebsd/sys/net/
H A Dethernet.h37 ((hasfcs) ? ETHER_CRC_LEN : 0) + \
38 (((etype) == ETHERTYPE_VLAN) ? ETHER_VLAN_ENCAP_LEN : 0))
48 #define ETHER_CRC_POLY_LE 0xedb88320
49 #define ETHER_CRC_POLY_BE 0x04c11db6
77 #define ETHER_IS_MULTICAST(addr) (*(addr) & 0x01) /* is address mcast/bcast? */
79 (((addr)[0] == 0x33) && ((addr)[1] == 0x33))
81 (((addr)[0] & (addr)[1] & (addr)[2] & \
82 (addr)[3] & (addr)[4] & (addr)[5]) == 0xff)
84 (((addr)[0] | (addr)[1] | (addr)[2] | \
85 (addr)[3] | (addr)[4] | (addr)[5]) == 0x00)
[all …]
/freebsd/sys/dev/ichiic/
H A Dig4_reg.h63 * 22.2 Default Values on device reset are 0 except as specified here:
64 * TAR_ADD 0x00000055
65 * SS_SCL_HCNT 0x00000264
66 * SS_SCL_LCNT 0x000002C2
67 * FS_SCL_HCNT 0x0000006E
68 * FS_SCL_LCNT 0x000000CF
69 * INTR_MASK 0x000008FF
70 * I2C_STA 0x00000006
71 * SDA_HOLD 0x00000001
72 * SDA_SETUP 0x0000006
[all...]

123