1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2025 Oxide Computer Company 14 */ 15 16 /* 17 * This works at performing remap tests across both the DFv3 and DFv4 variants. 18 */ 19 20 #include "zen_umc_test.h" 21 22 static const zen_umc_t zen_umc_remap_v3 = { 23 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 24 .umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL, 25 .umc_df_rev = DF_REV_3, 26 .umc_decomp = { 27 .dfd_sock_mask = 0x01, 28 .dfd_die_mask = 0x00, 29 .dfd_node_mask = 0x20, 30 .dfd_comp_mask = 0x1f, 31 .dfd_sock_shift = 0, 32 .dfd_die_shift = 0, 33 .dfd_node_shift = 5, 34 .dfd_comp_shift = 0 35 }, 36 .umc_ndfs = 1, 37 .umc_dfs = { { 38 .zud_dfno = 0, 39 .zud_dram_nrules = 1, 40 .zud_nchan = 4, 41 .zud_cs_nremap = 2, 42 .zud_hole_base = 0, 43 .zud_rules = { { 44 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN | 45 DF_DRAM_F_REMAP_SOCK, 46 .ddr_base = 0, 47 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL, 48 .ddr_dest_fabid = 0, 49 .ddr_sock_ileave_bits = 0, 50 .ddr_die_ileave_bits = 0, 51 .ddr_addr_start = 12, 52 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 53 } }, 54 .zud_remap = { { 55 .csr_nremaps = ZEN_UMC_MILAN_REMAP_ENTS, 56 .csr_remaps = { 0x3, 0x2, 0x1, 0x0, 0x4, 0x5, 0x6, 0x7, 57 0x8, 0x9, 0xa, 0xb }, 58 }, { 59 .csr_nremaps = ZEN_UMC_MILAN_REMAP_ENTS, 60 .csr_remaps = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 61 0x8, 0x9, 0xa, 0xb }, 62 } }, 63 .zud_chan = { { 64 .chan_flags = UMC_CHAN_F_ECC_EN, 65 .chan_fabid = 0, 66 .chan_instid = 0, 67 .chan_logid = 0, 68 .chan_nrules = 1, 69 .chan_type = UMC_DIMM_T_DDR4, 70 .chan_rules = { { 71 .ddr_flags = DF_DRAM_F_VALID | 72 DF_DRAM_F_REMAP_EN | 73 DF_DRAM_F_REMAP_SOCK, 74 .ddr_base = 0, 75 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 76 1024ULL, 77 .ddr_dest_fabid = 0, 78 .ddr_sock_ileave_bits = 0, 79 .ddr_die_ileave_bits = 0, 80 .ddr_addr_start = 12, 81 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 82 } }, 83 .chan_dimms = { { 84 .ud_flags = UMC_DIMM_F_VALID, 85 .ud_width = UMC_DIMM_W_X4, 86 .ud_kind = UMC_DIMM_K_RDIMM, 87 .ud_dimmno = 0, 88 .ud_cs = { { 89 .ucs_flags = UMC_CS_F_DECODE_EN, 90 .ucs_base = { 91 .udb_base = 0, 92 .udb_valid = B_TRUE 93 }, 94 .ucs_base_mask = 0x3ffffffff, 95 .ucs_nbanks = 0x4, 96 .ucs_ncol = 0xa, 97 .ucs_nrow_lo = 0x11, 98 .ucs_nbank_groups = 0x2, 99 .ucs_row_hi_bit = 0x18, 100 .ucs_row_low_bit = 0x11, 101 .ucs_bank_bits = { 0xf, 0x10, 0xd, 102 0xe }, 103 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 104 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 105 } } 106 } }, 107 }, { 108 .chan_flags = UMC_CHAN_F_ECC_EN, 109 .chan_fabid = 1, 110 .chan_instid = 1, 111 .chan_logid = 1, 112 .chan_nrules = 1, 113 .chan_type = UMC_DIMM_T_DDR4, 114 .chan_rules = { { 115 .ddr_flags = DF_DRAM_F_VALID | 116 DF_DRAM_F_REMAP_EN | 117 DF_DRAM_F_REMAP_SOCK, 118 .ddr_base = 0, 119 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 120 1024ULL, 121 .ddr_dest_fabid = 0, 122 .ddr_sock_ileave_bits = 0, 123 .ddr_die_ileave_bits = 0, 124 .ddr_addr_start = 12, 125 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 126 } }, 127 .chan_dimms = { { 128 .ud_flags = UMC_DIMM_F_VALID, 129 .ud_width = UMC_DIMM_W_X4, 130 .ud_kind = UMC_DIMM_K_RDIMM, 131 .ud_dimmno = 0, 132 .ud_cs = { { 133 .ucs_flags = UMC_CS_F_DECODE_EN, 134 .ucs_base = { 135 .udb_base = 0, 136 .udb_valid = B_TRUE 137 }, 138 .ucs_base_mask = 0x3ffffffff, 139 .ucs_nbanks = 0x4, 140 .ucs_ncol = 0xa, 141 .ucs_nrow_lo = 0x11, 142 .ucs_nbank_groups = 0x2, 143 .ucs_row_hi_bit = 0x18, 144 .ucs_row_low_bit = 0x11, 145 .ucs_bank_bits = { 0xf, 0x10, 0xd, 146 0xe }, 147 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 148 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 149 } } 150 } }, 151 }, { 152 .chan_flags = UMC_CHAN_F_ECC_EN, 153 .chan_fabid = 2, 154 .chan_instid = 2, 155 .chan_logid = 2, 156 .chan_nrules = 1, 157 .chan_type = UMC_DIMM_T_DDR4, 158 .chan_rules = { { 159 .ddr_flags = DF_DRAM_F_VALID | 160 DF_DRAM_F_REMAP_EN | 161 DF_DRAM_F_REMAP_SOCK, 162 .ddr_base = 0, 163 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 164 1024ULL, 165 .ddr_dest_fabid = 0, 166 .ddr_sock_ileave_bits = 0, 167 .ddr_die_ileave_bits = 0, 168 .ddr_addr_start = 12, 169 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 170 } }, 171 .chan_dimms = { { 172 .ud_flags = UMC_DIMM_F_VALID, 173 .ud_width = UMC_DIMM_W_X4, 174 .ud_kind = UMC_DIMM_K_RDIMM, 175 .ud_dimmno = 0, 176 .ud_cs = { { 177 .ucs_flags = UMC_CS_F_DECODE_EN, 178 .ucs_base = { 179 .udb_base = 0, 180 .udb_valid = B_TRUE 181 }, 182 .ucs_base_mask = 0x3ffffffff, 183 .ucs_nbanks = 0x4, 184 .ucs_ncol = 0xa, 185 .ucs_nrow_lo = 0x11, 186 .ucs_nbank_groups = 0x2, 187 .ucs_row_hi_bit = 0x18, 188 .ucs_row_low_bit = 0x11, 189 .ucs_bank_bits = { 0xf, 0x10, 0xd, 190 0xe }, 191 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 192 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 193 } } 194 } }, 195 }, { 196 .chan_flags = UMC_CHAN_F_ECC_EN, 197 .chan_fabid = 3, 198 .chan_instid = 3, 199 .chan_logid = 3, 200 .chan_nrules = 1, 201 .chan_type = UMC_DIMM_T_DDR4, 202 .chan_rules = { { 203 .ddr_flags = DF_DRAM_F_VALID | 204 DF_DRAM_F_REMAP_EN | 205 DF_DRAM_F_REMAP_SOCK, 206 .ddr_base = 0, 207 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 208 1024ULL, 209 .ddr_dest_fabid = 0, 210 .ddr_sock_ileave_bits = 0, 211 .ddr_die_ileave_bits = 0, 212 .ddr_addr_start = 12, 213 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 214 } }, 215 .chan_dimms = { { 216 .ud_flags = UMC_DIMM_F_VALID, 217 .ud_width = UMC_DIMM_W_X4, 218 .ud_kind = UMC_DIMM_K_RDIMM, 219 .ud_dimmno = 0, 220 .ud_cs = { { 221 .ucs_flags = UMC_CS_F_DECODE_EN, 222 .ucs_base = { 223 .udb_base = 0, 224 .udb_valid = B_TRUE 225 }, 226 .ucs_base_mask = 0x3ffffffff, 227 .ucs_nbanks = 0x4, 228 .ucs_ncol = 0xa, 229 .ucs_nrow_lo = 0x11, 230 .ucs_nbank_groups = 0x2, 231 .ucs_row_hi_bit = 0x18, 232 .ucs_row_low_bit = 0x11, 233 .ucs_bank_bits = { 0xf, 0x10, 0xd, 234 0xe }, 235 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 236 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 237 } } 238 } }, 239 } } 240 } } 241 }; 242 243 /* 244 * This sets up a DFv4 capable remap engine. The important difference we want to 245 * test here is that the remap rules can be selected on a per-DRAM rule basis. 246 * This leads us to split our rules in half and end up with two totally 247 * different remapping schemes. In comparison, DFv3 is target socket based. 248 */ 249 static const zen_umc_t zen_umc_remap_v4 = { 250 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 251 .umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL, 252 .umc_df_rev = DF_REV_4, 253 .umc_decomp = { 254 .dfd_sock_mask = 0x01, 255 .dfd_die_mask = 0x00, 256 .dfd_node_mask = 0x20, 257 .dfd_comp_mask = 0x1f, 258 .dfd_sock_shift = 0, 259 .dfd_die_shift = 0, 260 .dfd_node_shift = 5, 261 .dfd_comp_shift = 0 262 }, 263 .umc_ndfs = 1, 264 .umc_dfs = { { 265 .zud_dfno = 0, 266 .zud_dram_nrules = 2, 267 .zud_nchan = 4, 268 .zud_cs_nremap = 2, 269 .zud_hole_base = 0, 270 .zud_rules = { { 271 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN, 272 .ddr_base = 0, 273 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 1024ULL, 274 .ddr_dest_fabid = 0, 275 .ddr_sock_ileave_bits = 0, 276 .ddr_die_ileave_bits = 0, 277 .ddr_addr_start = 12, 278 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 279 .ddr_remap_ent = 0 280 }, { 281 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN, 282 .ddr_base = 32ULL * 1024ULL * 1024ULL * 1024ULL, 283 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL, 284 .ddr_dest_fabid = 0, 285 .ddr_sock_ileave_bits = 0, 286 .ddr_die_ileave_bits = 0, 287 .ddr_addr_start = 12, 288 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 289 .ddr_remap_ent = 1 290 } }, 291 .zud_remap = { { 292 .csr_nremaps = ZEN_UMC_MAX_REMAP_ENTS, 293 .csr_remaps = { 0x3, 0x2, 0x1, 0x0, 0x4, 0x5, 0x6, 0x7, 294 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf }, 295 }, { 296 .csr_nremaps = ZEN_UMC_MAX_REMAP_ENTS, 297 .csr_remaps = { 0x2, 0x1, 0x3, 0x0, 0x4, 0x5, 0x6, 0x7, 298 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf }, 299 } }, 300 .zud_chan = { { 301 .chan_flags = UMC_CHAN_F_ECC_EN, 302 .chan_fabid = 0, 303 .chan_instid = 0, 304 .chan_logid = 0, 305 .chan_nrules = 2, 306 .chan_type = UMC_DIMM_T_DDR4, 307 .chan_rules = { { 308 .ddr_flags = DF_DRAM_F_VALID | 309 DF_DRAM_F_REMAP_EN, 310 .ddr_base = 0, 311 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 312 1024ULL, 313 .ddr_dest_fabid = 0, 314 .ddr_sock_ileave_bits = 0, 315 .ddr_die_ileave_bits = 0, 316 .ddr_addr_start = 12, 317 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 318 .ddr_remap_ent = 0 319 }, { 320 .ddr_flags = DF_DRAM_F_VALID | 321 DF_DRAM_F_REMAP_EN, 322 .ddr_base = 32ULL * 1024ULL * 1024ULL * 323 1024ULL, 324 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 325 1024ULL, 326 .ddr_dest_fabid = 0, 327 .ddr_sock_ileave_bits = 0, 328 .ddr_die_ileave_bits = 0, 329 .ddr_addr_start = 12, 330 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 331 .ddr_remap_ent = 1 332 } }, 333 .chan_offsets = { { 334 .cho_valid = B_TRUE, 335 .cho_offset = 0x200000000, 336 } }, 337 .chan_dimms = { { 338 .ud_flags = UMC_DIMM_F_VALID, 339 .ud_width = UMC_DIMM_W_X4, 340 .ud_kind = UMC_DIMM_K_RDIMM, 341 .ud_dimmno = 0, 342 .ud_cs = { { 343 .ucs_flags = UMC_CS_F_DECODE_EN, 344 .ucs_base = { 345 .udb_base = 0, 346 .udb_valid = B_TRUE 347 }, 348 .ucs_base_mask = 0x3ffffffff, 349 .ucs_nbanks = 0x4, 350 .ucs_ncol = 0xa, 351 .ucs_nrow_lo = 0x11, 352 .ucs_nbank_groups = 0x2, 353 .ucs_row_hi_bit = 0x18, 354 .ucs_row_low_bit = 0x11, 355 .ucs_bank_bits = { 0xf, 0x10, 0xd, 356 0xe }, 357 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 358 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 359 } } 360 } }, 361 }, { 362 .chan_flags = UMC_CHAN_F_ECC_EN, 363 .chan_fabid = 1, 364 .chan_instid = 1, 365 .chan_logid = 1, 366 .chan_nrules = 2, 367 .chan_type = UMC_DIMM_T_DDR4, 368 .chan_rules = { { 369 .ddr_flags = DF_DRAM_F_VALID | 370 DF_DRAM_F_REMAP_EN, 371 .ddr_base = 0, 372 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 373 1024ULL, 374 .ddr_dest_fabid = 0, 375 .ddr_sock_ileave_bits = 0, 376 .ddr_die_ileave_bits = 0, 377 .ddr_addr_start = 12, 378 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 379 .ddr_remap_ent = 0 380 }, { 381 .ddr_flags = DF_DRAM_F_VALID | 382 DF_DRAM_F_REMAP_EN, 383 .ddr_base = 32ULL * 1024ULL * 1024ULL * 384 1024ULL, 385 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 386 1024ULL, 387 .ddr_dest_fabid = 0, 388 .ddr_sock_ileave_bits = 0, 389 .ddr_die_ileave_bits = 0, 390 .ddr_addr_start = 12, 391 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 392 .ddr_remap_ent = 1 393 } }, 394 .chan_offsets = { { 395 .cho_valid = B_TRUE, 396 .cho_offset = 0x200000000, 397 } }, 398 .chan_dimms = { { 399 .ud_flags = UMC_DIMM_F_VALID, 400 .ud_width = UMC_DIMM_W_X4, 401 .ud_kind = UMC_DIMM_K_RDIMM, 402 .ud_dimmno = 0, 403 .ud_cs = { { 404 .ucs_flags = UMC_CS_F_DECODE_EN, 405 .ucs_base = { 406 .udb_base = 0, 407 .udb_valid = B_TRUE 408 }, 409 .ucs_base_mask = 0x3ffffffff, 410 .ucs_nbanks = 0x4, 411 .ucs_ncol = 0xa, 412 .ucs_nrow_lo = 0x11, 413 .ucs_nbank_groups = 0x2, 414 .ucs_row_hi_bit = 0x18, 415 .ucs_row_low_bit = 0x11, 416 .ucs_bank_bits = { 0xf, 0x10, 0xd, 417 0xe }, 418 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 419 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 420 } } 421 } }, 422 }, { 423 .chan_flags = UMC_CHAN_F_ECC_EN, 424 .chan_fabid = 2, 425 .chan_instid = 2, 426 .chan_logid = 2, 427 .chan_nrules = 2, 428 .chan_type = UMC_DIMM_T_DDR4, 429 .chan_rules = { { 430 .ddr_flags = DF_DRAM_F_VALID | 431 DF_DRAM_F_REMAP_EN, 432 .ddr_base = 0, 433 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 434 1024ULL, 435 .ddr_dest_fabid = 0, 436 .ddr_sock_ileave_bits = 0, 437 .ddr_die_ileave_bits = 0, 438 .ddr_addr_start = 12, 439 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 440 .ddr_remap_ent = 0 441 }, { 442 .ddr_flags = DF_DRAM_F_VALID | 443 DF_DRAM_F_REMAP_EN, 444 .ddr_base = 32ULL * 1024ULL * 1024ULL * 445 1024ULL, 446 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 447 1024ULL, 448 .ddr_dest_fabid = 0, 449 .ddr_sock_ileave_bits = 0, 450 .ddr_die_ileave_bits = 0, 451 .ddr_addr_start = 12, 452 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 453 .ddr_remap_ent = 1 454 } }, 455 .chan_offsets = { { 456 .cho_valid = B_TRUE, 457 .cho_offset = 0x200000000, 458 } }, 459 .chan_dimms = { { 460 .ud_flags = UMC_DIMM_F_VALID, 461 .ud_width = UMC_DIMM_W_X4, 462 .ud_kind = UMC_DIMM_K_RDIMM, 463 .ud_dimmno = 0, 464 .ud_cs = { { 465 .ucs_flags = UMC_CS_F_DECODE_EN, 466 .ucs_base = { 467 .udb_base = 0, 468 .udb_valid = B_TRUE 469 }, 470 .ucs_base_mask = 0x3ffffffff, 471 .ucs_nbanks = 0x4, 472 .ucs_ncol = 0xa, 473 .ucs_nrow_lo = 0x11, 474 .ucs_nbank_groups = 0x2, 475 .ucs_row_hi_bit = 0x18, 476 .ucs_row_low_bit = 0x11, 477 .ucs_bank_bits = { 0xf, 0x10, 0xd, 478 0xe }, 479 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 480 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 481 } } 482 } }, 483 }, { 484 .chan_flags = UMC_CHAN_F_ECC_EN, 485 .chan_fabid = 3, 486 .chan_instid = 3, 487 .chan_logid = 3, 488 .chan_nrules = 2, 489 .chan_type = UMC_DIMM_T_DDR4, 490 .chan_rules = { { 491 .ddr_flags = DF_DRAM_F_VALID | 492 DF_DRAM_F_REMAP_EN, 493 .ddr_base = 0, 494 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 495 1024ULL, 496 .ddr_dest_fabid = 0, 497 .ddr_sock_ileave_bits = 0, 498 .ddr_die_ileave_bits = 0, 499 .ddr_addr_start = 12, 500 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 501 .ddr_remap_ent = 0 502 }, { 503 .ddr_flags = DF_DRAM_F_VALID | 504 DF_DRAM_F_REMAP_EN, 505 .ddr_base = 32ULL * 1024ULL * 1024ULL * 506 1024ULL, 507 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 508 1024ULL, 509 .ddr_dest_fabid = 0, 510 .ddr_sock_ileave_bits = 0, 511 .ddr_die_ileave_bits = 0, 512 .ddr_addr_start = 12, 513 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 514 .ddr_remap_ent = 1 515 } }, 516 .chan_offsets = { { 517 .cho_valid = B_TRUE, 518 .cho_offset = 0x200000000, 519 } }, 520 .chan_dimms = { { 521 .ud_flags = UMC_DIMM_F_VALID, 522 .ud_width = UMC_DIMM_W_X4, 523 .ud_kind = UMC_DIMM_K_RDIMM, 524 .ud_dimmno = 0, 525 .ud_cs = { { 526 .ucs_flags = UMC_CS_F_DECODE_EN, 527 .ucs_base = { 528 .udb_base = 0, 529 .udb_valid = B_TRUE 530 }, 531 .ucs_base_mask = 0x3ffffffff, 532 .ucs_nbanks = 0x4, 533 .ucs_ncol = 0xa, 534 .ucs_nrow_lo = 0x11, 535 .ucs_nbank_groups = 0x2, 536 .ucs_row_hi_bit = 0x18, 537 .ucs_row_low_bit = 0x11, 538 .ucs_bank_bits = { 0xf, 0x10, 0xd, 539 0xe }, 540 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 541 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 542 } } 543 } }, 544 } } 545 } } 546 }; 547 548 const umc_decode_test_t zen_umc_test_remap[] = { { 549 .udt_desc = "Milan Remap (0)", 550 .udt_umc = &zen_umc_remap_v3, 551 .udt_pa = 0x138, 552 .udt_pass = B_TRUE, 553 .udt_norm_addr = 0x138, 554 .udt_sock = 0, 555 .udt_die = 0, 556 .udt_comp = 3, 557 .udt_dimm_no = 0, 558 .udt_dimm_col = 0x27, 559 .udt_dimm_row = 0, 560 .udt_dimm_bank = 0, 561 .udt_dimm_bank_group = 0, 562 .udt_dimm_subchan = UINT8_MAX, 563 .udt_dimm_rm = 0, 564 .udt_dimm_cs = 0 565 }, { 566 .udt_desc = "Milan Remap (1)", 567 .udt_umc = &zen_umc_remap_v3, 568 .udt_pa = 0x1138, 569 .udt_pass = B_TRUE, 570 .udt_norm_addr = 0x138, 571 .udt_sock = 0, 572 .udt_die = 0, 573 .udt_comp = 2, 574 .udt_dimm_no = 0, 575 .udt_dimm_col = 0x27, 576 .udt_dimm_row = 0, 577 .udt_dimm_bank = 0, 578 .udt_dimm_bank_group = 0, 579 .udt_dimm_subchan = UINT8_MAX, 580 .udt_dimm_rm = 0, 581 .udt_dimm_cs = 0 582 }, { 583 .udt_desc = "Milan Remap (2)", 584 .udt_umc = &zen_umc_remap_v3, 585 .udt_pa = 0x2138, 586 .udt_pass = B_TRUE, 587 .udt_norm_addr = 0x138, 588 .udt_sock = 0, 589 .udt_die = 0, 590 .udt_comp = 1, 591 .udt_dimm_no = 0, 592 .udt_dimm_col = 0x27, 593 .udt_dimm_row = 0, 594 .udt_dimm_bank = 0, 595 .udt_dimm_bank_group = 0, 596 .udt_dimm_subchan = UINT8_MAX, 597 .udt_dimm_rm = 0, 598 .udt_dimm_cs = 0 599 }, { 600 .udt_desc = "Milan Remap (3)", 601 .udt_umc = &zen_umc_remap_v3, 602 .udt_pa = 0x3138, 603 .udt_pass = B_TRUE, 604 .udt_norm_addr = 0x138, 605 .udt_sock = 0, 606 .udt_die = 0, 607 .udt_comp = 0, 608 .udt_dimm_no = 0, 609 .udt_dimm_col = 0x27, 610 .udt_dimm_row = 0, 611 .udt_dimm_bank = 0, 612 .udt_dimm_bank_group = 0, 613 .udt_dimm_subchan = UINT8_MAX, 614 .udt_dimm_rm = 0, 615 .udt_dimm_cs = 0 616 }, { 617 .udt_desc = "DFv4 Remap (0)", 618 .udt_umc = &zen_umc_remap_v4, 619 .udt_pa = 0x163, 620 .udt_pass = B_TRUE, 621 .udt_norm_addr = 0x163, 622 .udt_sock = 0, 623 .udt_die = 0, 624 .udt_comp = 3, 625 .udt_dimm_no = 0, 626 .udt_dimm_col = 0x2c, 627 .udt_dimm_row = 0, 628 .udt_dimm_bank = 0, 629 .udt_dimm_bank_group = 0, 630 .udt_dimm_subchan = UINT8_MAX, 631 .udt_dimm_rm = 0, 632 .udt_dimm_cs = 0 633 }, { 634 .udt_desc = "DFv4 Remap (1)", 635 .udt_umc = &zen_umc_remap_v4, 636 .udt_pa = 0x1163, 637 .udt_pass = B_TRUE, 638 .udt_norm_addr = 0x163, 639 .udt_sock = 0, 640 .udt_die = 0, 641 .udt_comp = 2, 642 .udt_dimm_no = 0, 643 .udt_dimm_col = 0x2c, 644 .udt_dimm_row = 0, 645 .udt_dimm_bank = 0, 646 .udt_dimm_bank_group = 0, 647 .udt_dimm_subchan = UINT8_MAX, 648 .udt_dimm_rm = 0, 649 .udt_dimm_cs = 0 650 }, { 651 .udt_desc = "DFv4 Remap (2)", 652 .udt_umc = &zen_umc_remap_v4, 653 .udt_pa = 0x2163, 654 .udt_pass = B_TRUE, 655 .udt_norm_addr = 0x163, 656 .udt_sock = 0, 657 .udt_die = 0, 658 .udt_comp = 1, 659 .udt_dimm_no = 0, 660 .udt_dimm_col = 0x2c, 661 .udt_dimm_row = 0, 662 .udt_dimm_bank = 0, 663 .udt_dimm_bank_group = 0, 664 .udt_dimm_subchan = UINT8_MAX, 665 .udt_dimm_rm = 0, 666 .udt_dimm_cs = 0 667 }, { 668 .udt_desc = "DFv4 Remap (3)", 669 .udt_umc = &zen_umc_remap_v4, 670 .udt_pa = 0x3163, 671 .udt_pass = B_TRUE, 672 .udt_norm_addr = 0x163, 673 .udt_sock = 0, 674 .udt_die = 0, 675 .udt_comp = 0, 676 .udt_dimm_no = 0, 677 .udt_dimm_col = 0x2c, 678 .udt_dimm_row = 0, 679 .udt_dimm_bank = 0, 680 .udt_dimm_bank_group = 0, 681 .udt_dimm_subchan = UINT8_MAX, 682 .udt_dimm_rm = 0, 683 .udt_dimm_cs = 0 684 }, { 685 .udt_desc = "DFv4 Remap (4)", 686 .udt_umc = &zen_umc_remap_v4, 687 .udt_pa = 0x900000163, 688 .udt_pass = B_TRUE, 689 .udt_norm_addr = 0x240000163, 690 .udt_sock = 0, 691 .udt_die = 0, 692 .udt_comp = 2, 693 .udt_dimm_no = 0, 694 .udt_dimm_col = 0x2c, 695 .udt_dimm_row = 0x12000, 696 .udt_dimm_bank = 0, 697 .udt_dimm_bank_group = 0, 698 .udt_dimm_subchan = UINT8_MAX, 699 .udt_dimm_rm = 0, 700 .udt_dimm_cs = 0 701 }, { 702 .udt_desc = "DFv4 Remap (5)", 703 .udt_umc = &zen_umc_remap_v4, 704 .udt_pa = 0x900001163, 705 .udt_pass = B_TRUE, 706 .udt_norm_addr = 0x240000163, 707 .udt_sock = 0, 708 .udt_die = 0, 709 .udt_comp = 1, 710 .udt_dimm_no = 0, 711 .udt_dimm_col = 0x2c, 712 .udt_dimm_row = 0x12000, 713 .udt_dimm_bank = 0, 714 .udt_dimm_bank_group = 0, 715 .udt_dimm_subchan = UINT8_MAX, 716 .udt_dimm_rm = 0, 717 .udt_dimm_cs = 0 718 }, { 719 .udt_desc = "DFv4 Remap (6)", 720 .udt_umc = &zen_umc_remap_v4, 721 .udt_pa = 0x900002163, 722 .udt_pass = B_TRUE, 723 .udt_norm_addr = 0x240000163, 724 .udt_sock = 0, 725 .udt_die = 0, 726 .udt_comp = 3, 727 .udt_dimm_no = 0, 728 .udt_dimm_col = 0x2c, 729 .udt_dimm_row = 0x12000, 730 .udt_dimm_bank = 0, 731 .udt_dimm_bank_group = 0, 732 .udt_dimm_subchan = UINT8_MAX, 733 .udt_dimm_rm = 0, 734 .udt_dimm_cs = 0 735 }, { 736 .udt_desc = "DFv4 Remap (7)", 737 .udt_umc = &zen_umc_remap_v4, 738 .udt_pa = 0x900003163, 739 .udt_pass = B_TRUE, 740 .udt_norm_addr = 0x240000163, 741 .udt_sock = 0, 742 .udt_die = 0, 743 .udt_comp = 0, 744 .udt_dimm_no = 0, 745 .udt_dimm_col = 0x2c, 746 .udt_dimm_row = 0x12000, 747 .udt_dimm_bank = 0, 748 .udt_dimm_bank_group = 0, 749 .udt_dimm_subchan = UINT8_MAX, 750 .udt_dimm_rm = 0, 751 .udt_dimm_cs = 0 752 }, { 753 .udt_desc = NULL 754 } }; 755