1 /*-
2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
4 * All rights reserved.
5 *
6 * Adapted to Marvell SoC by Semihalf.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
29 */
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/eventhandler.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/malloc.h>
38 #include <sys/rman.h>
39 #include <sys/kdb.h>
40 #include <sys/timeet.h>
41 #include <sys/timetc.h>
42 #include <sys/watchdog.h>
43 #include <machine/bus.h>
44 #include <machine/cpu.h>
45
46 #include <arm/mv/mvreg.h>
47 #include <arm/mv/mvvar.h>
48
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51
52 #define INITIAL_TIMECOUNTER (0xffffffff)
53 #define MAX_WATCHDOG_TICKS (0xffffffff)
54 #define WD_RST_OUT_EN 0x00000002
55
56 #define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */
57
58 struct mv_wdt_config {
59 enum soc_family wdt_soc;
60 uint32_t wdt_timer;
61 void (*wdt_enable)(void);
62 void (*wdt_disable)(void);
63 unsigned int wdt_clock_src;
64 };
65
66 static void mv_wdt_enable_armv5(void);
67 static void mv_wdt_enable_armada_38x(void);
68 static void mv_wdt_enable_armada_xp(void);
69 static inline void mv_wdt_enable_armada_38x_xp_helper(void);
70
71 static void mv_wdt_disable_armv5(void);
72 static void mv_wdt_disable_armada_38x(void);
73 static void mv_wdt_disable_armada_xp(void);
74
75 static struct mv_wdt_config mv_wdt_armada_38x_config = {
76 .wdt_soc = MV_SOC_ARMADA_38X,
77 .wdt_timer = 4,
78 .wdt_enable = &mv_wdt_enable_armada_38x,
79 .wdt_disable = &mv_wdt_disable_armada_38x,
80 .wdt_clock_src = MV_CLOCK_SRC_ARMV7,
81 };
82
83 static struct mv_wdt_config mv_wdt_armada_xp_config = {
84 .wdt_soc = MV_SOC_ARMADA_XP,
85 .wdt_timer = 2,
86 .wdt_enable = &mv_wdt_enable_armada_xp,
87 .wdt_disable = &mv_wdt_disable_armada_xp,
88 .wdt_clock_src = MV_CLOCK_SRC_ARMV7,
89 };
90
91 static struct mv_wdt_config mv_wdt_armv5_config = {
92 .wdt_soc = MV_SOC_ARMV5,
93 .wdt_timer = 2,
94 .wdt_enable = &mv_wdt_enable_armv5,
95 .wdt_disable = &mv_wdt_disable_armv5,
96 .wdt_clock_src = 0,
97 };
98
99 struct mv_wdt_softc {
100 struct resource * wdt_res;
101 struct mtx wdt_mtx;
102 struct mv_wdt_config * wdt_config;
103 };
104
105 static struct resource_spec mv_wdt_spec[] = {
106 { SYS_RES_MEMORY, 0, RF_ACTIVE },
107 { -1, 0 }
108 };
109
110 static struct ofw_compat_data mv_wdt_compat[] = {
111 {"marvell,armada-380-wdt", (uintptr_t)&mv_wdt_armada_38x_config},
112 {"marvell,armada-xp-wdt", (uintptr_t)&mv_wdt_armada_xp_config},
113 {"marvell,orion-wdt", (uintptr_t)&mv_wdt_armv5_config},
114 {NULL, (uintptr_t)NULL}
115 };
116
117 static struct mv_wdt_softc *wdt_softc = NULL;
118 int timers_initialized = 0;
119
120 static int mv_wdt_probe(device_t);
121 static int mv_wdt_attach(device_t);
122
123 static uint32_t mv_get_timer_control(void);
124 static void mv_set_timer_control(uint32_t);
125 static void mv_set_timer(uint32_t, uint32_t);
126
127 static void mv_watchdog_event(void *, unsigned int, int *);
128
129 static device_method_t mv_wdt_methods[] = {
130 DEVMETHOD(device_probe, mv_wdt_probe),
131 DEVMETHOD(device_attach, mv_wdt_attach),
132 { 0, 0 }
133 };
134
135 static driver_t mv_wdt_driver = {
136 "wdt",
137 mv_wdt_methods,
138 sizeof(struct mv_wdt_softc),
139 };
140
141 DRIVER_MODULE(wdt, simplebus, mv_wdt_driver, 0, 0);
142
143 static int
mv_wdt_probe(device_t dev)144 mv_wdt_probe(device_t dev)
145 {
146
147 if (!ofw_bus_status_okay(dev))
148 return (ENXIO);
149
150 if (!ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data)
151 return (ENXIO);
152
153 device_set_desc(dev, "Marvell Watchdog Timer");
154 return (0);
155 }
156
157 static int
mv_wdt_attach(device_t dev)158 mv_wdt_attach(device_t dev)
159 {
160 struct mv_wdt_softc *sc;
161 int error;
162
163 if (wdt_softc != NULL)
164 return (ENXIO);
165
166 sc = device_get_softc(dev);
167 wdt_softc = sc;
168
169 error = bus_alloc_resources(dev, mv_wdt_spec, &sc->wdt_res);
170 if (error) {
171 device_printf(dev, "could not allocate resources\n");
172 return (ENXIO);
173 }
174
175 mtx_init(&sc->wdt_mtx, "watchdog", NULL, MTX_DEF);
176
177 sc->wdt_config = (struct mv_wdt_config *)
178 ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data;
179
180 if (sc->wdt_config->wdt_clock_src == 0)
181 sc->wdt_config->wdt_clock_src = get_tclk();
182
183 if (wdt_softc->wdt_config->wdt_disable != NULL)
184 wdt_softc->wdt_config->wdt_disable();
185 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
186
187 return (0);
188 }
189
190 static __inline uint32_t
mv_get_timer_control(void)191 mv_get_timer_control(void)
192 {
193
194 return (bus_read_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL));
195 }
196
197 static __inline void
mv_set_timer_control(uint32_t val)198 mv_set_timer_control(uint32_t val)
199 {
200
201 bus_write_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL, val);
202 }
203
204 static __inline void
mv_set_timer(uint32_t timer,uint32_t val)205 mv_set_timer(uint32_t timer, uint32_t val)
206 {
207
208 bus_write_4(wdt_softc->wdt_res, CPU_TIMER0 + timer * 0x8, val);
209 }
210 static void
mv_wdt_enable_armv5(void)211 mv_wdt_enable_armv5(void)
212 {
213 uint32_t val, irq_cause, irq_mask;
214
215 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
216 irq_cause &= IRQ_TIMER_WD_CLR;
217 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
218
219 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
220 irq_mask |= IRQ_TIMER_WD_MASK;
221 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
222
223 val = read_cpu_ctrl(RSTOUTn_MASK);
224 val |= WD_RST_OUT_EN;
225 write_cpu_ctrl(RSTOUTn_MASK, val);
226
227 val = mv_get_timer_control();
228 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
229 mv_set_timer_control(val);
230 }
231
232 static inline void
mv_wdt_enable_armada_38x_xp_helper(void)233 mv_wdt_enable_armada_38x_xp_helper(void)
234 {
235 uint32_t val, irq_cause;
236
237 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
238 irq_cause &= IRQ_TIMER_WD_CLR;
239 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
240
241 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
242 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
243 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
244
245 val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
246 val &= ~RSTOUTn_MASK_WD;
247 write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
248 }
249
250 static void
mv_wdt_enable_armada_38x(void)251 mv_wdt_enable_armada_38x(void)
252 {
253 uint32_t val, irq_cause;
254
255 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
256 irq_cause &= IRQ_TIMER_WD_CLR;
257 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
258
259 mv_wdt_enable_armada_38x_xp_helper();
260
261 val = mv_get_timer_control();
262 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN;
263 mv_set_timer_control(val);
264 }
265
266 static void
mv_wdt_enable_armada_xp(void)267 mv_wdt_enable_armada_xp(void)
268 {
269 uint32_t val, irq_cause;
270 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP);
271 irq_cause &= IRQ_TIMER_WD_CLR_ARMADAXP;
272 write_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP, irq_cause);
273
274 mv_wdt_enable_armada_38x_xp_helper();
275
276 val = mv_get_timer_control();
277 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
278 mv_set_timer_control(val);
279 }
280
281 static void
mv_wdt_disable_armv5(void)282 mv_wdt_disable_armv5(void)
283 {
284 uint32_t val, irq_cause, irq_mask;
285
286 val = mv_get_timer_control();
287 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
288 mv_set_timer_control(val);
289
290 val = read_cpu_ctrl(RSTOUTn_MASK);
291 val &= ~WD_RST_OUT_EN;
292 write_cpu_ctrl(RSTOUTn_MASK, val);
293
294 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
295 irq_mask &= ~(IRQ_TIMER_WD_MASK);
296 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
297
298 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
299 irq_cause &= IRQ_TIMER_WD_CLR;
300 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
301 }
302
303 static __inline void
mv_wdt_disable_armada_38x_xp_helper(void)304 mv_wdt_disable_armada_38x_xp_helper(void)
305 {
306 uint32_t val;
307
308 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
309 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
310 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
311
312 val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
313 val |= RSTOUTn_MASK_WD;
314 write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
315 }
316
317 static void
mv_wdt_disable_armada_38x(void)318 mv_wdt_disable_armada_38x(void)
319 {
320 uint32_t val;
321
322 val = mv_get_timer_control();
323 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
324 mv_set_timer_control(val);
325
326 mv_wdt_disable_armada_38x_xp_helper();
327 }
328
329 static void
mv_wdt_disable_armada_xp(void)330 mv_wdt_disable_armada_xp(void)
331 {
332 uint32_t val;
333
334 val = mv_get_timer_control();
335 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
336 mv_set_timer_control(val);
337
338 mv_wdt_disable_armada_38x_xp_helper();
339 }
340
341 /*
342 * Watchdog event handler.
343 */
344 static void
mv_watchdog_event(void * arg,unsigned int cmd,int * error)345 mv_watchdog_event(void *arg, unsigned int cmd, int *error)
346 {
347 struct mv_wdt_softc *sc;
348 uint64_t ns;
349 uint64_t ticks;
350
351 sc = arg;
352 mtx_lock(&sc->wdt_mtx);
353 if (cmd == 0) {
354 if (wdt_softc->wdt_config->wdt_disable != NULL)
355 wdt_softc->wdt_config->wdt_disable();
356 } else {
357 /*
358 * Watchdog timeout is in nanosecs, calculation according to
359 * watchdog(9)
360 */
361 ns = (uint64_t)1 << (cmd & WD_INTERVAL);
362 ticks = (uint64_t)(ns * sc->wdt_config->wdt_clock_src) / 1000000000;
363 if (ticks > MAX_WATCHDOG_TICKS) {
364 if (wdt_softc->wdt_config->wdt_disable != NULL)
365 wdt_softc->wdt_config->wdt_disable();
366 }
367 else {
368 mv_set_timer(wdt_softc->wdt_config->wdt_timer, ticks);
369 if (wdt_softc->wdt_config->wdt_enable != NULL)
370 wdt_softc->wdt_config->wdt_enable();
371 *error = 0;
372 }
373 }
374 mtx_unlock(&sc->wdt_mtx);
375 }
376