1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #pragma ident "%Z%%M% %I% %E% SMI"
27
28 /*
29 * hci1394_ohci.c
30 * Provides access routines to the OpenHCI HW.
31 */
32
33 #include <sys/conf.h>
34 #include <sys/ddi.h>
35 #include <sys/modctl.h>
36 #include <sys/sunddi.h>
37 #include <sys/types.h>
38 #include <sys/mkdev.h>
39 #include <sys/kmem.h>
40 #include <sys/pci.h>
41
42 #include <sys/1394/adapters/hci1394.h>
43 #include <sys/1394/adapters/hci1394_extern.h>
44
45
46 /*
47 * Data swap macros used to swap config rom data that is going to be placed
48 * in OpenHCI registers. The config rom is treated like a byte stream. When
49 * the services layer calls into us to update the config rom, they pass us a
50 * byte stream of data. This works well except for the the fact that the
51 * hardware uses its internal registers for the first 5 quadlets. We have to
52 * copy the cfgrom header and bus options into their corresponding OpenHCI
53 * registers. On an x86 machine, this means we have to byte swap them first.
54 */
55 #ifdef _LITTLE_ENDIAN
56 #define OHCI_SWAP32(DATA) (ddi_swap32(DATA))
57 #else
58 #define OHCI_SWAP32(DATA) (DATA)
59 #endif
60
61
62 static int hci1394_ohci_selfid_init(hci1394_ohci_handle_t ohci_hdl);
63 static int hci1394_ohci_cfgrom_init(hci1394_ohci_handle_t ohci_hdl);
64 static int hci1394_ohci_chip_init(hci1394_ohci_handle_t ohci_hdl);
65 static int hci1394_ohci_phy_resume(hci1394_ohci_handle_t ohci_hdl);
66 static int hci1394_ohci_1394a_init(hci1394_ohci_handle_t ohci_hdl);
67 static int hci1394_ohci_1394a_resume(hci1394_ohci_handle_t ohci_hdl);
68 static int hci1394_ohci_phy_read_no_lock(hci1394_ohci_handle_t ohci_hdl,
69 uint_t address, uint_t *data);
70 static int hci1394_ohci_phy_write_no_lock(hci1394_ohci_handle_t ohci_hdl,
71 uint_t address, uint_t data);
72
73
74 /*
75 * hci1394_ohci_init()
76 * Initialize the OpenHCI hardware.
77 */
78 int
hci1394_ohci_init(hci1394_state_t * soft_state,hci1394_drvinfo_t * drvinfo,hci1394_ohci_handle_t * ohci_hdl)79 hci1394_ohci_init(hci1394_state_t *soft_state, hci1394_drvinfo_t *drvinfo,
80 hci1394_ohci_handle_t *ohci_hdl)
81 {
82 int status;
83 uint32_t version;
84 hci1394_ohci_t *ohci;
85 #if defined(__x86)
86 uint16_t cmdreg;
87 #endif
88
89
90 ASSERT(ohci_hdl != NULL);
91 TNF_PROBE_0_DEBUG(hci1394_ohci_init_enter, HCI1394_TNF_HAL_STACK, "");
92
93 /* alloc the space for ohci */
94 ohci = kmem_alloc(sizeof (hci1394_ohci_t), KM_SLEEP);
95 *ohci_hdl = ohci;
96
97 /*
98 * Start with the cycle timer rollover interrupt disabled. When it is
99 * enabled, we will get an interrupt every 64 seconds, even if we have
100 * nothing plugged into the bus. This interrupt is used to keep track
101 * of the bus time. We will enable the interrupt when the bus manager
102 * writes to the bus_time CSR register (Currently there are not known
103 * implementations that write to the bus_time register)
104 */
105 ohci->ohci_bustime_enabled = B_FALSE;
106 ohci->ohci_bustime_count = 0;
107
108 ohci->ohci_set_root_holdoff = B_FALSE;
109 ohci->ohci_set_gap_count = B_FALSE;
110 ohci->ohci_gap_count = 0;
111
112 mutex_init(&ohci->ohci_mutex, NULL, MUTEX_DRIVER,
113 drvinfo->di_iblock_cookie);
114
115 /* Map OpenHCI Registers */
116 status = ddi_regs_map_setup(drvinfo->di_dip, OHCI_REG_SET,
117 (caddr_t *)&ohci->ohci_regs, 0, 0, &drvinfo->di_reg_attr,
118 &ohci->ohci_reg_handle);
119 if (status != DDI_SUCCESS) {
120 mutex_destroy(&ohci->ohci_mutex);
121 kmem_free(ohci, sizeof (hci1394_ohci_t));
122 *ohci_hdl = NULL;
123 TNF_PROBE_0(ddi_regs_map_setup_fail, HCI1394_TNF_HAL_ERROR,
124 "");
125 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, HCI1394_TNF_HAL_STACK,
126 "");
127 return (DDI_FAILURE);
128 }
129
130 ohci->soft_state = soft_state;
131 ohci->ohci_drvinfo = drvinfo;
132
133 /*
134 * make sure PCI Master and PCI Memory Access are enabled on x86
135 * platforms. This may not be the case if plug and play OS is
136 * set in the BIOS
137 */
138 #if defined(__x86)
139 cmdreg = pci_config_get16(soft_state->pci_config, PCI_CONF_COMM);
140 if ((cmdreg & (PCI_COMM_MAE | PCI_COMM_ME)) != (PCI_COMM_MAE |
141 PCI_COMM_ME)) {
142 cmdreg |= PCI_COMM_MAE | PCI_COMM_ME;
143 pci_config_put16(soft_state->pci_config, PCI_CONF_COMM, cmdreg);
144 }
145 #endif
146
147 /*
148 * Initialize the openHCI chip. This is broken out because we need to
149 * do this when resuming too.
150 */
151 status = hci1394_ohci_chip_init(ohci);
152 if (status != DDI_SUCCESS) {
153 ddi_regs_map_free(&ohci->ohci_reg_handle);
154 mutex_destroy(&ohci->ohci_mutex);
155 kmem_free(ohci, sizeof (hci1394_ohci_t));
156 *ohci_hdl = NULL;
157 TNF_PROBE_0(hci1394_ohci_chip_init_fail, HCI1394_TNF_HAL_ERROR,
158 "");
159 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit,
160 HCI1394_TNF_HAL_STACK, "");
161 return (DDI_FAILURE);
162 }
163
164 /* Init the 1394 PHY */
165 status = hci1394_ohci_phy_init(ohci);
166 if (status != DDI_SUCCESS) {
167 (void) hci1394_ohci_soft_reset(ohci);
168 ddi_regs_map_free(&ohci->ohci_reg_handle);
169 mutex_destroy(&ohci->ohci_mutex);
170 kmem_free(ohci, sizeof (hci1394_ohci_t));
171 *ohci_hdl = NULL;
172 TNF_PROBE_0(hci1394_ohci_phy_init_fail,
173 HCI1394_TNF_HAL_ERROR, "");
174 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit,
175 HCI1394_TNF_HAL_STACK, "");
176 return (DDI_FAILURE);
177 }
178
179 /* Init 1394a features if present */
180 if (ohci->ohci_phy == H1394_PHY_1394A) {
181 status = hci1394_ohci_1394a_init(ohci);
182 if (status != DDI_SUCCESS) {
183 (void) hci1394_ohci_soft_reset(ohci);
184 ddi_regs_map_free(&ohci->ohci_reg_handle);
185 mutex_destroy(&ohci->ohci_mutex);
186 kmem_free(ohci, sizeof (hci1394_ohci_t));
187 *ohci_hdl = NULL;
188 TNF_PROBE_0(hci1394_ohci_1394a_init_fail,
189 HCI1394_TNF_HAL_ERROR, "");
190 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit,
191 HCI1394_TNF_HAL_STACK, "");
192 return (DDI_FAILURE);
193 }
194 }
195
196 /* save away guid, phy type, and vendor info */
197 soft_state->halinfo.guid = hci1394_ohci_guid(ohci);
198 soft_state->halinfo.phy = ohci->ohci_phy;
199 soft_state->vendor_info.ohci_vendor_id =
200 ddi_get32(ohci->ohci_reg_handle, &ohci->ohci_regs->vendor_id);
201 version = ddi_get32(ohci->ohci_reg_handle, &ohci->ohci_regs->version);
202 soft_state->vendor_info.ohci_version = version;
203
204 /* We do not support version < 1.0 */
205 if (OHCI_VERSION(version) == 0) {
206 cmn_err(CE_NOTE,
207 "hci1394(%d): OpenHCI version %x.%x is not supported",
208 drvinfo->di_instance, OHCI_VERSION(version),
209 OHCI_REVISION(version));
210 (void) hci1394_ohci_soft_reset(ohci);
211 ddi_regs_map_free(&ohci->ohci_reg_handle);
212 mutex_destroy(&ohci->ohci_mutex);
213 kmem_free(ohci, sizeof (hci1394_ohci_t));
214 *ohci_hdl = NULL;
215 TNF_PROBE_0(hci1394_ohci_selfid_init_fail,
216 HCI1394_TNF_HAL_ERROR, "");
217 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit,
218 HCI1394_TNF_HAL_STACK, "");
219 return (DDI_FAILURE);
220 }
221
222 /* Initialize the selfid buffer */
223 status = hci1394_ohci_selfid_init(ohci);
224 if (status != DDI_SUCCESS) {
225 (void) hci1394_ohci_soft_reset(ohci);
226 ddi_regs_map_free(&ohci->ohci_reg_handle);
227 mutex_destroy(&ohci->ohci_mutex);
228 kmem_free(ohci, sizeof (hci1394_ohci_t));
229 *ohci_hdl = NULL;
230 TNF_PROBE_0(hci1394_ohci_selfid_init_fail,
231 HCI1394_TNF_HAL_ERROR, "");
232 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit,
233 HCI1394_TNF_HAL_STACK, "");
234 return (DDI_FAILURE);
235 }
236
237 /* Initialize the config rom buffer */
238 status = hci1394_ohci_cfgrom_init(ohci);
239 if (status != DDI_SUCCESS) {
240 (void) hci1394_ohci_soft_reset(ohci);
241 hci1394_buf_free(&ohci->ohci_selfid_handle);
242 ddi_regs_map_free(&ohci->ohci_reg_handle);
243 mutex_destroy(&ohci->ohci_mutex);
244 kmem_free(ohci, sizeof (hci1394_ohci_t));
245 *ohci_hdl = NULL;
246 TNF_PROBE_0(hci1394_ohci_cfgrom_init_fail,
247 HCI1394_TNF_HAL_ERROR, "");
248 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit,
249 HCI1394_TNF_HAL_STACK, "");
250 return (DDI_FAILURE);
251 }
252
253 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit, HCI1394_TNF_HAL_STACK, "");
254
255 return (DDI_SUCCESS);
256 }
257
258
259 /*
260 * hci1394_ohci_fini()
261 * Cleanup after OpenHCI init. This should be called during detach.
262 */
263 void
hci1394_ohci_fini(hci1394_ohci_handle_t * ohci_hdl)264 hci1394_ohci_fini(hci1394_ohci_handle_t *ohci_hdl)
265 {
266 hci1394_ohci_t *ohci;
267
268
269 ASSERT(ohci_hdl != NULL);
270 TNF_PROBE_0_DEBUG(hci1394_ohci_fini_enter, HCI1394_TNF_HAL_STACK, "");
271
272 ohci = *ohci_hdl;
273
274 /* reset chip */
275 (void) hci1394_ohci_soft_reset(ohci);
276
277 /* Free config rom space */
278 hci1394_buf_free(&ohci->ohci_cfgrom_handle);
279
280 /* Free selfid buffer space */
281 hci1394_buf_free(&ohci->ohci_selfid_handle);
282
283 /* Free up the OpenHCI registers */
284 ddi_regs_map_free(&ohci->ohci_reg_handle);
285
286 mutex_destroy(&ohci->ohci_mutex);
287
288 /* Free the OpenHCI state space */
289 kmem_free(ohci, sizeof (hci1394_ohci_t));
290 *ohci_hdl = NULL;
291
292 TNF_PROBE_0_DEBUG(hci1394_ohci_fini_exit, HCI1394_TNF_HAL_STACK, "");
293 }
294
295
296 /*
297 * hci1394_ohci_chip_init()
298 * Initialize the OpenHCI registers. This contains the bulk of the initial
299 * register setup.
300 */
301 static int
hci1394_ohci_chip_init(hci1394_ohci_handle_t ohci_hdl)302 hci1394_ohci_chip_init(hci1394_ohci_handle_t ohci_hdl)
303 {
304 int status;
305
306
307 ASSERT(ohci_hdl != NULL);
308 TNF_PROBE_0_DEBUG(hci1394_ohci_chip_init_enter, HCI1394_TNF_HAL_STACK,
309 "");
310
311 /* Reset 1394 OHCI HW */
312 status = hci1394_ohci_soft_reset(ohci_hdl);
313 if (status != DDI_SUCCESS) {
314 TNF_PROBE_0(hci1394_ohci_soft_reset_fail,
315 HCI1394_TNF_HAL_ERROR, "");
316 TNF_PROBE_0_DEBUG(hci1394_ohci_init_exit,
317 HCI1394_TNF_HAL_STACK, "");
318 return (DDI_FAILURE);
319 }
320
321 /*
322 * Setup Host Control Register. The software reset does not put all
323 * registers in a known state. The Host Control Register is one of these
324 * registers. First make sure noByteSwapData and postedWriteEnable and
325 * are cleared.
326 */
327 ddi_put32(ohci_hdl->ohci_reg_handle,
328 &ohci_hdl->ohci_regs->hc_ctrl_clr, OHCI_HC_NO_BSWAP |
329 OHCI_HC_POSTWR_ENBL);
330
331 /*
332 * the determination if we should swap data is made during the PCI
333 * initialization.
334 */
335 if (ohci_hdl->soft_state->swap_data == B_FALSE) {
336 /*
337 * most hba's don't swap data. It will be swapped in the
338 * global swap for SPARC. Enable Link Power(LPS). Enable
339 * Posted Writes
340 */
341 ddi_put32(ohci_hdl->ohci_reg_handle,
342 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_NO_BSWAP |
343 OHCI_HC_LPS | OHCI_HC_POSTWR_ENBL);
344 } else {
345 /*
346 * Swap Data. Enable Link Power(LPS). Enable Posted Writes
347 */
348 ddi_put32(ohci_hdl->ohci_reg_handle,
349 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_LPS |
350 OHCI_HC_POSTWR_ENBL);
351 }
352
353 /*
354 * Wait for PHY to come up. There does not seem to be standard time for
355 * how long wait for the PHY to come up. The problem is that the PHY
356 * provides a clock to the link layer and if that is not stable, we
357 * could get a PCI timeout error when reading/writing a phy register
358 * (and maybe an OpenHCI register?) This used to be set to 10mS which
359 * works for just about every adapter we tested on. We got a new TI
360 * adapter which would crash the system once in a while if nothing
361 * (1394 device) was pluged into the adapter. Changing this delay to
362 * 50mS made that problem go away. This value is set via a patchable
363 * variable located in hci1394_extern.c
364 */
365 delay(drv_usectohz(hci1394_phy_stabilization_delay_uS));
366
367 /* Clear Isochrounous receive multi-chan mode registers */
368 ddi_put32(ohci_hdl->ohci_reg_handle,
369 &ohci_hdl->ohci_regs->ir_multi_maskhi_clr, 0xFFFFFFFF);
370 ddi_put32(ohci_hdl->ohci_reg_handle,
371 &ohci_hdl->ohci_regs->ir_multi_masklo_clr, 0xFFFFFFFF);
372
373 /*
374 * Setup async retry on busy or ack_data_error
375 * secondlimit = 0 <= bits 31-29
376 * cycleLimit = 0 <= bits 28-16
377 * maxPhysRespRetries = 0 <= bits 11-8
378 * maxARRespRetries = 0 <= bits 7-4
379 * maxATReqRetries = 2 <= bits 3-0
380 */
381 ddi_put32(ohci_hdl->ohci_reg_handle,
382 &ohci_hdl->ohci_regs->at_retries, 0x00000002);
383
384 /*
385 * Setup Link Control
386 * Enable cycleMaster, cycleTimerEnable, and rcvPhyPkt.
387 */
388 ddi_put32(ohci_hdl->ohci_reg_handle,
389 &ohci_hdl->ohci_regs->link_ctrl_clr, 0xFFFFFFFF);
390 ddi_put32(ohci_hdl->ohci_reg_handle,
391 &ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_CYC_MAST |
392 OHCI_LC_CTIME_ENBL | OHCI_LC_RCV_PHY);
393
394 /*
395 * Set the Physical address map boundary to 0x0000FFFFFFFF. The
396 * phys_upper_bound is the upper 32-bits of the 48-bit 1394 address. The
397 * lower 16 bits are assumed to be 0xFFFF.
398 */
399 ddi_put32(ohci_hdl->ohci_reg_handle,
400 &ohci_hdl->ohci_regs->phys_upper_bound, (uint32_t)0x0000FFFF);
401
402 /*
403 * Enable all async requests.
404 * The asyncReqResourceAll bit (0x80000000) does not get cleared during
405 * a bus reset. If this code is changed to selectively allow nodes to
406 * perform ARREQ's, the ARREQ filter bits will need to be updated after
407 * every bus reset.
408 */
409 ddi_put32(ohci_hdl->ohci_reg_handle,
410 &ohci_hdl->ohci_regs->ar_req_filterhi_set, (uint32_t)0x80000000);
411
412 /*
413 * clear isochronous interrupt event and mask registers clearing the
414 * mask registers disable all isoc tx & rx ints
415 */
416 ddi_put32(ohci_hdl->ohci_reg_handle,
417 &ohci_hdl->ohci_regs->it_intr_event_clr, (uint32_t)0xFFFFFFFF);
418 ddi_put32(ohci_hdl->ohci_reg_handle,
419 &ohci_hdl->ohci_regs->it_intr_mask_clr, (uint32_t)0xFFFFFFFF);
420 ddi_put32(ohci_hdl->ohci_reg_handle,
421 &ohci_hdl->ohci_regs->ir_intr_event_clr, (uint32_t)0xFFFFFFFF);
422 ddi_put32(ohci_hdl->ohci_reg_handle,
423 &ohci_hdl->ohci_regs->ir_intr_mask_clr, (uint32_t)0xFFFFFFFF);
424
425 /* Clear interrupt event/mask register */
426 ddi_put32(ohci_hdl->ohci_reg_handle,
427 &ohci_hdl->ohci_regs->intr_event_clr, (uint32_t)0xFFFFFFFF);
428 ddi_put32(ohci_hdl->ohci_reg_handle,
429 &ohci_hdl->ohci_regs->intr_mask_clr, (uint32_t)0xFFFFFFFF);
430
431 TNF_PROBE_0_DEBUG(hci1394_ohci_chip_init_exit, HCI1394_TNF_HAL_STACK,
432 "");
433 return (DDI_SUCCESS);
434 }
435
436
437 /*
438 * hci1394_ohci_soft_reset()
439 * Reset OpenHCI HW.
440 */
441 int
hci1394_ohci_soft_reset(hci1394_ohci_handle_t ohci_hdl)442 hci1394_ohci_soft_reset(hci1394_ohci_handle_t ohci_hdl)
443 {
444 uint32_t resetStatus;
445
446
447 ASSERT(ohci_hdl != NULL);
448 TNF_PROBE_0_DEBUG(hci1394_ohci_soft_reset_enter,
449 HCI1394_TNF_HAL_STACK, "");
450
451 /* Reset 1394 HW - Reset is bit 16 in HCControl */
452 ddi_put32(ohci_hdl->ohci_reg_handle,
453 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_SOFT_RESET);
454
455 /* Wait for reset to complete */
456 drv_usecwait(OHCI_CHIP_RESET_TIME_IN_uSEC);
457
458 /* Verify reset is complete */
459 resetStatus = ddi_get32(ohci_hdl->ohci_reg_handle,
460 &ohci_hdl->ohci_regs->hc_ctrl_set);
461 resetStatus = resetStatus & OHCI_HC_SOFT_RESET;
462 if (resetStatus != 0) {
463 TNF_PROBE_0(hci1394_ohci_reset_not_complete_fail,
464 HCI1394_TNF_HAL_ERROR, "");
465 TNF_PROBE_0_DEBUG(hci1394_ohci_soft_reset_exit,
466 HCI1394_TNF_HAL_STACK, "");
467 return (DDI_FAILURE);
468 }
469
470 TNF_PROBE_0_DEBUG(hci1394_ohci_soft_reset_exit,
471 HCI1394_TNF_HAL_STACK, "");
472
473 return (DDI_SUCCESS);
474 }
475
476
477 /*
478 * hci1394_ohci_reg_read()
479 * Read OpenHCI register. This is called from the test ioctl interface
480 * through devctl.
481 */
482 void
hci1394_ohci_reg_read(hci1394_ohci_handle_t ohci_hdl,uint_t offset,uint32_t * data)483 hci1394_ohci_reg_read(hci1394_ohci_handle_t ohci_hdl,
484 uint_t offset, uint32_t *data)
485 {
486 uint32_t *addr;
487
488
489 ASSERT(ohci_hdl != NULL);
490 ASSERT(data != NULL);
491 TNF_PROBE_0_DEBUG(hci1394_ohci_reg_read_enter,
492 HCI1394_TNF_HAL_STACK, "");
493
494 addr = (uint32_t *)((uintptr_t)ohci_hdl->ohci_regs +
495 (uintptr_t)(offset & OHCI_REG_ADDR_MASK));
496 *data = ddi_get32(ohci_hdl->ohci_reg_handle, addr);
497
498 TNF_PROBE_0_DEBUG(hci1394_ohci_reg_read_exit,
499 HCI1394_TNF_HAL_STACK, "");
500 }
501
502
503 /*
504 * hci1394_ohci_reg_write()
505 * Write OpenHCI register. This is called from the test ioctl interface
506 * through devctl.
507 */
508 void
hci1394_ohci_reg_write(hci1394_ohci_handle_t ohci_hdl,uint_t offset,uint32_t data)509 hci1394_ohci_reg_write(hci1394_ohci_handle_t ohci_hdl,
510 uint_t offset, uint32_t data)
511 {
512 uint32_t *addr;
513
514
515 ASSERT(ohci_hdl != NULL);
516 TNF_PROBE_0_DEBUG(hci1394_ohci_reg_read_enter,
517 HCI1394_TNF_HAL_STACK, "");
518
519 addr = (uint32_t *)((uintptr_t)ohci_hdl->ohci_regs +
520 (uintptr_t)(offset & OHCI_REG_ADDR_MASK));
521 ddi_put32(ohci_hdl->ohci_reg_handle, addr, data);
522
523 TNF_PROBE_0_DEBUG(hci1394_ohci_reg_read_exit,
524 HCI1394_TNF_HAL_STACK, "");
525 }
526
527
528 /*
529 * hci1394_ohci_intr_master_enable()
530 * Enable interrupts to be passed on from OpenHCI. This is a global mask.
531 * Individual interrupts still need to be enabled for interrupts to be
532 * generated.
533 */
534 void
hci1394_ohci_intr_master_enable(hci1394_ohci_handle_t ohci_hdl)535 hci1394_ohci_intr_master_enable(hci1394_ohci_handle_t ohci_hdl)
536 {
537 ASSERT(ohci_hdl != NULL);
538 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_master_enable_enter,
539 HCI1394_TNF_HAL_STACK, "");
540
541 ddi_put32(ohci_hdl->ohci_reg_handle,
542 &ohci_hdl->ohci_regs->intr_mask_set, OHCI_INTR_MASTER_INTR_ENBL);
543
544 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_master_enable_exit,
545 HCI1394_TNF_HAL_STACK, "");
546 }
547
548
549 /*
550 * hci1394_ohci_intr_master_disable()
551 * Disable all OpenHCI interrupts from being passed on. This does not affect
552 * the individual interrupt mask settings. When interrupts are enabled
553 * again, the same individual interrupts will still be enabled.
554 */
555 void
hci1394_ohci_intr_master_disable(hci1394_ohci_handle_t ohci_hdl)556 hci1394_ohci_intr_master_disable(hci1394_ohci_handle_t ohci_hdl)
557 {
558 ASSERT(ohci_hdl != NULL);
559 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_master_disable_enter,
560 HCI1394_TNF_HAL_STACK, "");
561
562 ddi_put32(ohci_hdl->ohci_reg_handle,
563 &ohci_hdl->ohci_regs->intr_mask_clr, OHCI_INTR_MASTER_INTR_ENBL);
564
565 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_master_disable_exit,
566 HCI1394_TNF_HAL_STACK, "");
567 }
568
569
570 /*
571 * hci1394_ohci_intr_asserted()
572 * Return which ENABLED interrupts are asserted. If an interrupt is disabled
573 * via its mask bit, it will not be returned from here.
574 *
575 * NOTE: we may want to make this a macro at some point.
576 */
577 uint32_t
hci1394_ohci_intr_asserted(hci1394_ohci_handle_t ohci_hdl)578 hci1394_ohci_intr_asserted(hci1394_ohci_handle_t ohci_hdl)
579 {
580 uint32_t interrupts_asserted;
581
582 ASSERT(ohci_hdl != NULL);
583 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_asserted_enter,
584 HCI1394_TNF_HAL_STACK, "");
585
586 /*
587 * Only look at interrupts which are enabled by reading the
588 * intr_event_clr register.
589 */
590 interrupts_asserted = ddi_get32(ohci_hdl->ohci_reg_handle,
591 &ohci_hdl->ohci_regs->intr_event_clr);
592
593 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_asserted_exit,
594 HCI1394_TNF_HAL_STACK, "");
595 return (interrupts_asserted);
596 }
597
598
599 /*
600 * hci1394_ohci_intr_enable()
601 * Enable an individual interrupt or set of interrupts. This does not affect
602 * the global interrupt mask.
603 */
604 void
hci1394_ohci_intr_enable(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)605 hci1394_ohci_intr_enable(hci1394_ohci_handle_t ohci_hdl,
606 uint32_t interrupt_mask)
607 {
608 ASSERT(ohci_hdl != NULL);
609 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_enable_enter,
610 HCI1394_TNF_HAL_STACK, "");
611
612 ddi_put32(ohci_hdl->ohci_reg_handle,
613 &ohci_hdl->ohci_regs->intr_mask_set, interrupt_mask);
614
615 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_enable_exit,
616 HCI1394_TNF_HAL_STACK, "");
617 }
618
619
620 /*
621 * hci1394_ohci_intr_disable()
622 * Disable an individual interrupt or set of interrupts. This does not affect
623 * the global interrupt mask.
624 */
625 void
hci1394_ohci_intr_disable(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)626 hci1394_ohci_intr_disable(hci1394_ohci_handle_t ohci_hdl,
627 uint32_t interrupt_mask)
628 {
629 ASSERT(ohci_hdl != NULL);
630 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_disable_enter,
631 HCI1394_TNF_HAL_STACK, "");
632
633 ddi_put32(ohci_hdl->ohci_reg_handle,
634 &ohci_hdl->ohci_regs->intr_mask_clr, interrupt_mask);
635
636 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_disable_exit,
637 HCI1394_TNF_HAL_STACK, "");
638 }
639
640
641 /*
642 * hci1394_ohci_intr_clear()
643 * Clear a set of interrupts so that they are not asserted anymore.
644 *
645 * NOTE: we may want to make this a macro at some point.
646 */
647 void
hci1394_ohci_intr_clear(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)648 hci1394_ohci_intr_clear(hci1394_ohci_handle_t ohci_hdl,
649 uint32_t interrupt_mask)
650 {
651 ASSERT(ohci_hdl != NULL);
652 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_clear_enter,
653 HCI1394_TNF_HAL_STACK, "");
654
655 ddi_put32(ohci_hdl->ohci_reg_handle,
656 &ohci_hdl->ohci_regs->intr_event_clr, interrupt_mask);
657 TNF_PROBE_1_DEBUG(hci1394_ohci_intr_clear, HCI1394_TNF_HAL, "",
658 tnf_uint, intr_mask, interrupt_mask);
659
660 TNF_PROBE_0_DEBUG(hci1394_ohci_intr_clear_exit,
661 HCI1394_TNF_HAL_STACK, "");
662 }
663
664
665 /*
666 * hci1394_ohci_it_intr_asserted()
667 * Return which ENABLED isoch TX interrupts are asserted. If an interrupt is
668 * disabled via its mask bit, it will not be returned from here.
669 *
670 * NOTE: we may want to make this a macro at some point.
671 */
672 uint32_t
hci1394_ohci_it_intr_asserted(hci1394_ohci_handle_t ohci_hdl)673 hci1394_ohci_it_intr_asserted(hci1394_ohci_handle_t ohci_hdl)
674 {
675 uint32_t interrupts_asserted;
676
677 ASSERT(ohci_hdl != NULL);
678 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_asserted_enter,
679 HCI1394_TNF_HAL_STACK, "");
680
681 /* Only look at interrupts which are enabled */
682 interrupts_asserted = ddi_get32(ohci_hdl->ohci_reg_handle,
683 &ohci_hdl->ohci_regs->it_intr_event_clr);
684
685 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_asserted_exit,
686 HCI1394_TNF_HAL_STACK, "");
687 return (interrupts_asserted);
688 }
689
690
691 /*
692 * hci1394_ohci_it_intr_enable()
693 * Enable an individual isoch TX interrupt. This does not affect the general
694 * isoch interrupt mask in the OpenHCI Mask register. That is enabled/
695 * disabled via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable.
696 */
697 void
hci1394_ohci_it_intr_enable(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)698 hci1394_ohci_it_intr_enable(hci1394_ohci_handle_t ohci_hdl,
699 uint32_t interrupt_mask)
700 {
701 ASSERT(ohci_hdl != NULL);
702 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_enable_enter,
703 HCI1394_TNF_HAL_STACK, "");
704
705 ddi_put32(ohci_hdl->ohci_reg_handle,
706 &ohci_hdl->ohci_regs->it_intr_mask_set, interrupt_mask);
707
708 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_enable_exit,
709 HCI1394_TNF_HAL_STACK, "");
710 }
711
712
713 /*
714 * hci1394_ohci_it_intr_disable()
715 * Disable an individual isoch TX interrupt. This does not affect the general
716 * isoch interrupt mask in the OpenHCI Mask register. That is enabled/
717 * disabled via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable.
718 */
719 void
hci1394_ohci_it_intr_disable(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)720 hci1394_ohci_it_intr_disable(hci1394_ohci_handle_t ohci_hdl,
721 uint32_t interrupt_mask)
722 {
723 ASSERT(ohci_hdl != NULL);
724 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_disable_enter,
725 HCI1394_TNF_HAL_STACK, "");
726
727 ddi_put32(ohci_hdl->ohci_reg_handle,
728 &ohci_hdl->ohci_regs->it_intr_mask_clr, interrupt_mask);
729
730 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_disable_exit,
731 HCI1394_TNF_HAL_STACK, "");
732 }
733
734
735 /*
736 * hci1394_ohci_it_intr_clear()
737 * Clear an individual isoch TX interrupt so that it is not asserted anymore.
738 *
739 * NOTE: we may want to make this a macro at some point.
740 */
741 void
hci1394_ohci_it_intr_clear(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)742 hci1394_ohci_it_intr_clear(hci1394_ohci_handle_t ohci_hdl,
743 uint32_t interrupt_mask)
744 {
745 ASSERT(ohci_hdl != NULL);
746 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_clear_enter,
747 HCI1394_TNF_HAL_STACK, "");
748
749 ddi_put32(ohci_hdl->ohci_reg_handle,
750 &ohci_hdl->ohci_regs->it_intr_event_clr, interrupt_mask);
751
752 TNF_PROBE_0_DEBUG(hci1394_ohci_it_intr_clear_exit,
753 HCI1394_TNF_HAL_STACK, "");
754 }
755
756
757 /*
758 * hci1394_ohci_it_ctxt_count_get()
759 * Determine the number of supported isochronous transmit contexts.
760 */
761 int
hci1394_ohci_it_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl)762 hci1394_ohci_it_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl)
763 {
764 uint32_t channel_mask;
765 int count;
766
767 ASSERT(ohci_hdl != NULL);
768 TNF_PROBE_0_DEBUG(hci1394_ohci_it_ctxt_count_get_enter,
769 HCI1394_TNF_HAL_STACK, "");
770
771 /*
772 * hw is required to support contexts 0 to N, where N <= 31
773 * the interrupt mask bits are wired to ground for unsupported
774 * contexts. Write 1's to all it mask bits, then read the mask.
775 * Implemented contexts will read (sequentially) as 1
776 */
777 ddi_put32(ohci_hdl->ohci_reg_handle,
778 &ohci_hdl->ohci_regs->it_intr_mask_set, 0xFFFFFFFF);
779 channel_mask = ddi_get32(ohci_hdl->ohci_reg_handle,
780 &ohci_hdl->ohci_regs->it_intr_mask_set);
781 count = 0;
782 while (channel_mask != 0) {
783 channel_mask = channel_mask >> 1;
784 count++;
785 }
786
787 TNF_PROBE_0_DEBUG(hci1394_ohci_it_ctxt_count_get_exit,
788 HCI1394_TNF_HAL_STACK, "");
789 return (count);
790 }
791
792
793 /*
794 * hci1394_ohci_it_cmd_ptr_set()
795 * Set the context pointer for a given isoch TX context. This is the IO
796 * address for the HW to fetch the first descriptor. The context should
797 * not be running when this routine is called.
798 */
799 void
hci1394_ohci_it_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl,uint_t context_number,uint32_t io_addr)800 hci1394_ohci_it_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl,
801 uint_t context_number, uint32_t io_addr)
802 {
803 ASSERT(ohci_hdl != NULL);
804 TNF_PROBE_0_DEBUG(hci1394_ohci_it_cmd_ptr_set_enter,
805 HCI1394_TNF_HAL_STACK, "");
806
807 ddi_put32(ohci_hdl->ohci_reg_handle,
808 &ohci_hdl->ohci_regs->it[context_number].cmd_ptrlo,
809 io_addr);
810
811 TNF_PROBE_0_DEBUG(hci1394_ohci_it_cmd_ptr_set_exit,
812 HCI1394_TNF_HAL_STACK, "");
813 }
814
815
816 /*
817 * hci1394_ohci_ir_intr_asserted()
818 * Return which ENABLED isoch RX interrupts are asserted. If an interrupt is
819 * disabled via its mask bit, it will not be returned from here.
820 *
821 * NOTE: we may want to make this a macro at some point.
822 */
823 uint32_t
hci1394_ohci_ir_intr_asserted(hci1394_ohci_handle_t ohci_hdl)824 hci1394_ohci_ir_intr_asserted(hci1394_ohci_handle_t ohci_hdl)
825 {
826 uint32_t interrupts_asserted;
827
828 ASSERT(ohci_hdl != NULL);
829 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_asserted_enter,
830 HCI1394_TNF_HAL_STACK, "");
831
832 /* Only look at interrupts which are enabled */
833 interrupts_asserted = ddi_get32(ohci_hdl->ohci_reg_handle,
834 &ohci_hdl->ohci_regs->ir_intr_event_clr);
835
836 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_asserted_exit,
837 HCI1394_TNF_HAL_STACK, "");
838 return (interrupts_asserted);
839 }
840
841
842 /*
843 * hci1394_ohci_ir_intr_enable()
844 * Enable an individual isoch RX interrupt. This does not affect the isoch
845 * interrupt mask in the OpenHCI Mask register. That is enabled/disabled
846 * via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable.
847 */
848 void
hci1394_ohci_ir_intr_enable(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)849 hci1394_ohci_ir_intr_enable(hci1394_ohci_handle_t ohci_hdl,
850 uint32_t interrupt_mask)
851 {
852 ASSERT(ohci_hdl != NULL);
853 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_enable_enter,
854 HCI1394_TNF_HAL_STACK, "");
855
856 ddi_put32(ohci_hdl->ohci_reg_handle,
857 &ohci_hdl->ohci_regs->ir_intr_mask_set, interrupt_mask);
858
859 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_enable_exit,
860 HCI1394_TNF_HAL_STACK, "");
861 }
862
863
864 /*
865 * hci1394_ohci_ir_intr_disable()
866 * Disable an individual isoch RX interrupt. This does not affect the isoch
867 * interrupt mask in the OpenHCI Mask register. That is enabled/disabled
868 * via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable.
869 */
870 void
hci1394_ohci_ir_intr_disable(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)871 hci1394_ohci_ir_intr_disable(hci1394_ohci_handle_t ohci_hdl,
872 uint32_t interrupt_mask)
873 {
874 ASSERT(ohci_hdl != NULL);
875 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_disable_enter,
876 HCI1394_TNF_HAL_STACK, "");
877
878 ddi_put32(ohci_hdl->ohci_reg_handle,
879 &ohci_hdl->ohci_regs->ir_intr_mask_clr, interrupt_mask);
880
881 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_disable_exit,
882 HCI1394_TNF_HAL_STACK, "");
883 }
884
885
886 /*
887 * hci1394_ohci_ir_intr_clear()
888 * Clear an individual isoch RX interrupt so that it is not asserted anymore.
889 *
890 * NOTE: we may want to make this a macro at some point.
891 */
892 void
hci1394_ohci_ir_intr_clear(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)893 hci1394_ohci_ir_intr_clear(hci1394_ohci_handle_t ohci_hdl,
894 uint32_t interrupt_mask)
895 {
896 ASSERT(ohci_hdl != NULL);
897 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_clear_enter,
898 HCI1394_TNF_HAL_STACK, "");
899
900 ddi_put32(ohci_hdl->ohci_reg_handle,
901 &ohci_hdl->ohci_regs->ir_intr_event_clr, interrupt_mask);
902
903 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_intr_clear_exit,
904 HCI1394_TNF_HAL_STACK, "");
905 }
906
907
908 /*
909 * hci1394_ohci_ir_ctxt_count_get()
910 * Determine the number of supported isochronous receive contexts.
911 */
912 int
hci1394_ohci_ir_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl)913 hci1394_ohci_ir_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl)
914 {
915 uint32_t channel_mask;
916 int count;
917
918 ASSERT(ohci_hdl != NULL);
919 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_ctxt_count_get_enter,
920 HCI1394_TNF_HAL_STACK, "");
921
922 /*
923 * hw is required to support contexts 0 to N, where N <= 31
924 * the interrupt mask bits are wired to ground for unsupported
925 * contexts. Write 1's to all ir mask bits, then read the mask.
926 * Implemented contexts will read (sequentially) as 1
927 */
928 ddi_put32(ohci_hdl->ohci_reg_handle,
929 &ohci_hdl->ohci_regs->ir_intr_mask_set, 0xFFFFFFFF);
930 channel_mask = ddi_get32(ohci_hdl->ohci_reg_handle,
931 &ohci_hdl->ohci_regs->ir_intr_mask_set);
932 count = 0;
933 while (channel_mask != 0) {
934 channel_mask = channel_mask >> 1;
935 count++;
936 }
937
938 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_ctxt_count_get_exit,
939 HCI1394_TNF_HAL_STACK, "");
940 return (count);
941 }
942
943
944 /*
945 * hci1394_ohci_ir_cmd_ptr_set()
946 * Set the context pointer for a given isoch RX context. This is the IO
947 * address for the HW to fetch the first descriptor. The context should
948 * not be running when this routine is called.
949 */
950 void
hci1394_ohci_ir_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl,uint_t context_number,uint32_t io_addr)951 hci1394_ohci_ir_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl,
952 uint_t context_number, uint32_t io_addr)
953 {
954 ASSERT(ohci_hdl != NULL);
955 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_cmd_ptr_set_enter,
956 HCI1394_TNF_HAL_STACK, "");
957
958 ddi_put32(ohci_hdl->ohci_reg_handle,
959 &ohci_hdl->ohci_regs->ir[context_number].cmd_ptrlo,
960 io_addr);
961
962 TNF_PROBE_0_DEBUG(hci1394_ohci_ir_cmd_ptr_set_exit,
963 HCI1394_TNF_HAL_STACK, "");
964 }
965
966
967 /*
968 * hci1394_ohci_link_enable()
969 * Enable the 1394 link layer. When the link is enabled, the PHY will pass
970 * up any 1394 bus transactions which would normally come up to the link.
971 */
972 void
hci1394_ohci_link_enable(hci1394_ohci_handle_t ohci_hdl)973 hci1394_ohci_link_enable(hci1394_ohci_handle_t ohci_hdl)
974 {
975 ASSERT(ohci_hdl != NULL);
976 TNF_PROBE_0_DEBUG(hci1394_ohci_link_enable_enter,
977 HCI1394_TNF_HAL_STACK, "");
978
979 ddi_put32(ohci_hdl->ohci_reg_handle,
980 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_LINK_ENBL);
981
982 TNF_PROBE_0_DEBUG(hci1394_ohci_link_enable_exit,
983 HCI1394_TNF_HAL_STACK, "");
984 }
985
986
987 /*
988 * hci1394_ohci_link_disable()
989 * Disable the 1394 link layer. When the link is disabled, the PHY will NOT
990 * pass up any 1394 bus transactions which would normally come up to the
991 * link. This "logically" disconnects us from the 1394 bus.
992 */
993 void
hci1394_ohci_link_disable(hci1394_ohci_handle_t ohci_hdl)994 hci1394_ohci_link_disable(hci1394_ohci_handle_t ohci_hdl)
995 {
996 ASSERT(ohci_hdl != NULL);
997 TNF_PROBE_0_DEBUG(hci1394_ohci_link_disable_enter,
998 HCI1394_TNF_HAL_STACK, "");
999
1000 ddi_put32(ohci_hdl->ohci_reg_handle,
1001 &ohci_hdl->ohci_regs->hc_ctrl_clr, OHCI_HC_LINK_ENBL);
1002
1003 TNF_PROBE_0_DEBUG(hci1394_ohci_link_disable_exit,
1004 HCI1394_TNF_HAL_STACK, "");
1005 }
1006
1007
1008 /*
1009 * hci1394_ohci_bus_reset()
1010 * Reset the 1394 bus. This performs a "long" bus reset and can be called
1011 * when the adapter has either a 1394-1995 or 1394A PHY.
1012 */
1013 int
hci1394_ohci_bus_reset(hci1394_ohci_handle_t ohci_hdl)1014 hci1394_ohci_bus_reset(hci1394_ohci_handle_t ohci_hdl)
1015 {
1016 int status;
1017 uint_t reg;
1018
1019
1020 ASSERT(ohci_hdl != NULL);
1021 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_enter,
1022 HCI1394_TNF_HAL_STACK, "");
1023
1024 /*
1025 * We want to reset the bus. We also handle the root_holdoff and gap
1026 * count cacheing explained at the top of this file.
1027 */
1028 reg = OHCI_PHY_IBR;
1029 if (ohci_hdl->ohci_set_root_holdoff == B_TRUE) {
1030 reg = reg | OHCI_PHY_RHB;
1031 }
1032 if (ohci_hdl->ohci_set_gap_count == B_TRUE) {
1033 reg = reg | ohci_hdl->ohci_gap_count;
1034 } else {
1035 reg = reg | OHCI_PHY_MAX_GAP;
1036 }
1037
1038 /*
1039 * Reset the bus. We intentionally do NOT do a PHY read here. A PHY
1040 * read could introduce race conditions and would be more likely to fail
1041 * due to a timeout.
1042 */
1043 status = hci1394_ohci_phy_write(ohci_hdl, 0x1, reg);
1044 if (status != DDI_SUCCESS) {
1045 TNF_PROBE_0(hci1394_ohci_phy_write_fail,
1046 HCI1394_TNF_HAL_ERROR, "");
1047 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_exit,
1048 HCI1394_TNF_HAL_STACK, "");
1049 return (DDI_FAILURE);
1050 }
1051
1052 /* clear the root holdoff and gap count state bits */
1053 ohci_hdl->ohci_set_root_holdoff = B_FALSE;
1054 ohci_hdl->ohci_set_gap_count = B_FALSE;
1055
1056 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_exit,
1057 HCI1394_TNF_HAL_STACK, "");
1058
1059 return (DDI_SUCCESS);
1060 }
1061
1062 /*
1063 *
1064 * hci1394_ohci_bus_reset_nroot()
1065 * Reset the 1394 bus. This performs a "long" bus reset with out a root.
1066 */
1067 int
hci1394_ohci_bus_reset_nroot(hci1394_ohci_handle_t ohci_hdl)1068 hci1394_ohci_bus_reset_nroot(hci1394_ohci_handle_t ohci_hdl)
1069 {
1070 int status;
1071 uint_t reg;
1072
1073 ASSERT(ohci_hdl != NULL);
1074
1075 /*
1076 * We want to reset the bus. We don't care about any holdoff
1077 * we are suspending need no root...
1078 */
1079 (void) hci1394_ohci_phy_read(ohci_hdl, 0x1, ®);
1080 reg = reg | OHCI_PHY_IBR;
1081 reg = reg & ~OHCI_PHY_RHB;
1082
1083 /*
1084 * Reset the bus. We intentionally do NOT do a PHY read here. A PHY
1085 * read could introduce race conditions and would be more likely to fail
1086 * due to a timeout.
1087 */
1088 status = hci1394_ohci_phy_write(ohci_hdl, 0x1, reg);
1089 if (status != DDI_SUCCESS) {
1090 TNF_PROBE_0(hci1394_ohci_phy_write_fail,
1091 HCI1394_TNF_HAL_ERROR, "");
1092 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_nroot_exit,
1093 HCI1394_TNF_HAL_STACK, "");
1094 return (DDI_FAILURE);
1095 }
1096
1097 return (DDI_SUCCESS);
1098 }
1099
1100 /*
1101 * hci1394_ohci_phy_init()
1102 * Setup the PHY. This should be called during attach and performs any PHY
1103 * initialization required including figuring out what kind of PHY we have.
1104 */
1105 int
hci1394_ohci_phy_init(hci1394_ohci_handle_t ohci_hdl)1106 hci1394_ohci_phy_init(hci1394_ohci_handle_t ohci_hdl)
1107 {
1108 int status;
1109 uint_t phy_reg;
1110
1111
1112 ASSERT(ohci_hdl != NULL);
1113 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_init_enter,
1114 HCI1394_TNF_HAL_STACK, "");
1115
1116 /*
1117 * if the phy has extended set to 7, the phy is a not a 1394-1995 PHY.
1118 * It could be a 1394a phy or beyond. The PHY type can be found in PHY
1119 * register page 1 in the compliance_level register.
1120 *
1121 * Since there are not any current standards beyond 1394A, we are going
1122 * to consider the PHY to be a 1394A phy if the extended bit is set.
1123 *
1124 * phy registers are byte wide registers and are addressed as 0, 1, 2,
1125 * 3, ... Phy register 0 may not be read or written.
1126 *
1127 * Phy register 0x2 (bit 0 MSB, 7 LSB)
1128 * Extended - bits 0 - 2
1129 * Total Ports - bits 4 - 7
1130 */
1131 status = hci1394_ohci_phy_read(ohci_hdl, 2, &phy_reg);
1132 if (status != DDI_SUCCESS) {
1133 TNF_PROBE_0(hci1394_ohci_phy_read_failed,
1134 HCI1394_TNF_HAL_ERROR, "");
1135 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_init_exit,
1136 HCI1394_TNF_HAL_STACK, "");
1137 return (DDI_FAILURE);
1138 }
1139
1140 if ((phy_reg & OHCI_PHY_EXTND_MASK) != OHCI_PHY_EXTND) {
1141 /*
1142 * if the extended bit is not set, we have to be a 1394-1995
1143 * PHY
1144 */
1145 ohci_hdl->ohci_phy = H1394_PHY_1995;
1146 } else {
1147 /* Treat all other PHY's as a 1394A PHY */
1148 ohci_hdl->ohci_phy = H1394_PHY_1394A;
1149 }
1150
1151 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_init_exit,
1152 HCI1394_TNF_HAL_STACK, "");
1153
1154 return (DDI_SUCCESS);
1155 }
1156
1157
1158 /*
1159 * hci1394_ohci_phy_resume()
1160 * re-initialize the PHY. This routine should be called during a resume after
1161 * a successful suspend has been done.
1162 */
1163 /* ARGSUSED */
1164 static int
hci1394_ohci_phy_resume(hci1394_ohci_handle_t ohci_hdl)1165 hci1394_ohci_phy_resume(hci1394_ohci_handle_t ohci_hdl)
1166 {
1167 ASSERT(ohci_hdl != NULL);
1168 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_resume_enter,
1169 HCI1394_TNF_HAL_STACK, "");
1170
1171 /* There is currently nothing to re-initialize here */
1172
1173 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_resume_exit,
1174 HCI1394_TNF_HAL_STACK, "");
1175
1176 return (DDI_SUCCESS);
1177 }
1178
1179
1180 /*
1181 * hci1394_ohci_phy_set()
1182 * Perform bitset operation on PHY register.
1183 */
1184 int
hci1394_ohci_phy_set(hci1394_ohci_handle_t ohci_hdl,uint_t address,uint_t bits)1185 hci1394_ohci_phy_set(hci1394_ohci_handle_t ohci_hdl, uint_t address,
1186 uint_t bits)
1187 {
1188 int status;
1189 uint_t reg;
1190
1191
1192 ASSERT(ohci_hdl != NULL);
1193 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_set_enter,
1194 HCI1394_TNF_HAL_STACK, "");
1195
1196 mutex_enter(&ohci_hdl->ohci_mutex);
1197
1198 /* read the PHY register */
1199 status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, ®);
1200 if (status != DDI_SUCCESS) {
1201 mutex_exit(&ohci_hdl->ohci_mutex);
1202 TNF_PROBE_0(hci1394_ohci_phy_read_fail,
1203 HCI1394_TNF_HAL_ERROR, "");
1204 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_set_exit,
1205 HCI1394_TNF_HAL_STACK, "");
1206 return (DDI_FAILURE);
1207 }
1208
1209 /* Set the bits and write the result back */
1210 reg = reg | bits;
1211 status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, reg);
1212 if (status != DDI_SUCCESS) {
1213 mutex_exit(&ohci_hdl->ohci_mutex);
1214 TNF_PROBE_0(hci1394_ohci_phy_write_fail,
1215 HCI1394_TNF_HAL_ERROR, "");
1216 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_set_exit,
1217 HCI1394_TNF_HAL_STACK, "");
1218 return (DDI_FAILURE);
1219 }
1220
1221 mutex_exit(&ohci_hdl->ohci_mutex);
1222
1223 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_set_exit, HCI1394_TNF_HAL_STACK,
1224 "");
1225
1226 return (DDI_SUCCESS);
1227 }
1228
1229
1230 /*
1231 * hci1394_ohci_phy_clr()
1232 * Perform bitclr operation on PHY register.
1233 */
1234 int
hci1394_ohci_phy_clr(hci1394_ohci_handle_t ohci_hdl,uint_t address,uint_t bits)1235 hci1394_ohci_phy_clr(hci1394_ohci_handle_t ohci_hdl, uint_t address,
1236 uint_t bits)
1237 {
1238 int status;
1239 uint_t reg;
1240
1241
1242 ASSERT(ohci_hdl != NULL);
1243 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_clr_enter,
1244 HCI1394_TNF_HAL_STACK, "");
1245
1246 mutex_enter(&ohci_hdl->ohci_mutex);
1247
1248 /* read the PHY register */
1249 status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, ®);
1250 if (status != DDI_SUCCESS) {
1251 mutex_exit(&ohci_hdl->ohci_mutex);
1252 TNF_PROBE_0(hci1394_ohci_phy_read_fail,
1253 HCI1394_TNF_HAL_ERROR, "");
1254 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_clr_exit,
1255 HCI1394_TNF_HAL_STACK, "");
1256 return (DDI_FAILURE);
1257 }
1258
1259 /* Set the bits and write the result back */
1260 reg = reg & ~bits;
1261 status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, reg);
1262 if (status != DDI_SUCCESS) {
1263 mutex_exit(&ohci_hdl->ohci_mutex);
1264 TNF_PROBE_0(hci1394_ohci_phy_write_fail,
1265 HCI1394_TNF_HAL_ERROR, "");
1266 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_clr_exit,
1267 HCI1394_TNF_HAL_STACK, "");
1268 return (DDI_FAILURE);
1269 }
1270
1271 mutex_exit(&ohci_hdl->ohci_mutex);
1272
1273 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_clr_exit, HCI1394_TNF_HAL_STACK,
1274 "");
1275
1276 return (DDI_SUCCESS);
1277 }
1278
1279
1280 /*
1281 * hci1394_ohci_phy_read()
1282 * Atomic PHY register read
1283 */
1284 int
hci1394_ohci_phy_read(hci1394_ohci_handle_t ohci_hdl,uint_t address,uint_t * data)1285 hci1394_ohci_phy_read(hci1394_ohci_handle_t ohci_hdl, uint_t address,
1286 uint_t *data)
1287 {
1288 int status;
1289
1290 ASSERT(ohci_hdl != NULL);
1291 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_enter, HCI1394_TNF_HAL_STACK,
1292 "");
1293 mutex_enter(&ohci_hdl->ohci_mutex);
1294 status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, data);
1295 mutex_exit(&ohci_hdl->ohci_mutex);
1296 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_exit, HCI1394_TNF_HAL_STACK,
1297 "");
1298
1299 return (status);
1300 }
1301
1302
1303 /*
1304 * hci1394_ohci_phy_write()
1305 * Atomic PHY register write
1306 */
1307 int
hci1394_ohci_phy_write(hci1394_ohci_handle_t ohci_hdl,uint_t address,uint_t data)1308 hci1394_ohci_phy_write(hci1394_ohci_handle_t ohci_hdl, uint_t address,
1309 uint_t data)
1310 {
1311 int status;
1312
1313 ASSERT(ohci_hdl != NULL);
1314 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_enter, HCI1394_TNF_HAL_STACK,
1315 "");
1316 mutex_enter(&ohci_hdl->ohci_mutex);
1317 status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, data);
1318 mutex_exit(&ohci_hdl->ohci_mutex);
1319 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit, HCI1394_TNF_HAL_STACK,
1320 "");
1321
1322 return (status);
1323 }
1324
1325
1326 /*
1327 * hci1394_ohci_phy_read_no_lock()
1328 * This routine actually performs the PHY register read. It is seperated
1329 * out from phy_read so set & clr lock can perform an atomic PHY register
1330 * operation. It assumes the OpenHCI mutex is held.
1331 */
1332 static int
hci1394_ohci_phy_read_no_lock(hci1394_ohci_handle_t ohci_hdl,uint_t address,uint_t * data)1333 hci1394_ohci_phy_read_no_lock(hci1394_ohci_handle_t ohci_hdl, uint_t address,
1334 uint_t *data)
1335 {
1336 uint32_t ohci_reg;
1337 int count;
1338
1339
1340 ASSERT(ohci_hdl != NULL);
1341 ASSERT(data != NULL);
1342 ASSERT(MUTEX_HELD(&ohci_hdl->ohci_mutex));
1343 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_enter,
1344 HCI1394_TNF_HAL_STACK, "");
1345
1346 /* You can't read or write PHY register #0 */
1347 if (address == 0) {
1348 TNF_PROBE_1(hci1394_ohci_phy_addr_fail, HCI1394_TNF_HAL_ERROR,
1349 "", tnf_string, errmsg, "can't rd/wr PHY reg #0");
1350 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_exit,
1351 HCI1394_TNF_HAL_STACK, "");
1352 return (DDI_FAILURE);
1353 }
1354
1355 /* Verify phy access not in progress */
1356 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1357 &ohci_hdl->ohci_regs->phy_ctrl);
1358 if ((ohci_reg & (OHCI_PHYC_RDREG | OHCI_PHYC_WRREG)) != 0) {
1359 TNF_PROBE_1(hci1394_ohci_phy_xfer_fail, HCI1394_TNF_HAL_ERROR,
1360 "", tnf_string, errmsg, "transfer already in progress?");
1361 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_exit,
1362 HCI1394_TNF_HAL_STACK, "");
1363 return (DDI_FAILURE);
1364 }
1365
1366 /* Start the PHY register read */
1367 ohci_reg = OHCI_PHYC_RDREG | ((address & 0xF) <<
1368 OHCI_PHYC_REGADDR_SHIFT);
1369 ddi_put32(ohci_hdl->ohci_reg_handle, &ohci_hdl->ohci_regs->phy_ctrl,
1370 ohci_reg);
1371
1372 /*
1373 * The PHY read usually takes less than 1uS. It is not worth having
1374 * this be interrupt driven. Having this be interrupt driven would also
1375 * make the bus reset and self id processing much more complex for
1376 * 1995 PHY's. We will wait up to hci1394_phy_delay_uS for the read
1377 * to complete (this was initially set to 10). I have yet to see
1378 * count > 1. The delay is a patchable variable.
1379 */
1380 count = 0;
1381 while (count < hci1394_phy_delay_uS) {
1382 /* See if the read is done yet */
1383 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1384 &ohci_hdl->ohci_regs->phy_ctrl);
1385 if ((ohci_reg & OHCI_PHYC_RDDONE) != 0) {
1386 /*
1387 * The read is done. clear the phyRegRecv interrupt. We
1388 * do not have this interrupt enabled but this keeps
1389 * things clean in case someone in the future does.
1390 * Break out of the loop, we are done.
1391 */
1392 ddi_put32(ohci_hdl->ohci_reg_handle,
1393 &ohci_hdl->ohci_regs->intr_event_clr,
1394 OHCI_INTR_PHY_REG_RCVD);
1395 break;
1396 }
1397
1398 /*
1399 * the phy read did not yet complete, wait 1uS, increment the
1400 * count and try again.
1401 */
1402 drv_usecwait(1);
1403 count++;
1404 }
1405
1406 /* Check to see if we timed out */
1407 if (count >= hci1394_phy_delay_uS) {
1408 /* we timed out, return failure */
1409 *data = 0;
1410 TNF_PROBE_0(hci1394_ohci_phy_rd_timeout_fail,
1411 HCI1394_TNF_HAL_ERROR, "");
1412 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_exit,
1413 HCI1394_TNF_HAL_STACK, "");
1414 return (DDI_FAILURE);
1415 }
1416
1417 /* setup the PHY read data to be returned */
1418 *data = (ddi_get32(ohci_hdl->ohci_reg_handle,
1419 &ohci_hdl->ohci_regs->phy_ctrl) & OHCI_PHYC_RDDATA_MASK) >>
1420 OHCI_PHYC_RDDATA_SHIFT;
1421
1422 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_read_no_lock_exit,
1423 HCI1394_TNF_HAL_STACK, "");
1424
1425 return (DDI_SUCCESS);
1426 }
1427
1428
1429 /*
1430 * hci1394_ohci_phy_write_no_lock()
1431 * This routine actually performs the PHY register write. It is separated
1432 * out from phy_write so set & clr lock can perform an atomic PHY register
1433 * operation. It assumes the OpenHCI mutex is held.
1434 */
1435 static int
hci1394_ohci_phy_write_no_lock(hci1394_ohci_handle_t ohci_hdl,uint_t address,uint_t data)1436 hci1394_ohci_phy_write_no_lock(hci1394_ohci_handle_t ohci_hdl, uint_t address,
1437 uint_t data)
1438 {
1439 uint32_t ohci_reg;
1440 int count;
1441
1442
1443 ASSERT(ohci_hdl != NULL);
1444 ASSERT(MUTEX_HELD(&ohci_hdl->ohci_mutex));
1445 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_enter,
1446 HCI1394_TNF_HAL_STACK, "");
1447
1448 /* You can't read or write PHY register #0 */
1449 if (address == 0) {
1450 TNF_PROBE_1(hci1394_ohci_phy_addr_fail, HCI1394_TNF_HAL_ERROR,
1451 "", tnf_string, errmsg, "can't rd/wr PHY reg #0");
1452 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit,
1453 HCI1394_TNF_HAL_STACK, "");
1454 return (DDI_FAILURE);
1455 }
1456
1457 /* Verify phy access not in progress */
1458 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1459 &ohci_hdl->ohci_regs->phy_ctrl);
1460 if ((ohci_reg & (OHCI_PHYC_RDREG | OHCI_PHYC_WRREG)) != 0) {
1461 TNF_PROBE_1(hci1394_ohci_phy_xfer_fail, HCI1394_TNF_HAL_ERROR,
1462 "", tnf_string, errmsg, "transfer already in progress?");
1463 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit,
1464 HCI1394_TNF_HAL_STACK, "");
1465 return (DDI_FAILURE);
1466 }
1467
1468 /* Start the PHY register write */
1469 ohci_reg = OHCI_PHYC_WRREG | ((address & 0xF) <<
1470 OHCI_PHYC_REGADDR_SHIFT) | (data & OHCI_PHYC_WRDATA_MASK);
1471 ddi_put32(ohci_hdl->ohci_reg_handle,
1472 &ohci_hdl->ohci_regs->phy_ctrl, ohci_reg);
1473
1474 /*
1475 * The PHY write usually takes less than 1uS. It is not worth having
1476 * this be interrupt driven. Having this be interrupt driven would also
1477 * make the bus reset and self id processing much more complex. We will
1478 * wait up to hci1394_phy_delay_uS for the write to complete (this was
1479 * initially set to 10). I have yet to see count > 0. The delay is a
1480 * patchable variable.
1481 */
1482 count = 0;
1483 while (count < hci1394_phy_delay_uS) {
1484 /* See if the write is done yet */
1485 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1486 &ohci_hdl->ohci_regs->phy_ctrl);
1487 if ((ohci_reg & OHCI_PHYC_WRREG) == 0) {
1488 /*
1489 * The write completed. Break out of the loop, we are
1490 * done.
1491 */
1492 break;
1493 }
1494
1495 /*
1496 * the phy write did not yet complete, wait 1uS, increment the
1497 * count and try again.
1498 */
1499 drv_usecwait(1);
1500 count++;
1501 }
1502
1503 /* Check to see if we timed out */
1504 if (count >= hci1394_phy_delay_uS) {
1505 /* we timed out, return failure */
1506 TNF_PROBE_0(hci1394_ohci_phy_wr_timeout_fail,
1507 HCI1394_TNF_HAL_ERROR, "");
1508 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit,
1509 HCI1394_TNF_HAL_STACK, "");
1510 return (DDI_FAILURE);
1511 }
1512
1513 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_write_exit,
1514 HCI1394_TNF_HAL_STACK, "");
1515
1516 return (DDI_SUCCESS);
1517 }
1518
1519
1520 /*
1521 * hci1394_ohci_phy_info()
1522 * Return selfid word for our PHY. This routine should ONLY be called for
1523 * adapters with a 1394-1995 PHY. These PHY's do not embed their own selfid
1524 * information in the selfid buffer so we need to do it for them in the
1525 * selfid complete interrupt handler. This routine only supports building
1526 * selfid info for a 3 port PHY. Since we will probably not ever see a
1527 * 1394-1995 PHY in any production system, and if we do it will have 3 ports
1528 * or less, this is a pretty safe assumption.
1529 */
1530 int
hci1394_ohci_phy_info(hci1394_ohci_handle_t ohci_hdl,uint32_t * info)1531 hci1394_ohci_phy_info(hci1394_ohci_handle_t ohci_hdl, uint32_t *info)
1532 {
1533 int status;
1534 uint32_t phy_info;
1535 uint32_t reg;
1536 int index;
1537 int num_ports;
1538 int count;
1539 uint32_t port_status;
1540
1541
1542 ASSERT(ohci_hdl != NULL);
1543 ASSERT(info != NULL);
1544 ASSERT(ohci_hdl->ohci_phy == H1394_PHY_1995);
1545 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_enter,
1546 HCI1394_TNF_HAL_STACK, "");
1547
1548 /*
1549 * Set Link on. We are using power class 0 since we have no idea what
1550 * our real power class is.
1551 */
1552 phy_info = 0x80400000;
1553
1554 /* Add in Physical ID */
1555 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1556 &ohci_hdl->ohci_regs->node_id);
1557 phy_info = phy_info | ((reg << IEEE1394_SELFID_PHYID_SHIFT) &
1558 IEEE1394_SELFID_PHYID_MASK);
1559
1560 /* Add in Gap Count */
1561 status = hci1394_ohci_phy_read(ohci_hdl, 1, ®);
1562 if (status != DDI_SUCCESS) {
1563 TNF_PROBE_0(hci1394_ohci_phy_read_fail,
1564 HCI1394_TNF_HAL_ERROR, "");
1565 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit,
1566 HCI1394_TNF_HAL_STACK, "");
1567 return (DDI_FAILURE);
1568 }
1569 phy_info = phy_info | ((reg << IEEE1394_SELFID_GAP_CNT_SHIFT) &
1570 IEEE1394_SELFID_GAP_CNT_MASK);
1571
1572 /* Add in speed & ports */
1573 status = hci1394_ohci_phy_read(ohci_hdl, 2, ®);
1574 if (status != DDI_SUCCESS) {
1575 TNF_PROBE_0(hci1394_ohci_phy_read_fail,
1576 HCI1394_TNF_HAL_ERROR, "");
1577 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit,
1578 HCI1394_TNF_HAL_STACK, "");
1579 return (DDI_FAILURE);
1580 }
1581 phy_info = phy_info | ((reg & 0xC0) << 8);
1582 num_ports = reg & 0x1F;
1583
1584 /* PHY reports that it has 0 ports?? */
1585 if (num_ports == 0) {
1586 TNF_PROBE_1(hci1394_ohci_phy_zero_ports_fail,
1587 HCI1394_TNF_HAL_ERROR, "", tnf_string, errmsg,
1588 "1995 phy has zero ports?");
1589 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit,
1590 HCI1394_TNF_HAL_STACK, "");
1591 return (DDI_FAILURE);
1592 }
1593
1594 /* Build up the port information for each port in the PHY */
1595 count = 0;
1596 for (index = 0; index < 3; index++) {
1597 if (num_ports > 0) {
1598 status = hci1394_ohci_phy_read(ohci_hdl,
1599 count + 3, ®);
1600 if (status != DDI_SUCCESS) {
1601 TNF_PROBE_0(hci1394_ohci_phy_read_fail,
1602 HCI1394_TNF_HAL_ERROR, "");
1603 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit,
1604 HCI1394_TNF_HAL_STACK, "");
1605 return (DDI_FAILURE);
1606 }
1607 /* if port is not connected */
1608 if ((reg & 0x04) == 0) {
1609 port_status =
1610 IEEE1394_SELFID_PORT_NOT_CONNECTED;
1611
1612 /* else if port is connected to parent */
1613 } else if ((reg & 0x08) == 0) {
1614 port_status = IEEE1394_SELFID_PORT_TO_PARENT;
1615
1616 /* else port is connected to child */
1617 } else {
1618 port_status = IEEE1394_SELFID_PORT_TO_CHILD;
1619 }
1620
1621 num_ports--;
1622 } else {
1623 port_status = IEEE1394_SELFID_PORT_NO_PORT;
1624 }
1625
1626 /* add in the port information */
1627 phy_info = phy_info | (port_status << (6 - (index * 2)));
1628 count++;
1629 }
1630
1631 /* Copy the PHY selfid info to the return parameter */
1632 *info = phy_info;
1633
1634 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_info_exit,
1635 HCI1394_TNF_HAL_STACK, "");
1636
1637 return (DDI_SUCCESS);
1638 }
1639
1640
1641 /*
1642 * hci1394_ohci_current_busgen()
1643 * return the current bus generation.
1644 */
1645 uint_t
hci1394_ohci_current_busgen(hci1394_ohci_handle_t ohci_hdl)1646 hci1394_ohci_current_busgen(hci1394_ohci_handle_t ohci_hdl)
1647 {
1648 uint32_t reg;
1649 uint_t generation_count;
1650
1651
1652 ASSERT(ohci_hdl != NULL);
1653 TNF_PROBE_0_DEBUG(hci1394_ohci_current_busgen_enter,
1654 HCI1394_TNF_HAL_STACK, "");
1655
1656 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1657 &ohci_hdl->ohci_regs->self_id_count);
1658 generation_count = (reg & OHCI_SLFC_GEN_MASK) >> OHCI_SLFC_GEN_SHIFT;
1659
1660 TNF_PROBE_0_DEBUG(hci1394_ohci_current_busgen_exit,
1661 HCI1394_TNF_HAL_STACK, "");
1662
1663 return (generation_count);
1664 }
1665
1666
1667 /*
1668 * hci1394_ohci_startup()
1669 * Startup the 1394 nexus driver. This is called after all of the HW has
1670 * been initialized (in both attach and resume) and we are ready to
1671 * participate on the bus.
1672 */
1673 int
hci1394_ohci_startup(hci1394_ohci_handle_t ohci_hdl)1674 hci1394_ohci_startup(hci1394_ohci_handle_t ohci_hdl)
1675 {
1676 int status;
1677
1678
1679 ASSERT(ohci_hdl != NULL);
1680 TNF_PROBE_0_DEBUG(hci1394_ohci_startup_enter,
1681 HCI1394_TNF_HAL_STACK, "");
1682
1683 /*
1684 * Turn on 1394 link. This allows us to receive 1394 traffic off the
1685 * bus
1686 */
1687 hci1394_ohci_link_enable(ohci_hdl);
1688
1689 /*
1690 * Reset the 1394 Bus.
1691 * Need to do this so that the link layer can collect all of the self-id
1692 * packets. The Interrupt routine will cause further initialization
1693 * after the bus reset has completed
1694 */
1695 status = hci1394_ohci_bus_reset(ohci_hdl);
1696 if (status != DDI_SUCCESS) {
1697 TNF_PROBE_1_DEBUG(hci1394_ohci_startup_exit,
1698 HCI1394_TNF_HAL_ERROR, "", tnf_string, errmsg,
1699 "failed to reset bus");
1700 TNF_PROBE_0_DEBUG(hci1394_ohci_startup_exit,
1701 HCI1394_TNF_HAL_STACK, "");
1702 return (DDI_FAILURE);
1703 }
1704
1705 /* setup out initial interrupt mask and enable interrupts */
1706 hci1394_isr_mask_setup(ohci_hdl->soft_state);
1707 hci1394_ohci_intr_master_enable(ohci_hdl);
1708
1709 TNF_PROBE_0_DEBUG(hci1394_ohci_startup_exit, HCI1394_TNF_HAL_STACK,
1710 "");
1711
1712 return (DDI_SUCCESS);
1713 }
1714
1715
1716 /*
1717 * hci1394_ohci_postwr_addr()
1718 * Read the Posted Write Address registers. This should be read when a
1719 * posted write error is detected to find out what transaction had an error.
1720 */
1721 void
hci1394_ohci_postwr_addr(hci1394_ohci_handle_t ohci_hdl,uint64_t * addr)1722 hci1394_ohci_postwr_addr(hci1394_ohci_handle_t ohci_hdl, uint64_t *addr)
1723 {
1724 uint32_t reg;
1725
1726
1727 ASSERT(ohci_hdl != NULL);
1728 ASSERT(addr != NULL);
1729 TNF_PROBE_0_DEBUG(hci1394_ohci_postwr_addr_enter,
1730 HCI1394_TNF_HAL_STACK, "");
1731
1732 /* read in the errored address */
1733 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1734 &ohci_hdl->ohci_regs->posted_write_addrhi);
1735 *addr = ((uint64_t)reg) << 32;
1736 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1737 &ohci_hdl->ohci_regs->posted_write_addrlo);
1738 *addr = *addr | (uint64_t)reg;
1739
1740 /*
1741 * Interrupt should be cleared after reading the posted write address.
1742 * See 13.2.8.1 in OpenHCI spec v1.0.
1743 */
1744 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_POST_WR_ERR);
1745
1746 TNF_PROBE_0_DEBUG(hci1394_ohci_postwr_addr_exit,
1747 HCI1394_TNF_HAL_STACK, "");
1748 }
1749
1750
1751 /*
1752 * hci1394_ohci_guid()
1753 * Return the adapter's GUID
1754 */
1755 uint64_t
hci1394_ohci_guid(hci1394_ohci_handle_t ohci_hdl)1756 hci1394_ohci_guid(hci1394_ohci_handle_t ohci_hdl)
1757 {
1758 uint32_t reg;
1759 uint64_t guid;
1760
1761
1762 ASSERT(ohci_hdl != NULL);
1763 TNF_PROBE_0_DEBUG(hci1394_ohci_guid_enter, HCI1394_TNF_HAL_STACK, "");
1764
1765 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1766 &ohci_hdl->ohci_regs->guid_hi);
1767 guid = ((uint64_t)reg) << 32;
1768 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1769 &ohci_hdl->ohci_regs->guid_lo);
1770 guid = guid | (uint64_t)reg;
1771
1772 TNF_PROBE_0_DEBUG(hci1394_ohci_guid_exit, HCI1394_TNF_HAL_STACK, "");
1773
1774 return (guid);
1775 }
1776
1777
1778 /*
1779 * hci1394_ohci_csr_read()
1780 * Read one of the HW implemented CSR registers. These include
1781 * bus_manager_id, bandwidth_available, channels_available_hi, and
1782 * channels_available_lo. Offset should be set to
1783 * OHCI_CSR_SEL_BUS_MGR_ID, OHCI_CSR_SEL_BANDWIDTH_AVAIL
1784 * OHCI_CSR_SEL_CHANS_AVAIL_HI, or OHCI_CSR_SEL_CHANS_AVAIL_LO.
1785 */
1786 int
hci1394_ohci_csr_read(hci1394_ohci_handle_t ohci_hdl,uint_t offset,uint32_t * data)1787 hci1394_ohci_csr_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset,
1788 uint32_t *data)
1789 {
1790 uint_t generation;
1791 int status;
1792
1793
1794 ASSERT(ohci_hdl != NULL);
1795 ASSERT(data != NULL);
1796 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_read_enter, HCI1394_TNF_HAL_STACK,
1797 "");
1798
1799 /*
1800 * read the CSR register by doing a cswap with the same compare and
1801 * swap value.
1802 */
1803 generation = hci1394_ohci_current_busgen(ohci_hdl);
1804 status = hci1394_ohci_csr_cswap(ohci_hdl, generation, offset, 0, 0,
1805 data);
1806 if (status != DDI_SUCCESS) {
1807 TNF_PROBE_0(hci1394_ohci_csr_read_csw_fail,
1808 HCI1394_TNF_HAL_ERROR, "");
1809 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_read_exit,
1810 HCI1394_TNF_HAL_STACK, "");
1811 return (DDI_FAILURE);
1812 }
1813
1814 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_read_exit, HCI1394_TNF_HAL_STACK,
1815 "");
1816
1817 return (DDI_SUCCESS);
1818 }
1819
1820
1821 /*
1822 * hci1394_ohci_csr_cswap()
1823 * Perform a compare/swap on one of the HW implemented CSR registers. These
1824 * include bus_manager_id, bandwidth_available, channels_available_hi, and
1825 * channels_available_lo. Offset should be set to
1826 * OHCI_CSR_SEL_BUS_MGR_ID, OHCI_CSR_SEL_BANDWIDTH_AVAIL
1827 * OHCI_CSR_SEL_CHANS_AVAIL_HI, or OHCI_CSR_SEL_CHANS_AVAIL_LO.
1828 */
1829 int
hci1394_ohci_csr_cswap(hci1394_ohci_handle_t ohci_hdl,uint_t generation,uint_t offset,uint32_t compare,uint32_t swap,uint32_t * old)1830 hci1394_ohci_csr_cswap(hci1394_ohci_handle_t ohci_hdl, uint_t generation,
1831 uint_t offset, uint32_t compare, uint32_t swap, uint32_t *old)
1832 {
1833 int count;
1834 uint32_t ohci_reg;
1835
1836
1837 ASSERT(ohci_hdl != NULL);
1838 ASSERT(old != NULL);
1839 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_enter,
1840 HCI1394_TNF_HAL_STACK, "");
1841
1842 /*
1843 * Make sure we have not gotten a bus reset since this action was
1844 * started.
1845 */
1846 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) {
1847 TNF_PROBE_1(hci1394_ohci_invbusgen_fail, HCI1394_TNF_HAL_ERROR,
1848 "", tnf_string, errmsg, "Invalid Bus Generation");
1849 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_exit,
1850 HCI1394_TNF_HAL_STACK, "");
1851 return (DDI_FAILURE);
1852 }
1853
1854 mutex_enter(&ohci_hdl->ohci_mutex);
1855
1856 /* init csrData and csrCompare */
1857 ddi_put32(ohci_hdl->ohci_reg_handle,
1858 &ohci_hdl->ohci_regs->csr_data, swap);
1859 ddi_put32(ohci_hdl->ohci_reg_handle,
1860 &ohci_hdl->ohci_regs->csr_compare_data, compare);
1861
1862 /* start the compare swap */
1863 ddi_put32(ohci_hdl->ohci_reg_handle,
1864 &ohci_hdl->ohci_regs->csr_ctrl, offset & OHCI_CSR_SELECT);
1865
1866 /*
1867 * The CSR access should be immediate. There in nothing that officially
1868 * states this so we will wait up to 2uS just in case before we timeout.
1869 * We actually perform a compare swap with both compare and swap set
1870 * to the same value. This will return the old value which is in
1871 * essence, a read.
1872 */
1873 count = 0;
1874 while (count < 2) {
1875 /* See if the compare swap is done */
1876 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1877 &ohci_hdl->ohci_regs->csr_ctrl);
1878 if ((ohci_reg & OHCI_CSR_DONE) != 0) {
1879 /* The compare swap is done, break out of the loop */
1880 break;
1881 }
1882 /*
1883 * The compare swap has not completed yet, wait 1uS, increment
1884 * the count and try again
1885 */
1886 drv_usecwait(1);
1887 count++;
1888 }
1889
1890 /* If we timed out, return an error */
1891 if (count >= 2) {
1892 *old = 0;
1893 mutex_exit(&ohci_hdl->ohci_mutex);
1894 TNF_PROBE_0(hci1394_ohci_phy_csr_timeout_fail,
1895 HCI1394_TNF_HAL_ERROR, "");
1896 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_exit,
1897 HCI1394_TNF_HAL_STACK, "");
1898 return (DDI_FAILURE);
1899 }
1900
1901 /* Copy the old data into the return parameter */
1902 *old = ddi_get32(ohci_hdl->ohci_reg_handle,
1903 &ohci_hdl->ohci_regs->csr_data);
1904
1905 mutex_exit(&ohci_hdl->ohci_mutex);
1906
1907 /*
1908 * There is a race condition in the OpenHCI design here. After checking
1909 * the generation and before performing the cswap, we could get a bus
1910 * reset and incorrectly set something like the bus manager. This would
1911 * put us into a condition where we would not have a bus manager and
1912 * we would think there was one. If it is possible that this race
1913 * condition occured, we will reset the bus to clean things up. We only
1914 * care about this if the compare swap was successful.
1915 */
1916 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) {
1917 if (*old == compare) {
1918 (void) hci1394_ohci_bus_reset(ohci_hdl);
1919 TNF_PROBE_1(hci1394_ohci_invbusgen_fail,
1920 HCI1394_TNF_HAL_ERROR, "", tnf_string, errmsg,
1921 "Invalid Bus Generation");
1922 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_exit,
1923 HCI1394_TNF_HAL_STACK, "");
1924 return (DDI_FAILURE);
1925 }
1926 }
1927
1928 TNF_PROBE_0_DEBUG(hci1394_ohci_csr_cswap_exit, HCI1394_TNF_HAL_STACK,
1929 "");
1930
1931 return (DDI_SUCCESS);
1932 }
1933
1934
1935 /*
1936 * hci1394_ohci_contender_enable()
1937 * Set the contender bit in the PHY. This routine should only be called
1938 * if our PHY is 1394A compliant. (i.e. this routine should not be called
1939 * for a 1394-1995 PHY).
1940 */
1941 int
hci1394_ohci_contender_enable(hci1394_ohci_handle_t ohci_hdl)1942 hci1394_ohci_contender_enable(hci1394_ohci_handle_t ohci_hdl)
1943 {
1944 int status;
1945
1946
1947 ASSERT(ohci_hdl != NULL);
1948 TNF_PROBE_0_DEBUG(hci1394_ohci_contender_enable_enter,
1949 HCI1394_TNF_HAL_STACK, "");
1950
1951 /*
1952 * Make sure that phy is not a 1394-1995 phy. Those phy's do not have a
1953 * contender bit to set.
1954 */
1955 if (ohci_hdl->ohci_phy == H1394_PHY_1995) {
1956 TNF_PROBE_0(hci1394_ohci_phy_type_fail,
1957 HCI1394_TNF_HAL_ERROR, "");
1958 TNF_PROBE_0_DEBUG(hci1394_ohci_contender_enable_exit,
1959 HCI1394_TNF_HAL_STACK, "");
1960 return (DDI_FAILURE);
1961 }
1962
1963 /* Set the Contender Bit */
1964 status = hci1394_ohci_phy_set(ohci_hdl, 0x4, OHCI_PHY_CNTDR);
1965 if (status != DDI_SUCCESS) {
1966 TNF_PROBE_0(hci1394_ohci_phy_set_fail,
1967 HCI1394_TNF_HAL_ERROR, "");
1968 TNF_PROBE_0_DEBUG(hci1394_ohci_contender_enable_exit,
1969 HCI1394_TNF_HAL_STACK, "");
1970 return (DDI_FAILURE);
1971 }
1972
1973 TNF_PROBE_0_DEBUG(hci1394_ohci_contender_enable_exit,
1974 HCI1394_TNF_HAL_STACK, "");
1975
1976 return (DDI_SUCCESS);
1977 }
1978
1979
1980 /*
1981 * hci1394_ohci_root_holdoff_enable()
1982 * Set the root holdoff bit in the PHY. Since there are race conditions when
1983 * writing to PHY register 1 (which can get updated from a PHY packet off the
1984 * bus), we cache this state until a "long" bus reset is issued.
1985 */
1986 int
hci1394_ohci_root_holdoff_enable(hci1394_ohci_handle_t ohci_hdl)1987 hci1394_ohci_root_holdoff_enable(hci1394_ohci_handle_t ohci_hdl)
1988 {
1989 ASSERT(ohci_hdl != NULL);
1990 TNF_PROBE_0_DEBUG(hci1394_ohci_root_holdoff_enable_enter,
1991 HCI1394_TNF_HAL_STACK, "");
1992
1993 ohci_hdl->ohci_set_root_holdoff = B_TRUE;
1994
1995 TNF_PROBE_0_DEBUG(hci1394_ohci_root_holdoff_enable_exit,
1996 HCI1394_TNF_HAL_STACK, "");
1997
1998 return (DDI_SUCCESS);
1999 }
2000
2001
2002 /*
2003 * hci1394_ohci_gap_count_set()
2004 * Set the gap count in the PHY. Since there are race conditions when writing
2005 * to PHY register 1 (which can get updated from a PHY packet off the bus),
2006 * we cache this gap count until a "long" bus reset is issued.
2007 */
2008 int
hci1394_ohci_gap_count_set(hci1394_ohci_handle_t ohci_hdl,uint_t gap_count)2009 hci1394_ohci_gap_count_set(hci1394_ohci_handle_t ohci_hdl, uint_t gap_count)
2010 {
2011 ASSERT(ohci_hdl != NULL);
2012 TNF_PROBE_0_DEBUG(hci1394_ohci_gap_count_set_enter,
2013 HCI1394_TNF_HAL_STACK, "");
2014
2015 ohci_hdl->ohci_set_gap_count = B_TRUE;
2016 ohci_hdl->ohci_gap_count = gap_count & OHCI_PHY_MAX_GAP;
2017
2018 TNF_PROBE_0_DEBUG(hci1394_ohci_gap_count_set_exit,
2019 HCI1394_TNF_HAL_STACK, "");
2020
2021 return (DDI_SUCCESS);
2022 }
2023
2024
2025 /*
2026 * hci1394_ohci_phy_filter_set()
2027 * Enable a node (or nodes) to perform transactions to our physical
2028 * memory. OpenHCI allows you to disable/enable physical requests on a node
2029 * per node basis. A physical request is basically a read/write to 1394
2030 * address space 0x0 - 0xFFFFFFFF. This address goes out to the IO MMU (in
2031 * the case of a SPARC machine). The HAL starts with all nodes unable to
2032 * read/write physical memory. The Services Layer will call down and enable
2033 * nodes via setting a physical filter bit for that given node. Since node
2034 * numbers change every bus reset, the services layer has to call down after
2035 * every bus reset to re-enable physical accesses. (NOTE: the hardware
2036 * automatically clears these bits.
2037 */
2038 int
hci1394_ohci_phy_filter_set(hci1394_ohci_handle_t ohci_hdl,uint64_t mask,uint_t generation)2039 hci1394_ohci_phy_filter_set(hci1394_ohci_handle_t ohci_hdl, uint64_t mask,
2040 uint_t generation)
2041 {
2042 uint32_t data;
2043
2044
2045 ASSERT(ohci_hdl != NULL);
2046 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_set_enter,
2047 HCI1394_TNF_HAL_STACK, "");
2048
2049 /*
2050 * Make sure we have not gotten a bus reset since this action was
2051 * started.
2052 */
2053 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) {
2054 TNF_PROBE_1(hci1394_ohci_invbusgen_fail, HCI1394_TNF_HAL_ERROR,
2055 "", tnf_string, errmsg, "Invalid Bus Generation");
2056 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_set_exit,
2057 HCI1394_TNF_HAL_STACK, "");
2058 return (DDI_FAILURE);
2059 }
2060
2061 data = (uint32_t)((mask >> 32) & 0xFFFFFFFF);
2062 ddi_put32(ohci_hdl->ohci_reg_handle,
2063 &ohci_hdl->ohci_regs->phys_req_filterhi_set, data);
2064 data = (uint32_t)(mask & 0xFFFFFFFF);
2065 ddi_put32(ohci_hdl->ohci_reg_handle,
2066 &ohci_hdl->ohci_regs->phys_req_filterlo_set, data);
2067
2068 /*
2069 * There is a race condition in the OpenHCI design here. After checking
2070 * the generation and before setting the physical filter bits, we could
2071 * get a bus reset and incorrectly set the physical filter bits. If it
2072 * is possible that this race condition occured, we will reset the bus
2073 * to clean things up.
2074 */
2075 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) {
2076 (void) hci1394_ohci_bus_reset(ohci_hdl);
2077 TNF_PROBE_1(hci1394_ohci_filterrace_fail, HCI1394_TNF_HAL_ERROR,
2078 "", tnf_string, errmsg, "Invalid Bus Generation");
2079 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_set_exit,
2080 HCI1394_TNF_HAL_STACK, "");
2081 return (DDI_SUCCESS);
2082 }
2083
2084 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_set_exit,
2085 HCI1394_TNF_HAL_STACK, "");
2086
2087 return (DDI_SUCCESS);
2088 }
2089
2090
2091 /*
2092 * hci1394_ohci_phy_filter_clr()
2093 * Disable a node (or nodes) from performing transactions to our physical
2094 * memory. See hci1394_ohci_phy_filter_set() above for more info.
2095 */
2096 int
hci1394_ohci_phy_filter_clr(hci1394_ohci_handle_t ohci_hdl,uint64_t mask,uint_t generation)2097 hci1394_ohci_phy_filter_clr(hci1394_ohci_handle_t ohci_hdl,
2098 uint64_t mask, uint_t generation)
2099 {
2100 uint32_t data;
2101
2102
2103 ASSERT(ohci_hdl != NULL);
2104 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_clr_enter,
2105 HCI1394_TNF_HAL_STACK, "");
2106
2107 /*
2108 * Make sure we have not gotten a bus reset since this action was
2109 * started.
2110 */
2111 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) {
2112 TNF_PROBE_1(hci1394_ohci_invbusgen_fail, HCI1394_TNF_HAL_ERROR,
2113 "", tnf_string, errmsg, "Invalid Bus Generation");
2114 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_clr_exit,
2115 HCI1394_TNF_HAL_STACK, "");
2116 return (DDI_FAILURE);
2117 }
2118
2119 data = (uint32_t)((mask >> 32) & 0xFFFFFFFF);
2120 ddi_put32(ohci_hdl->ohci_reg_handle,
2121 &ohci_hdl->ohci_regs->phys_req_filterhi_clr, data);
2122 data = (uint32_t)(mask & 0xFFFFFFFF);
2123 ddi_put32(ohci_hdl->ohci_reg_handle,
2124 &ohci_hdl->ohci_regs->phys_req_filterlo_clr, data);
2125
2126 TNF_PROBE_0_DEBUG(hci1394_ohci_phy_filter_clr_exit,
2127 HCI1394_TNF_HAL_STACK, "");
2128
2129 return (DDI_SUCCESS);
2130 }
2131
2132
2133 /*
2134 * hci1394_ohci_bus_reset_short()
2135 * Perform a 1394A short bus reset. This function should only be called
2136 * on an adapter with a 1394A PHY (or later).
2137 */
2138 int
hci1394_ohci_bus_reset_short(hci1394_ohci_handle_t ohci_hdl)2139 hci1394_ohci_bus_reset_short(hci1394_ohci_handle_t ohci_hdl)
2140 {
2141 int status;
2142
2143 ASSERT(ohci_hdl != NULL);
2144 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_short_enter,
2145 HCI1394_TNF_HAL_STACK, "");
2146
2147 /*
2148 * Make sure that phy is not a 1394-1995 phy. Those phy's do not have a
2149 * contender bit to set.
2150 */
2151 if (ohci_hdl->ohci_phy == H1394_PHY_1995) {
2152 TNF_PROBE_0(hci1394_ohci_brs_phy_fail,
2153 HCI1394_TNF_HAL_ERROR, "");
2154 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_short_exit,
2155 HCI1394_TNF_HAL_STACK, "");
2156 return (DDI_FAILURE);
2157 }
2158
2159 /* Initiate the short bus reset */
2160 status = hci1394_ohci_phy_set(ohci_hdl, 0x5, OHCI_PHY_ISBR);
2161 if (status != DDI_SUCCESS) {
2162 TNF_PROBE_0(hci1394_ohci_phy_set_fail,
2163 HCI1394_TNF_HAL_ERROR, "");
2164 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_short_exit,
2165 HCI1394_TNF_HAL_STACK, "");
2166 return (DDI_FAILURE);
2167 }
2168
2169 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_reset_short_exit,
2170 HCI1394_TNF_HAL_STACK, "");
2171
2172 return (status);
2173 }
2174
2175
2176 /*
2177 * hci1394_ohci_cfgrom_update()
2178 * Update the config rom with the provided contents. The config rom is
2179 * provided as a byte stream which is multiple of 4 bytes large. The
2180 * size is passed as a quadlet (4 bytes) count. The entire contents
2181 * of the config rom is updated at once. We do not provide a partial
2182 * update interface.
2183 */
2184 void
hci1394_ohci_cfgrom_update(hci1394_ohci_handle_t ohci_hdl,void * local_buf,uint_t quadlet_count)2185 hci1394_ohci_cfgrom_update(hci1394_ohci_handle_t ohci_hdl, void *local_buf,
2186 uint_t quadlet_count)
2187 {
2188 uint32_t *data;
2189
2190
2191 ASSERT(ohci_hdl != NULL);
2192 ASSERT(local_buf != NULL);
2193 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_update_enter,
2194 HCI1394_TNF_HAL_STACK, "");
2195
2196 data = (uint32_t *)local_buf;
2197
2198 /* zero out the config ROM header to start */
2199 ddi_put32(ohci_hdl->ohci_reg_handle,
2200 &ohci_hdl->ohci_regs->config_rom_hdr, 0);
2201
2202 /* copy Services Layer buffer into config rom buffer */
2203 ddi_rep_put8(ohci_hdl->ohci_cfgrom.bi_handle, local_buf,
2204 (uint8_t *)ohci_hdl->ohci_cfgrom.bi_kaddr, quadlet_count << 2,
2205 DDI_DEV_AUTOINCR);
2206
2207 (void) ddi_dma_sync(ohci_hdl->ohci_cfgrom.bi_dma_handle, 0,
2208 quadlet_count << 2, DDI_DMA_SYNC_FORDEV);
2209
2210 /*
2211 * setup OHCI bus options and config rom hdr registers. We need to swap
2212 * the config rom header and bus options on an X86 machine since the
2213 * data is provided to us as a byte stream and the OHCI registers expect
2214 * a big endian 32-bit number.
2215 */
2216 ddi_put32(ohci_hdl->ohci_reg_handle,
2217 &ohci_hdl->ohci_regs->bus_options, OHCI_SWAP32(data[2]));
2218 ddi_put32(ohci_hdl->ohci_reg_handle,
2219 &ohci_hdl->ohci_regs->config_rom_hdr, OHCI_SWAP32(data[0]));
2220
2221 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_update_exit,
2222 HCI1394_TNF_HAL_STACK, "");
2223 }
2224
2225
2226 /*
2227 * hci1394_ohci_nodeid_get()
2228 * Return our current nodeid (bus #/Node #)
2229 */
2230 void
hci1394_ohci_nodeid_get(hci1394_ohci_handle_t ohci_hdl,uint_t * nodeid)2231 hci1394_ohci_nodeid_get(hci1394_ohci_handle_t ohci_hdl, uint_t *nodeid)
2232 {
2233 uint32_t reg;
2234
2235 ASSERT(ohci_hdl != NULL);
2236 ASSERT(nodeid != NULL);
2237 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_get_enter, HCI1394_TNF_HAL_STACK,
2238 "");
2239 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2240 &ohci_hdl->ohci_regs->node_id);
2241 *nodeid = (reg & 0xFFFF) << 16;
2242 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_get_exit, HCI1394_TNF_HAL_STACK,
2243 "");
2244 }
2245
2246
2247 /*
2248 * hci1394_ohci_nodeid_set()
2249 * Set our current nodeid (bus #/Node #). This actually sets our bus number.
2250 * Our node number cannot be set by software. This is usually trigered via
2251 * a write to the CSR NODEIDS register.
2252 */
2253 void
hci1394_ohci_nodeid_set(hci1394_ohci_handle_t ohci_hdl,uint_t nodeid)2254 hci1394_ohci_nodeid_set(hci1394_ohci_handle_t ohci_hdl, uint_t nodeid)
2255 {
2256 uint32_t reg;
2257
2258 ASSERT(ohci_hdl != NULL);
2259 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_set_enter,
2260 HCI1394_TNF_HAL_STACK, "");
2261
2262 reg = ((nodeid & 0xFFC00000) >> 16);
2263 ddi_put32(ohci_hdl->ohci_reg_handle,
2264 &ohci_hdl->ohci_regs->node_id, reg);
2265
2266 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_set_exit,
2267 HCI1394_TNF_HAL_STACK, "");
2268 }
2269
2270
2271 /*
2272 * hci1394_ohci_nodeid_info()
2273 * Return our current nodeid (bus #/Node #). This also returns whether or
2274 * not our nodeid error bit is set. This is useful in determining if the
2275 * bus reset completed without errors in the selfid complete interrupt
2276 * processing.
2277 */
2278 void
hci1394_ohci_nodeid_info(hci1394_ohci_handle_t ohci_hdl,uint_t * nodeid,boolean_t * error)2279 hci1394_ohci_nodeid_info(hci1394_ohci_handle_t ohci_hdl, uint_t *nodeid,
2280 boolean_t *error)
2281 {
2282 uint32_t reg;
2283
2284 ASSERT(ohci_hdl != NULL);
2285 ASSERT(nodeid != NULL);
2286 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_info_enter,
2287 HCI1394_TNF_HAL_STACK, "");
2288
2289 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2290 &ohci_hdl->ohci_regs->node_id);
2291 *nodeid = reg & 0xFFFF;
2292 if ((reg & OHCI_NDID_IDVALID) == 0) {
2293 *error = B_TRUE;
2294 } else {
2295 *error = B_FALSE;
2296 }
2297
2298 TNF_PROBE_0_DEBUG(hci1394_ohci_nodeid_info_exit,
2299 HCI1394_TNF_HAL_STACK, "");
2300 }
2301
2302
2303 /*
2304 * hci1394_ohci_cycletime_get()
2305 * Return the current cycle time
2306 */
2307 void
hci1394_ohci_cycletime_get(hci1394_ohci_handle_t ohci_hdl,uint32_t * cycle_time)2308 hci1394_ohci_cycletime_get(hci1394_ohci_handle_t ohci_hdl,
2309 uint32_t *cycle_time)
2310 {
2311 ASSERT(ohci_hdl != NULL);
2312 ASSERT(cycle_time != NULL);
2313 TNF_PROBE_0_DEBUG(hci1394_ohci_cycletime_get_enter,
2314 HCI1394_TNF_HAL_STACK, "");
2315 *cycle_time = ddi_get32(ohci_hdl->ohci_reg_handle,
2316 &ohci_hdl->ohci_regs->isoch_cycle_timer);
2317 TNF_PROBE_0_DEBUG(hci1394_ohci_cycletime_get_exit,
2318 HCI1394_TNF_HAL_STACK, "");
2319 }
2320
2321
2322 /*
2323 * hci1394_ohci_cycletime_get()
2324 * Set the cycle time
2325 */
2326 void
hci1394_ohci_cycletime_set(hci1394_ohci_handle_t ohci_hdl,uint32_t cycle_time)2327 hci1394_ohci_cycletime_set(hci1394_ohci_handle_t ohci_hdl,
2328 uint32_t cycle_time)
2329 {
2330 ASSERT(ohci_hdl != NULL);
2331 TNF_PROBE_0_DEBUG(hci1394_ohci_cycletime_set_enter,
2332 HCI1394_TNF_HAL_STACK, "");
2333 ddi_put32(ohci_hdl->ohci_reg_handle,
2334 &ohci_hdl->ohci_regs->isoch_cycle_timer, cycle_time);
2335 TNF_PROBE_0_DEBUG(hci1394_ohci_cycletime_set_exit,
2336 HCI1394_TNF_HAL_STACK, "");
2337 }
2338
2339
2340 /*
2341 * hci1394_ohci_bustime_get()
2342 * Return the current bus time.
2343 */
2344 void
hci1394_ohci_bustime_get(hci1394_ohci_handle_t ohci_hdl,uint32_t * bus_time)2345 hci1394_ohci_bustime_get(hci1394_ohci_handle_t ohci_hdl, uint32_t *bus_time)
2346 {
2347 uint32_t bus_time1;
2348 uint32_t bus_time2;
2349 uint32_t cycle_time;
2350
2351
2352 ASSERT(ohci_hdl != NULL);
2353 ASSERT(bus_time != NULL);
2354 TNF_PROBE_0_DEBUG(hci1394_ohci_bustime_get_enter,
2355 HCI1394_TNF_HAL_STACK, "");
2356
2357 /*
2358 * The bus time is composed of a portion of the cycle time and the
2359 * cycle time rollover count (ohci_bustime_count). There is a race
2360 * condition where we read the rollover count and then the cycle
2361 * timer rolls over. This is the reason for the double read of the
2362 * rollover count.
2363 */
2364 do {
2365 bus_time1 = ohci_hdl->ohci_bustime_count;
2366 cycle_time = ddi_get32(ohci_hdl->ohci_reg_handle,
2367 &ohci_hdl->ohci_regs->isoch_cycle_timer);
2368 bus_time2 = ohci_hdl->ohci_bustime_count;
2369 } while (bus_time1 != bus_time2);
2370
2371 *bus_time = (bus_time2 << 7) | (cycle_time >> 25);
2372
2373 TNF_PROBE_0_DEBUG(hci1394_ohci_bustime_get_exit,
2374 HCI1394_TNF_HAL_STACK, "");
2375 }
2376
2377
2378 /*
2379 * hci1394_ohci_bustime_set()
2380 * Set the cycle timer rollover portion of the bus time.
2381 */
2382 void
hci1394_ohci_bustime_set(hci1394_ohci_handle_t ohci_hdl,uint32_t bus_time)2383 hci1394_ohci_bustime_set(hci1394_ohci_handle_t ohci_hdl, uint32_t bus_time)
2384 {
2385 ASSERT(ohci_hdl != NULL);
2386 TNF_PROBE_0_DEBUG(hci1394_ohci_bustime_set_enter,
2387 HCI1394_TNF_HAL_STACK, "");
2388
2389 /*
2390 * we will start with the cycle 64 seconds interrupt disabled. If this
2391 * is the first write to bus time, enable the interrupt.
2392 */
2393 if (ohci_hdl->ohci_bustime_enabled == B_FALSE) {
2394 ohci_hdl->ohci_bustime_enabled = B_TRUE;
2395 /* Clear the cycle64Seconds interrupt then enable it */
2396 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_CYC_64_SECS);
2397 hci1394_ohci_intr_enable(ohci_hdl, OHCI_INTR_CYC_64_SECS);
2398 }
2399 ohci_hdl->ohci_bustime_count = (bus_time >> 7);
2400
2401 TNF_PROBE_0_DEBUG(hci1394_ohci_bustime_set_exit,
2402 HCI1394_TNF_HAL_STACK, "");
2403 }
2404
2405
2406 /*
2407 * hci1394_ohci_atreq_retries_get()
2408 * Get the number of atreq retries we will perform.
2409 */
2410 void
hci1394_ohci_atreq_retries_get(hci1394_ohci_handle_t ohci_hdl,uint_t * atreq_retries)2411 hci1394_ohci_atreq_retries_get(hci1394_ohci_handle_t ohci_hdl,
2412 uint_t *atreq_retries)
2413 {
2414 uint32_t reg;
2415
2416 ASSERT(ohci_hdl != NULL);
2417 ASSERT(atreq_retries != NULL);
2418 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_retries_get_enter,
2419 HCI1394_TNF_HAL_STACK, "");
2420 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2421 &ohci_hdl->ohci_regs->at_retries);
2422 *atreq_retries = reg & OHCI_RET_MAX_ATREQ_MASK;
2423 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_retries_get_exit,
2424 HCI1394_TNF_HAL_STACK, "");
2425 }
2426
2427
2428 /*
2429 * hci1394_ohci_atreq_retries_get()
2430 * Set the number of atreq retries we will perform.
2431 */
2432 void
hci1394_ohci_atreq_retries_set(hci1394_ohci_handle_t ohci_hdl,uint_t atreq_retries)2433 hci1394_ohci_atreq_retries_set(hci1394_ohci_handle_t ohci_hdl,
2434 uint_t atreq_retries)
2435 {
2436 uint32_t reg;
2437
2438
2439 ASSERT(ohci_hdl != NULL);
2440 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_retries_set_enter,
2441 HCI1394_TNF_HAL_STACK, "");
2442
2443 mutex_enter(&ohci_hdl->ohci_mutex);
2444 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2445 &ohci_hdl->ohci_regs->at_retries);
2446 reg = reg & ~OHCI_RET_MAX_ATREQ_MASK;
2447 reg = reg | (atreq_retries & OHCI_RET_MAX_ATREQ_MASK);
2448 ddi_put32(ohci_hdl->ohci_reg_handle,
2449 &ohci_hdl->ohci_regs->at_retries, reg);
2450 mutex_exit(&ohci_hdl->ohci_mutex);
2451
2452 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_retries_set_exit,
2453 HCI1394_TNF_HAL_STACK, "");
2454 }
2455
2456
2457 /*
2458 * hci1394_ohci_isr_cycle64seconds()
2459 * Interrupt handler for the cycle64seconds interrupt.
2460 */
2461 void
hci1394_ohci_isr_cycle64seconds(hci1394_ohci_handle_t ohci_hdl)2462 hci1394_ohci_isr_cycle64seconds(hci1394_ohci_handle_t ohci_hdl)
2463 {
2464 uint32_t cycle_time;
2465
2466 ASSERT(ohci_hdl != NULL);
2467 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_cycle64seconds_enter,
2468 HCI1394_TNF_HAL_STACK, "");
2469
2470 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_CYC_64_SECS);
2471 cycle_time = ddi_get32(ohci_hdl->ohci_reg_handle,
2472 &ohci_hdl->ohci_regs->isoch_cycle_timer);
2473
2474 /*
2475 * cycle64second interrupts when the MSBit in the cycle timer changes
2476 * state. We only care about rollover so we will increment only when
2477 * the MSBit is set to 0.
2478 */
2479 if ((cycle_time & 0x80000000) == 0) {
2480 ohci_hdl->ohci_bustime_count++;
2481 }
2482
2483 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_cycle64seconds_exit,
2484 HCI1394_TNF_HAL_STACK, "");
2485 }
2486
2487
2488 /*
2489 * hci1394_ohci_isr_phy()
2490 * Interrupt handler for a PHY event
2491 */
2492 void
hci1394_ohci_isr_phy(hci1394_ohci_handle_t ohci_hdl)2493 hci1394_ohci_isr_phy(hci1394_ohci_handle_t ohci_hdl)
2494 {
2495 uint_t phy_status;
2496 int status;
2497
2498
2499 ASSERT(ohci_hdl != NULL);
2500 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_enter,
2501 HCI1394_TNF_HAL_STACK, "");
2502
2503 /* clear the interrupt */
2504 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_PHY);
2505
2506 /* increment the statistics count */
2507 ohci_hdl->ohci_drvinfo->di_stats.st_phy_isr++;
2508
2509 /*
2510 * If the PHY is a 1995 phy, just return since there are no status bits
2511 * to read.
2512 */
2513 if (ohci_hdl->ohci_phy == H1394_PHY_1995) {
2514 TNF_PROBE_0(hci1394_ohci_phy_isr_1995,
2515 HCI1394_TNF_HAL_ERROR, "");
2516 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_exit,
2517 HCI1394_TNF_HAL_STACK, "");
2518 return;
2519 }
2520
2521 /* See why we got this interrupt */
2522 status = hci1394_ohci_phy_read(ohci_hdl, 5, &phy_status);
2523 if (status != DDI_SUCCESS) {
2524 TNF_PROBE_0(hci1394_ohci_phy_read_failed,
2525 HCI1394_TNF_HAL_ERROR, "");
2526 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_exit,
2527 HCI1394_TNF_HAL_STACK, "");
2528 return;
2529 }
2530
2531 if (phy_status & OHCI_PHY_LOOP_ERR) {
2532 ohci_hdl->ohci_drvinfo->di_stats.st_phy_loop_err++;
2533 cmn_err(CE_NOTE, "hci1394(%d): ERROR - bus loop detected",
2534 ohci_hdl->ohci_drvinfo->di_instance);
2535 TNF_PROBE_0(hci1394_ohci_phy_isr_loop, HCI1394_TNF_HAL, "");
2536 }
2537 if (phy_status & OHCI_PHY_PWRFAIL_ERR) {
2538 ohci_hdl->ohci_drvinfo->di_stats.st_phy_pwrfail_err++;
2539 TNF_PROBE_0(hci1394_ohci_phy_isr_pwr, HCI1394_TNF_HAL, "");
2540 }
2541 if (phy_status & OHCI_PHY_TIMEOUT_ERR) {
2542 ohci_hdl->ohci_drvinfo->di_stats.st_phy_timeout_err++;
2543 TNF_PROBE_0(hci1394_ohci_phy_isr_tmout, HCI1394_TNF_HAL, "");
2544 }
2545 if (phy_status & OHCI_PHY_PORTEVT_ERR) {
2546 ohci_hdl->ohci_drvinfo->di_stats.st_phy_portevt_err++;
2547 TNF_PROBE_0(hci1394_ohci_phy_isr_pevt, HCI1394_TNF_HAL, "");
2548 }
2549
2550 /* clear any set status bits */
2551 status = hci1394_ohci_phy_write(ohci_hdl, 5, phy_status);
2552 if (status != DDI_SUCCESS) {
2553 TNF_PROBE_0(hci1394_ohci_phy_write_failed,
2554 HCI1394_TNF_HAL_ERROR, "");
2555 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_exit,
2556 HCI1394_TNF_HAL_STACK, "");
2557 return;
2558 }
2559
2560 /*
2561 * Disable the PHY interrupt. We are getting stuck in this ISR in
2562 * certain PHY implementations so we will disable the interrupt until
2563 * we see a selfid complete.
2564 */
2565 hci1394_ohci_intr_disable(ohci_hdl, OHCI_INTR_PHY);
2566
2567 TNF_PROBE_0_DEBUG(hci1394_ohci_isr_phy_exit,
2568 HCI1394_TNF_HAL_STACK, "");
2569 }
2570
2571
2572 /*
2573 * hci1394_ohci_root_check
2574 * Returns status about if we are currently the root node on the 1394 bus.
2575 * returns B_TRUE if we are the root, B_FALSE if we are not the root.
2576 */
2577 boolean_t
hci1394_ohci_root_check(hci1394_ohci_handle_t ohci_hdl)2578 hci1394_ohci_root_check(hci1394_ohci_handle_t ohci_hdl)
2579 {
2580 uint32_t reg;
2581 int status;
2582
2583 ASSERT(ohci_hdl != NULL);
2584 TNF_PROBE_0_DEBUG(hci1394_ohci_root_check_enter, HCI1394_TNF_HAL_STACK,
2585 "");
2586 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2587 &ohci_hdl->ohci_regs->node_id);
2588 if ((reg & OHCI_REG_NODEID_ROOT) && (reg & OHCI_NDID_IDVALID)) {
2589 status = B_TRUE;
2590 } else {
2591 status = B_FALSE;
2592 }
2593 TNF_PROBE_0_DEBUG(hci1394_ohci_root_check_exit, HCI1394_TNF_HAL_STACK,
2594 "");
2595
2596 return (status);
2597 }
2598
2599
2600 /*
2601 * hci1394_ohci_cmc_check()
2602 * Returns status about if we are cycle master capable. Returns
2603 * B_TRUE if we are the cycle master capable, B_FALSE if we are not the cycle
2604 * master capable.
2605 */
2606 boolean_t
hci1394_ohci_cmc_check(hci1394_ohci_handle_t ohci_hdl)2607 hci1394_ohci_cmc_check(hci1394_ohci_handle_t ohci_hdl)
2608 {
2609 uint32_t reg;
2610 int status;
2611
2612 ASSERT(ohci_hdl != NULL);
2613 TNF_PROBE_0_DEBUG(hci1394_ohci_cmc_check_enter, HCI1394_TNF_HAL_STACK,
2614 "");
2615 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2616 &ohci_hdl->ohci_regs->bus_options);
2617 if (reg & OHCI_REG_BUSOPTIONS_CMC) {
2618 status = B_TRUE;
2619 } else {
2620 status = B_FALSE;
2621 }
2622 TNF_PROBE_0_DEBUG(hci1394_ohci_cmc_check_exit, HCI1394_TNF_HAL_STACK,
2623 "");
2624
2625 return (status);
2626 }
2627
2628
2629 /*
2630 * hci1394_ohci_cycle_master_enable()
2631 * Enables us to be cycle master. If we are root, we will start generating
2632 * cycle start packets.
2633 */
2634 void
hci1394_ohci_cycle_master_enable(hci1394_ohci_handle_t ohci_hdl)2635 hci1394_ohci_cycle_master_enable(hci1394_ohci_handle_t ohci_hdl)
2636 {
2637 ASSERT(ohci_hdl != NULL);
2638 TNF_PROBE_0_DEBUG(hci1394_ohci_cycle_master_enable_enter,
2639 HCI1394_TNF_HAL_STACK, "");
2640
2641 /* First make sure that cycleTooLong is clear */
2642 ddi_put32(ohci_hdl->ohci_reg_handle,
2643 &ohci_hdl->ohci_regs->intr_event_clr, OHCI_INTR_CYC_TOO_LONG);
2644
2645 /* Enable Cycle Master */
2646 ddi_put32(ohci_hdl->ohci_reg_handle,
2647 &ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_CYC_MAST);
2648
2649 TNF_PROBE_0_DEBUG(hci1394_ohci_cycle_master_enable_exit,
2650 HCI1394_TNF_HAL_STACK, "");
2651 }
2652
2653
2654 /*
2655 * hci1394_ohci_cycle_master_disable()
2656 * Disabled us from being cycle master. If we are root, we will stop
2657 * generating cycle start packets.
2658 */
2659 void
hci1394_ohci_cycle_master_disable(hci1394_ohci_handle_t ohci_hdl)2660 hci1394_ohci_cycle_master_disable(hci1394_ohci_handle_t ohci_hdl)
2661 {
2662 ASSERT(ohci_hdl != NULL);
2663 TNF_PROBE_0_DEBUG(hci1394_ohci_cycle_master_disable_enter,
2664 HCI1394_TNF_HAL_STACK, "");
2665
2666 /* disable cycle master */
2667 ddi_put32(ohci_hdl->ohci_reg_handle,
2668 &ohci_hdl->ohci_regs->link_ctrl_clr, OHCI_LC_CYC_MAST);
2669
2670 TNF_PROBE_0_DEBUG(hci1394_ohci_cycle_master_disable_exit,
2671 HCI1394_TNF_HAL_STACK, "");
2672 }
2673
2674
2675 /*
2676 * hci1394_ohci_resume()
2677 * Re-initialize the openHCI HW during a resume. (after a power suspend)
2678 */
2679 int
hci1394_ohci_resume(hci1394_ohci_handle_t ohci_hdl)2680 hci1394_ohci_resume(hci1394_ohci_handle_t ohci_hdl)
2681 {
2682 uint32_t quadlet;
2683 int status;
2684
2685
2686 ASSERT(ohci_hdl != NULL);
2687 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_enter,
2688 HCI1394_TNF_HAL_STACK, "");
2689
2690 /* Re-initialize the OpenHCI chip */
2691 status = hci1394_ohci_chip_init(ohci_hdl);
2692 if (status != DDI_SUCCESS) {
2693 TNF_PROBE_0(hci1394_ohci_chip_init_fail, HCI1394_TNF_HAL_ERROR,
2694 "");
2695 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_exit,
2696 HCI1394_TNF_HAL_STACK, "");
2697 return (DDI_FAILURE);
2698 }
2699
2700 /* Re-initialize the PHY */
2701 status = hci1394_ohci_phy_resume(ohci_hdl);
2702 if (status != DDI_SUCCESS) {
2703 TNF_PROBE_0(hci1394_ohci_phy_resume_fail,
2704 HCI1394_TNF_HAL_ERROR, "");
2705 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_exit,
2706 HCI1394_TNF_HAL_STACK, "");
2707 return (DDI_FAILURE);
2708 }
2709
2710 /* Re-initialize any 1394A features we are using */
2711 status = hci1394_ohci_1394a_resume(ohci_hdl);
2712 if (status != DDI_SUCCESS) {
2713 TNF_PROBE_0(hci1394_ohci_1394a_resume_fail,
2714 HCI1394_TNF_HAL_ERROR, "");
2715 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_exit,
2716 HCI1394_TNF_HAL_STACK, "");
2717 return (DDI_FAILURE);
2718 }
2719
2720 /* Tell OpenHCI where the Config ROM buffer is */
2721 ddi_put32(ohci_hdl->ohci_reg_handle,
2722 &ohci_hdl->ohci_regs->config_rom_maplo,
2723 (uint32_t)ohci_hdl->ohci_cfgrom.bi_cookie.dmac_address);
2724
2725 /* Tell OpenHCI where the SelfId buffer is */
2726 ddi_put32(ohci_hdl->ohci_reg_handle,
2727 &ohci_hdl->ohci_regs->self_id_buflo,
2728 (uint32_t)ohci_hdl->ohci_selfid.bi_cookie.dmac_address);
2729
2730 /* Enable selfid DMA engine */
2731 hci1394_ohci_selfid_enable(ohci_hdl);
2732
2733 /*
2734 * re-setup OHCI bus options and config rom hdr registers. We need to
2735 * read from the config rom using ddi_rep_get8 since it is stored as
2736 * a byte stream. We need to swap he config rom header and bus options
2737 * on an X86 machine since the data is a byte stream and the OHCI
2738 * registers expect a big endian 32-bit number.
2739 */
2740 ddi_rep_get8(ohci_hdl->ohci_cfgrom.bi_handle, (uint8_t *)&quadlet,
2741 &((uint8_t *)ohci_hdl->ohci_cfgrom.bi_kaddr)[8], 4,
2742 DDI_DEV_AUTOINCR);
2743 ddi_put32(ohci_hdl->ohci_reg_handle,
2744 &ohci_hdl->ohci_regs->bus_options, OHCI_SWAP32(quadlet));
2745 ddi_rep_get8(ohci_hdl->ohci_cfgrom.bi_handle, (uint8_t *)&quadlet,
2746 &((uint8_t *)ohci_hdl->ohci_cfgrom.bi_kaddr)[0], 4,
2747 DDI_DEV_AUTOINCR);
2748 ddi_put32(ohci_hdl->ohci_reg_handle,
2749 &ohci_hdl->ohci_regs->config_rom_hdr, OHCI_SWAP32(quadlet));
2750
2751 TNF_PROBE_0_DEBUG(hci1394_ohci_resume_exit,
2752 HCI1394_TNF_HAL_STACK, "");
2753 return (DDI_SUCCESS);
2754 }
2755
2756
2757 /*
2758 * hci1394_ohci_selfid_init()
2759 * Initialize the selfid buffer
2760 */
2761 static int
hci1394_ohci_selfid_init(hci1394_ohci_handle_t ohci_hdl)2762 hci1394_ohci_selfid_init(hci1394_ohci_handle_t ohci_hdl)
2763 {
2764 hci1394_buf_parms_t parms;
2765 int status;
2766
2767
2768 ASSERT(ohci_hdl != NULL);
2769 TNF_PROBE_0_DEBUG(hci1394_init_selfid_enter, HCI1394_TNF_HAL_STACK, "");
2770
2771 /*
2772 * Setup for 2K buffer, aligned on a 2Kbyte address boundary. Make sure
2773 * that the buffer is not broken up into multiple cookies. OpenHCI can
2774 * only handle one address for the selfid buffer location.
2775 */
2776 parms.bp_length = 2048;
2777 parms.bp_max_cookies = 1;
2778 parms.bp_alignment = 2048;
2779 status = hci1394_buf_alloc(ohci_hdl->ohci_drvinfo, &parms,
2780 &ohci_hdl->ohci_selfid, &ohci_hdl->ohci_selfid_handle);
2781 if (status != DDI_SUCCESS) {
2782 TNF_PROBE_0(hci1394_buf_alloc_fail, HCI1394_TNF_HAL_ERROR, "");
2783 TNF_PROBE_0_DEBUG(hci1394_init_selfid_exit,
2784 HCI1394_TNF_HAL_STACK, "");
2785 return (DDI_FAILURE);
2786 }
2787
2788 /* Tell OpenHCI where the buffer is */
2789 ddi_put32(ohci_hdl->ohci_reg_handle,
2790 &ohci_hdl->ohci_regs->self_id_buflo,
2791 (uint32_t)ohci_hdl->ohci_selfid.bi_cookie.dmac_address);
2792
2793 /* Enable selfid DMA engine */
2794 hci1394_ohci_selfid_enable(ohci_hdl);
2795
2796 TNF_PROBE_0_DEBUG(hci1394_init_selfid_exit, HCI1394_TNF_HAL_STACK, "");
2797
2798 return (DDI_SUCCESS);
2799 }
2800
2801
2802 /*
2803 * hci1394_ohci_selfid_enable()
2804 * Allow selfid packets to be placed into the selfid buffer. This should be
2805 * called after the selfid buffer address has been setup in the HW.
2806 */
2807 void
hci1394_ohci_selfid_enable(hci1394_ohci_handle_t ohci_hdl)2808 hci1394_ohci_selfid_enable(hci1394_ohci_handle_t ohci_hdl)
2809 {
2810 ASSERT(ohci_hdl != NULL);
2811 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_enable_enter,
2812 HCI1394_TNF_HAL_STACK, "");
2813
2814 /*
2815 * Allow selfid packets to be received. This should be called during
2816 * driver attach after the selfid buffer address has been initialized.
2817 *
2818 * Link Control Register
2819 * rscSelfId = 1 <= bit 9
2820 */
2821 ddi_put32(ohci_hdl->ohci_reg_handle,
2822 &ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_RCV_SELF);
2823
2824 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_enable_exit,
2825 HCI1394_TNF_HAL_STACK, "");
2826 }
2827
2828
2829 /*
2830 * hci1394_ohci_selfid_read()
2831 * Read a word out of the selfid buffer.
2832 */
2833 void
hci1394_ohci_selfid_read(hci1394_ohci_handle_t ohci_hdl,uint_t offset,uint32_t * data)2834 hci1394_ohci_selfid_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset,
2835 uint32_t *data)
2836 {
2837 ASSERT(ohci_hdl != NULL);
2838 ASSERT(data != NULL);
2839 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_read_enter,
2840 HCI1394_TNF_HAL_STACK, "");
2841 *data = ddi_get32(ohci_hdl->ohci_selfid.bi_handle,
2842 &((uint32_t *)ohci_hdl->ohci_selfid.bi_kaddr)[offset]);
2843 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_read_exit,
2844 HCI1394_TNF_HAL_STACK, "");
2845 }
2846
2847
2848 /*
2849 * hci1394_ohci_selfid_info()
2850 * Return the current bus generation, the number of bytes currently in the
2851 * selfid buffer, and if we have seen any selfid errors.
2852 */
2853 void
hci1394_ohci_selfid_info(hci1394_ohci_handle_t ohci_hdl,uint_t * busgen,uint_t * size,boolean_t * error)2854 hci1394_ohci_selfid_info(hci1394_ohci_handle_t ohci_hdl, uint_t *busgen,
2855 uint_t *size, boolean_t *error)
2856 {
2857 uint32_t reg;
2858
2859
2860 ASSERT(ohci_hdl != NULL);
2861 ASSERT(busgen != NULL);
2862 ASSERT(size != NULL);
2863 ASSERT(error != NULL);
2864 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_info_enter,
2865 HCI1394_TNF_HAL_STACK, "");
2866
2867 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2868 &ohci_hdl->ohci_regs->self_id_count);
2869 *busgen = (reg & OHCI_SLFC_GEN_MASK) >> OHCI_SLFC_GEN_SHIFT;
2870 *size = reg & OHCI_SLFC_NUM_QUADS_MASK;
2871 if ((reg & OHCI_SLFC_ERROR) == 0) {
2872 *error = B_FALSE;
2873 } else {
2874 *error = B_TRUE;
2875 }
2876
2877 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_info_exit,
2878 HCI1394_TNF_HAL_STACK, "");
2879 }
2880
2881
2882 /*
2883 * hci1394_ohci_selfid_buf_current()
2884 * Test if the selfid buffer is current. Return B_TRUE if it is current and
2885 * B_FALSE if it is not current.
2886 */
2887 boolean_t
hci1394_ohci_selfid_buf_current(hci1394_ohci_handle_t ohci_hdl)2888 hci1394_ohci_selfid_buf_current(hci1394_ohci_handle_t ohci_hdl)
2889 {
2890 uint32_t reg;
2891 int status;
2892
2893 ASSERT(ohci_hdl != NULL);
2894 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_buf_current_enter,
2895 HCI1394_TNF_HAL_STACK, "");
2896
2897 /*
2898 * if the generation stored in the selfid buffer is not equal to the
2899 * generation we have previously stored, the selfid buffer is not
2900 * current. (It maybe older or it maybe newer)
2901 */
2902 reg = ddi_get32(ohci_hdl->ohci_selfid.bi_handle,
2903 &((uint32_t *)ohci_hdl->ohci_selfid.bi_kaddr)[0]);
2904 if (ohci_hdl->ohci_drvinfo->di_gencnt != ((reg & OHCI_SLFC_GEN_MASK) >>
2905 OHCI_SLFC_GEN_SHIFT)) {
2906 status = B_FALSE;
2907 } else {
2908 status = B_TRUE;
2909 }
2910
2911 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_buf_current_exit,
2912 HCI1394_TNF_HAL_STACK, "");
2913
2914 return (status);
2915 }
2916
2917
2918 /*
2919 * hci1394_ohci_selfid_sync()
2920 * Perform a ddi_dma_sync on the selfid buffer
2921 */
2922 void
hci1394_ohci_selfid_sync(hci1394_ohci_handle_t ohci_hdl)2923 hci1394_ohci_selfid_sync(hci1394_ohci_handle_t ohci_hdl)
2924 {
2925 ASSERT(ohci_hdl != NULL);
2926 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_sync_enter,
2927 HCI1394_TNF_HAL_STACK, "");
2928 (void) ddi_dma_sync(ohci_hdl->ohci_selfid.bi_dma_handle, 0,
2929 ohci_hdl->ohci_selfid.bi_length, DDI_DMA_SYNC_FORKERNEL);
2930 TNF_PROBE_0_DEBUG(hci1394_ohci_selfid_sync_exit, HCI1394_TNF_HAL_STACK,
2931 "");
2932 }
2933
2934
2935 /*
2936 * hci1394_ohci_cfgrom_init()
2937 * Initialize the configuration ROM buffer
2938 */
2939 static int
hci1394_ohci_cfgrom_init(hci1394_ohci_handle_t ohci_hdl)2940 hci1394_ohci_cfgrom_init(hci1394_ohci_handle_t ohci_hdl)
2941 {
2942 hci1394_buf_parms_t parms;
2943 int status;
2944
2945
2946 ASSERT(ohci_hdl != NULL);
2947 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_init_enter,
2948 HCI1394_TNF_HAL_STACK, "");
2949
2950 /*
2951 * Setup for 1K buffer, aligned at 1K address boundary, and allow no
2952 * less than 4 byte data transfers. Create the Buffer. Make sure that
2953 * the buffer is not broken up into multiple cookies. OpenHCI can only
2954 * handle one address for the config ROM buffer location.
2955 */
2956 parms.bp_length = 1024;
2957 parms.bp_max_cookies = 1;
2958 parms.bp_alignment = 1024;
2959 status = hci1394_buf_alloc(ohci_hdl->ohci_drvinfo, &parms,
2960 &ohci_hdl->ohci_cfgrom, &ohci_hdl->ohci_cfgrom_handle);
2961 if (status != DDI_SUCCESS) {
2962 TNF_PROBE_0(hci1394_buf_alloc_fail, HCI1394_TNF_HAL_ERROR, "");
2963 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_init_exit,
2964 HCI1394_TNF_HAL_STACK, "");
2965 return (DDI_FAILURE);
2966 }
2967
2968 /* Tell OpenHCI where the buffer is */
2969 ddi_put32(ohci_hdl->ohci_reg_handle,
2970 &ohci_hdl->ohci_regs->config_rom_maplo,
2971 (uint32_t)ohci_hdl->ohci_cfgrom.bi_cookie.dmac_address);
2972
2973 TNF_PROBE_0_DEBUG(hci1394_ohci_cfgrom_init_exit, HCI1394_TNF_HAL_STACK,
2974 "");
2975
2976 return (DDI_SUCCESS);
2977 }
2978
2979
2980 /*
2981 * hci1394_ohci_bus_capabilities()
2982 * Return our current bus capabilities
2983 */
2984 void
hci1394_ohci_bus_capabilities(hci1394_ohci_handle_t ohci_hdl,uint32_t * bus_capabilities)2985 hci1394_ohci_bus_capabilities(hci1394_ohci_handle_t ohci_hdl,
2986 uint32_t *bus_capabilities)
2987 {
2988 ASSERT(ohci_hdl != NULL);
2989 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_capabilities_enter,
2990 HCI1394_TNF_HAL_STACK, "");
2991 /*
2992 * read in the bus options register. Set bits saying that we are isoch
2993 * resource manager capable, Cycle master capable, and Isoch capable
2994 */
2995 *bus_capabilities = ddi_get32(ohci_hdl->ohci_reg_handle,
2996 &ohci_hdl->ohci_regs->bus_options) | (OHCI_BOPT_IRMC |
2997 OHCI_BOPT_CMC | OHCI_BOPT_ISC);
2998 TNF_PROBE_0_DEBUG(hci1394_ohci_bus_capabilities_exit,
2999 HCI1394_TNF_HAL_STACK, "");
3000 }
3001
3002
3003 /*
3004 * hci1394_ohci_at_active()
3005 * Returns status one if either of the AT engines are active. If either AT
3006 * engine is active, we return B_TRUE. If both AT engines are not active, we
3007 * return B_FALSE.
3008 */
3009 boolean_t
hci1394_ohci_at_active(hci1394_ohci_handle_t ohci_hdl)3010 hci1394_ohci_at_active(hci1394_ohci_handle_t ohci_hdl)
3011 {
3012 uint32_t reg;
3013
3014
3015 ASSERT(ohci_hdl != NULL);
3016 TNF_PROBE_0_DEBUG(hci1394_ohci_at_active_enter,
3017 HCI1394_TNF_HAL_STACK, "");
3018
3019 /* see if atreq active bit set */
3020 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
3021 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set);
3022 if (reg & OHCI_CC_ACTIVE_MASK) {
3023 /* atreq engine is still active */
3024 TNF_PROBE_0(hci1394_ohci_atreq_active_fail,
3025 HCI1394_TNF_HAL_ERROR, "");
3026 TNF_PROBE_0_DEBUG(hci1394_ohci_at_active_exit,
3027 HCI1394_TNF_HAL_STACK, "");
3028 return (B_TRUE);
3029 }
3030
3031 /* see if atresp active bit set */
3032 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
3033 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set);
3034 if (reg & OHCI_CC_ACTIVE_MASK) {
3035 /* atresp engine is still active */
3036 TNF_PROBE_0(hci1394_ohci_atresp_active_fail,
3037 HCI1394_TNF_HAL_ERROR, "");
3038 TNF_PROBE_0_DEBUG(hci1394_ohci_at_active_exit,
3039 HCI1394_TNF_HAL_STACK, "");
3040 return (B_TRUE);
3041 }
3042
3043 TNF_PROBE_0_DEBUG(hci1394_ohci_at_active_exit,
3044 HCI1394_TNF_HAL_STACK, "");
3045
3046 /* both atreq and atresp active bits are cleared */
3047 return (B_FALSE);
3048 }
3049
3050
3051 /*
3052 * hci1394_ohci_atreq_start()
3053 * Start the atreq dma engine. Set the address of the first descriptor
3054 * to read in equal to cmdptr.
3055 */
3056 void
hci1394_ohci_atreq_start(hci1394_ohci_handle_t ohci_hdl,uint32_t cmdptr)3057 hci1394_ohci_atreq_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr)
3058 {
3059 ASSERT(ohci_hdl != NULL);
3060 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_start_enter,
3061 HCI1394_TNF_HAL_STACK, "");
3062
3063 ddi_put32(ohci_hdl->ohci_reg_handle,
3064 &ohci_hdl->ohci_regs->at_req.cmd_ptrlo, cmdptr);
3065 ddi_put32(ohci_hdl->ohci_reg_handle,
3066 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set, OHCI_CC_RUN_MASK);
3067
3068 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_start_exit,
3069 HCI1394_TNF_HAL_STACK, "");
3070 }
3071
3072
3073 /*
3074 * hci1394_ohci_atreq_wake()
3075 * Wake up the atreq dma engine. This should be called when a new descriptor
3076 * is added to the Q and the dma engine has already be started. It it OK to
3077 * call this when the DMA engine is active.
3078 */
3079 void
hci1394_ohci_atreq_wake(hci1394_ohci_handle_t ohci_hdl)3080 hci1394_ohci_atreq_wake(hci1394_ohci_handle_t ohci_hdl)
3081 {
3082 ASSERT(ohci_hdl != NULL);
3083 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_wake_enter,
3084 HCI1394_TNF_HAL_STACK, "");
3085
3086 ddi_put32(ohci_hdl->ohci_reg_handle,
3087 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set, OHCI_CC_WAKE_MASK);
3088
3089 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_wake_exit,
3090 HCI1394_TNF_HAL_STACK, "");
3091 }
3092
3093
3094 /*
3095 * hci1394_ohci_atreq_stop()
3096 * Stop the atreq dma engine. No further descriptors will be read until
3097 * it dma engine is started again.
3098 */
3099 void
hci1394_ohci_atreq_stop(hci1394_ohci_handle_t ohci_hdl)3100 hci1394_ohci_atreq_stop(hci1394_ohci_handle_t ohci_hdl)
3101 {
3102 ASSERT(ohci_hdl != NULL);
3103 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_stop_enter,
3104 HCI1394_TNF_HAL_STACK, "");
3105
3106 ddi_put32(ohci_hdl->ohci_reg_handle,
3107 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_clr, OHCI_CC_RUN_MASK);
3108
3109 TNF_PROBE_0_DEBUG(hci1394_ohci_atreq_stop_exit,
3110 HCI1394_TNF_HAL_STACK, "");
3111 }
3112
3113
3114 /*
3115 * hci1394_ohci_arresp_start()
3116 * Start the arresp dma engine. Set the address of the first descriptor
3117 * to read in equal to cmdptr.
3118 */
3119 void
hci1394_ohci_arresp_start(hci1394_ohci_handle_t ohci_hdl,uint32_t cmdptr)3120 hci1394_ohci_arresp_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr)
3121 {
3122 ASSERT(ohci_hdl != NULL);
3123 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_start_enter,
3124 HCI1394_TNF_HAL_STACK, "");
3125
3126 ddi_put32(ohci_hdl->ohci_reg_handle,
3127 &ohci_hdl->ohci_regs->ar_resp.cmd_ptrlo, cmdptr);
3128 ddi_put32(ohci_hdl->ohci_reg_handle,
3129 &ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_set, OHCI_CC_RUN_MASK);
3130
3131 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_start_exit,
3132 HCI1394_TNF_HAL_STACK, "");
3133 }
3134
3135
3136 /*
3137 * hci1394_ohci_arresp_wake()
3138 * Wake up the arresp dma engine. This should be called when a new
3139 * descriptor is added to the Q and the dma engine has already be started.
3140 * It is OK to call this when the DMA engine is active.
3141 */
3142 void
hci1394_ohci_arresp_wake(hci1394_ohci_handle_t ohci_hdl)3143 hci1394_ohci_arresp_wake(hci1394_ohci_handle_t ohci_hdl)
3144 {
3145 ASSERT(ohci_hdl != NULL);
3146 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_wake_enter,
3147 HCI1394_TNF_HAL_STACK, "");
3148
3149 ddi_put32(ohci_hdl->ohci_reg_handle,
3150 &ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_set, OHCI_CC_WAKE_MASK);
3151
3152 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_wake_exit,
3153 HCI1394_TNF_HAL_STACK, "");
3154 }
3155
3156
3157 /*
3158 * hci1394_ohci_atreq_stop()
3159 * Stop the arresp dma engine. No further data will be received after any
3160 * current packets being received have finished.
3161 */
3162 void
hci1394_ohci_arresp_stop(hci1394_ohci_handle_t ohci_hdl)3163 hci1394_ohci_arresp_stop(hci1394_ohci_handle_t ohci_hdl)
3164 {
3165 ASSERT(ohci_hdl != NULL);
3166 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_stop_enter,
3167 HCI1394_TNF_HAL_STACK, "");
3168
3169 ddi_put32(ohci_hdl->ohci_reg_handle,
3170 &ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_clr, OHCI_CC_RUN_MASK);
3171
3172 TNF_PROBE_0_DEBUG(hci1394_ohci_arresp_stop_exit,
3173 HCI1394_TNF_HAL_STACK, "");
3174 }
3175
3176
3177 /*
3178 * hci1394_ohci_arreq_start()
3179 * Start the arreq dma engine. Set the address of the first descriptor
3180 * to read in equal to cmdptr.
3181 */
3182 void
hci1394_ohci_arreq_start(hci1394_ohci_handle_t ohci_hdl,uint32_t cmdptr)3183 hci1394_ohci_arreq_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr)
3184 {
3185 ASSERT(ohci_hdl != NULL);
3186 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_start_enter,
3187 HCI1394_TNF_HAL_STACK, "");
3188
3189 ddi_put32(ohci_hdl->ohci_reg_handle,
3190 &ohci_hdl->ohci_regs->ar_req.cmd_ptrlo, cmdptr);
3191 ddi_put32(ohci_hdl->ohci_reg_handle,
3192 &ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_set, OHCI_CC_RUN_MASK);
3193
3194 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_start_exit,
3195 HCI1394_TNF_HAL_STACK, "");
3196 }
3197
3198
3199 /*
3200 * hci1394_ohci_arreq_wake()
3201 * Wake up the arreq dma engine. This should be called when a new descriptor
3202 * is added to the Q and the dma engine has already be started. It is OK to
3203 * call this when the DMA engine is active.
3204 */
3205 void
hci1394_ohci_arreq_wake(hci1394_ohci_handle_t ohci_hdl)3206 hci1394_ohci_arreq_wake(hci1394_ohci_handle_t ohci_hdl)
3207 {
3208 ASSERT(ohci_hdl != NULL);
3209 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_wake_enter,
3210 HCI1394_TNF_HAL_STACK, "");
3211
3212 ddi_put32(ohci_hdl->ohci_reg_handle,
3213 &ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_set, OHCI_CC_WAKE_MASK);
3214
3215 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_wake_exit,
3216 HCI1394_TNF_HAL_STACK, "");
3217 }
3218
3219
3220 /*
3221 * hci1394_ohci_arreq_stop()
3222 * Stop the arreq dma engine. No further data will be received after any
3223 * current packets being received have finished.
3224 */
3225 void
hci1394_ohci_arreq_stop(hci1394_ohci_handle_t ohci_hdl)3226 hci1394_ohci_arreq_stop(hci1394_ohci_handle_t ohci_hdl)
3227 {
3228 ASSERT(ohci_hdl != NULL);
3229 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_stop_enter,
3230 HCI1394_TNF_HAL_STACK, "");
3231
3232 ddi_put32(ohci_hdl->ohci_reg_handle,
3233 &ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_clr, OHCI_CC_RUN_MASK);
3234
3235 TNF_PROBE_0_DEBUG(hci1394_ohci_arreq_stop_exit,
3236 HCI1394_TNF_HAL_STACK, "");
3237 }
3238
3239
3240 /*
3241 * hci1394_ohci_atresp_start()
3242 * Start the atresp dma engine. Set the address of the first descriptor
3243 * to read in equal to cmdptr.
3244 */
3245 void
hci1394_ohci_atresp_start(hci1394_ohci_handle_t ohci_hdl,uint32_t cmdptr)3246 hci1394_ohci_atresp_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr)
3247 {
3248 ASSERT(ohci_hdl != NULL);
3249 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_start_enter,
3250 HCI1394_TNF_HAL_STACK, "");
3251
3252 ddi_put32(ohci_hdl->ohci_reg_handle,
3253 &ohci_hdl->ohci_regs->at_resp.cmd_ptrlo, cmdptr);
3254 ddi_put32(ohci_hdl->ohci_reg_handle,
3255 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set, OHCI_CC_RUN_MASK);
3256
3257 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_start_exit,
3258 HCI1394_TNF_HAL_STACK, "");
3259 }
3260
3261
3262 /*
3263 * hci1394_ohci_atresp_wake()
3264 * Wake up the atresp dma engine. This should be called when a new
3265 * descriptor is added to the Q and the dma engine has already be started.
3266 * It is OK to call this when the DMA engine is active.
3267 */
3268 void
hci1394_ohci_atresp_wake(hci1394_ohci_handle_t ohci_hdl)3269 hci1394_ohci_atresp_wake(hci1394_ohci_handle_t ohci_hdl)
3270 {
3271 ASSERT(ohci_hdl != NULL);
3272 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_wake_enter,
3273 HCI1394_TNF_HAL_STACK, "");
3274
3275 ddi_put32(ohci_hdl->ohci_reg_handle,
3276 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set, OHCI_CC_WAKE_MASK);
3277
3278 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_wake_exit,
3279 HCI1394_TNF_HAL_STACK, "");
3280 }
3281
3282
3283 /*
3284 * hci1394_ohci_atresp_stop()
3285 * Stop the atresp dma engine. No further descriptors will be read until
3286 * it dma engine is started again.
3287 */
3288 void
hci1394_ohci_atresp_stop(hci1394_ohci_handle_t ohci_hdl)3289 hci1394_ohci_atresp_stop(hci1394_ohci_handle_t ohci_hdl)
3290 {
3291 ASSERT(ohci_hdl != NULL);
3292 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_stop_enter,
3293 HCI1394_TNF_HAL_STACK, "");
3294
3295 ddi_put32(ohci_hdl->ohci_reg_handle,
3296 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_clr, OHCI_CC_RUN_MASK);
3297
3298 TNF_PROBE_0_DEBUG(hci1394_ohci_atresp_stop_exit,
3299 HCI1394_TNF_HAL_STACK, "");
3300 }
3301
3302
3303 /*
3304 * hci1394_ohci_1394a_init()
3305 * Initialize any 1394a features that we are using.
3306 */
3307 /* ARGSUSED */
3308 int
hci1394_ohci_1394a_init(hci1394_ohci_handle_t ohci_hdl)3309 hci1394_ohci_1394a_init(hci1394_ohci_handle_t ohci_hdl)
3310 {
3311 uint32_t reg;
3312 int status;
3313
3314 ASSERT(ohci_hdl != NULL);
3315 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_init_enter, HCI1394_TNF_HAL_STACK,
3316 "");
3317
3318 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
3319 &ohci_hdl->ohci_regs->hc_ctrl_set);
3320 if (reg & OHCI_HC_PROG_PHY_ENBL) {
3321 ddi_put32(ohci_hdl->ohci_reg_handle,
3322 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_APHY_ENBL);
3323 status = hci1394_ohci_phy_set(ohci_hdl, 5,
3324 (OHCI_PHY_ENBL_ACCEL | OHCI_PHY_ENBL_MULTI));
3325 if (status != DDI_SUCCESS) {
3326 TNF_PROBE_0(hci1394_ohci_1394a_init_phy_fail,
3327 HCI1394_TNF_HAL_STACK, "");
3328 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_init_exit,
3329 HCI1394_TNF_HAL_STACK, "");
3330 return (DDI_FAILURE);
3331 }
3332 }
3333
3334 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_init_exit, HCI1394_TNF_HAL_STACK,
3335 "");
3336 return (DDI_SUCCESS);
3337 }
3338
3339
3340 /*
3341 * hci1394_ohci_1394a_init()
3342 * Re-initialize any 1394a features that we are using.
3343 */
3344 /* ARGSUSED */
3345 int
hci1394_ohci_1394a_resume(hci1394_ohci_handle_t ohci_hdl)3346 hci1394_ohci_1394a_resume(hci1394_ohci_handle_t ohci_hdl)
3347 {
3348 uint32_t reg;
3349 int status;
3350
3351 ASSERT(ohci_hdl != NULL);
3352 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_resume_enter,
3353 HCI1394_TNF_HAL_STACK, "");
3354
3355 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
3356 &ohci_hdl->ohci_regs->hc_ctrl_set);
3357 if (reg & OHCI_HC_PROG_PHY_ENBL) {
3358 ddi_put32(ohci_hdl->ohci_reg_handle,
3359 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_APHY_ENBL);
3360 status = hci1394_ohci_phy_set(ohci_hdl, 5,
3361 (OHCI_PHY_ENBL_ACCEL | OHCI_PHY_ENBL_MULTI));
3362 if (status != DDI_SUCCESS) {
3363 TNF_PROBE_0(hci1394_ohci_1394a_resume_phy_fail,
3364 HCI1394_TNF_HAL_STACK, "");
3365 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_resume_exit,
3366 HCI1394_TNF_HAL_STACK, "");
3367 return (DDI_FAILURE);
3368 }
3369 }
3370
3371 TNF_PROBE_0_DEBUG(hci1394_ohci_1394a_resume_exit,
3372 HCI1394_TNF_HAL_STACK, "");
3373 return (DDI_SUCCESS);
3374 }
3375