1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34
35 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
36 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
37 */
38
39 #include "e1000_api.h"
40
41 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
42 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
43 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
44 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
45 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
46 u32 offset,
47 u16 *data);
48 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
49 u32 offset,
50 u16 data);
51 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
52 u16 words, u16 *data);
53 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
54 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
55 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
56 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
57 u16 *duplex);
58 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
59 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
60 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
61 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
62 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
63 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
64 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
65 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
66 u16 *data);
67 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
68 u16 data);
69 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
70 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
71 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
72
73 /* A table for the GG82563 cable length where the range is defined
74 * with a lower bound at "index" and the upper bound at
75 * "index + 5".
76 */
77 static const u16 e1000_gg82563_cable_length_table[] = {
78 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
79 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
80 (sizeof(e1000_gg82563_cable_length_table) / \
81 sizeof(e1000_gg82563_cable_length_table[0]))
82
83 /**
84 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
85 * @hw: pointer to the HW structure
86 **/
e1000_init_phy_params_80003es2lan(struct e1000_hw * hw)87 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
88 {
89 struct e1000_phy_info *phy = &hw->phy;
90 s32 ret_val;
91
92 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
93
94 if (hw->phy.media_type != e1000_media_type_copper) {
95 phy->type = e1000_phy_none;
96 return E1000_SUCCESS;
97 } else {
98 phy->ops.power_up = e1000_power_up_phy_copper;
99 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
100 }
101
102 phy->addr = 1;
103 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
104 phy->reset_delay_us = 100;
105 phy->type = e1000_phy_gg82563;
106
107 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
108 phy->ops.check_polarity = e1000_check_polarity_m88;
109 phy->ops.check_reset_block = e1000_check_reset_block_generic;
110 phy->ops.commit = e1000_phy_sw_reset_generic;
111 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
112 phy->ops.get_info = e1000_get_phy_info_m88;
113 phy->ops.release = e1000_release_phy_80003es2lan;
114 phy->ops.reset = e1000_phy_hw_reset_generic;
115 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
116
117 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
118 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
119 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
120 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
121
122 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
123
124 /* This can only be done after all function pointers are setup. */
125 ret_val = e1000_get_phy_id(hw);
126
127 /* Verify phy id */
128 if (phy->id != GG82563_E_PHY_ID)
129 return -E1000_ERR_PHY;
130
131 return ret_val;
132 }
133
134 /**
135 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
136 * @hw: pointer to the HW structure
137 **/
e1000_init_nvm_params_80003es2lan(struct e1000_hw * hw)138 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
139 {
140 struct e1000_nvm_info *nvm = &hw->nvm;
141 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
142 u16 size;
143
144 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
145
146 nvm->opcode_bits = 8;
147 nvm->delay_usec = 1;
148 switch (nvm->override) {
149 case e1000_nvm_override_spi_large:
150 nvm->page_size = 32;
151 nvm->address_bits = 16;
152 break;
153 case e1000_nvm_override_spi_small:
154 nvm->page_size = 8;
155 nvm->address_bits = 8;
156 break;
157 default:
158 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
159 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
160 break;
161 }
162
163 nvm->type = e1000_nvm_eeprom_spi;
164
165 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
166 E1000_EECD_SIZE_EX_SHIFT);
167
168 /* Added to a constant, "size" becomes the left-shift value
169 * for setting word_size.
170 */
171 size += NVM_WORD_SIZE_BASE_SHIFT;
172
173 /* EEPROM access above 16k is unsupported */
174 if (size > 14)
175 size = 14;
176 nvm->word_size = 1 << size;
177
178 /* Function Pointers */
179 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
180 nvm->ops.read = e1000_read_nvm_eerd;
181 nvm->ops.release = e1000_release_nvm_80003es2lan;
182 nvm->ops.update = e1000_update_nvm_checksum_generic;
183 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
184 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
185 nvm->ops.write = e1000_write_nvm_80003es2lan;
186
187 return E1000_SUCCESS;
188 }
189
190 /**
191 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
192 * @hw: pointer to the HW structure
193 **/
e1000_init_mac_params_80003es2lan(struct e1000_hw * hw)194 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
195 {
196 struct e1000_mac_info *mac = &hw->mac;
197
198 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
199
200 /* Set media type and media-dependent function pointers */
201 switch (hw->device_id) {
202 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
203 hw->phy.media_type = e1000_media_type_internal_serdes;
204 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
205 mac->ops.setup_physical_interface =
206 e1000_setup_fiber_serdes_link_generic;
207 break;
208 default:
209 hw->phy.media_type = e1000_media_type_copper;
210 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
211 mac->ops.setup_physical_interface =
212 e1000_setup_copper_link_80003es2lan;
213 break;
214 }
215
216 /* Set mta register count */
217 mac->mta_reg_count = 128;
218 /* Set rar entry count */
219 mac->rar_entry_count = E1000_RAR_ENTRIES;
220 /* Set if part includes ASF firmware */
221 mac->asf_firmware_present = true;
222 /* FWSM register */
223 mac->has_fwsm = true;
224 /* ARC supported; valid only if manageability features are enabled. */
225 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
226 E1000_FWSM_MODE_MASK);
227 /* Adaptive IFS not supported */
228 mac->adaptive_ifs = false;
229
230 /* Function pointers */
231
232 /* bus type/speed/width */
233 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
234 /* reset */
235 mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
236 /* hw initialization */
237 mac->ops.init_hw = e1000_init_hw_80003es2lan;
238 /* link setup */
239 mac->ops.setup_link = e1000_setup_link_generic;
240 /* check management mode */
241 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
242 /* multicast address update */
243 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
244 /* writing VFTA */
245 mac->ops.write_vfta = e1000_write_vfta_generic;
246 /* clearing VFTA */
247 mac->ops.clear_vfta = e1000_clear_vfta_generic;
248 /* read mac address */
249 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
250 /* ID LED init */
251 mac->ops.id_led_init = e1000_id_led_init_generic;
252 /* blink LED */
253 mac->ops.blink_led = e1000_blink_led_generic;
254 /* setup LED */
255 mac->ops.setup_led = e1000_setup_led_generic;
256 /* cleanup LED */
257 mac->ops.cleanup_led = e1000_cleanup_led_generic;
258 /* turn on/off LED */
259 mac->ops.led_on = e1000_led_on_generic;
260 mac->ops.led_off = e1000_led_off_generic;
261 /* clear hardware counters */
262 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
263 /* link info */
264 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
265
266 /* set lan id for port to determine which phy lock to use */
267 hw->mac.ops.set_lan_id(hw);
268
269 return E1000_SUCCESS;
270 }
271
272 /**
273 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
274 * @hw: pointer to the HW structure
275 *
276 * Called to initialize all function pointers and parameters.
277 **/
e1000_init_function_pointers_80003es2lan(struct e1000_hw * hw)278 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
279 {
280 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
281
282 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
283 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
284 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
285 }
286
287 /**
288 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
289 * @hw: pointer to the HW structure
290 *
291 * A wrapper to acquire access rights to the correct PHY.
292 **/
e1000_acquire_phy_80003es2lan(struct e1000_hw * hw)293 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
294 {
295 u16 mask;
296
297 DEBUGFUNC("e1000_acquire_phy_80003es2lan");
298
299 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
300 return e1000_acquire_swfw_sync(hw, mask);
301 }
302
303 /**
304 * e1000_release_phy_80003es2lan - Release rights to access PHY
305 * @hw: pointer to the HW structure
306 *
307 * A wrapper to release access rights to the correct PHY.
308 **/
e1000_release_phy_80003es2lan(struct e1000_hw * hw)309 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
310 {
311 u16 mask;
312
313 DEBUGFUNC("e1000_release_phy_80003es2lan");
314
315 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
316 e1000_release_swfw_sync(hw, mask);
317 }
318
319 /**
320 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
321 * @hw: pointer to the HW structure
322 *
323 * Acquire the semaphore to access the Kumeran interface.
324 *
325 **/
e1000_acquire_mac_csr_80003es2lan(struct e1000_hw * hw)326 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
327 {
328 u16 mask;
329
330 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
331
332 mask = E1000_SWFW_CSR_SM;
333
334 return e1000_acquire_swfw_sync(hw, mask);
335 }
336
337 /**
338 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
339 * @hw: pointer to the HW structure
340 *
341 * Release the semaphore used to access the Kumeran interface
342 **/
e1000_release_mac_csr_80003es2lan(struct e1000_hw * hw)343 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
344 {
345 u16 mask;
346
347 DEBUGFUNC("e1000_release_mac_csr_80003es2lan");
348
349 mask = E1000_SWFW_CSR_SM;
350
351 e1000_release_swfw_sync(hw, mask);
352 }
353
354 /**
355 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
356 * @hw: pointer to the HW structure
357 *
358 * Acquire the semaphore to access the EEPROM.
359 **/
e1000_acquire_nvm_80003es2lan(struct e1000_hw * hw)360 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
361 {
362 s32 ret_val;
363
364 DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
365
366 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
367 if (ret_val)
368 return ret_val;
369
370 ret_val = e1000_acquire_nvm_generic(hw);
371
372 if (ret_val)
373 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
374
375 return ret_val;
376 }
377
378 /**
379 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
380 * @hw: pointer to the HW structure
381 *
382 * Release the semaphore used to access the EEPROM.
383 **/
e1000_release_nvm_80003es2lan(struct e1000_hw * hw)384 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
385 {
386 DEBUGFUNC("e1000_release_nvm_80003es2lan");
387
388 e1000_release_nvm_generic(hw);
389 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM);
390 }
391
392 /**
393 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
394 * @hw: pointer to the HW structure
395 * @offset: offset of the register to read
396 * @data: pointer to the data returned from the operation
397 *
398 * Read the GG82563 PHY register.
399 **/
e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw * hw,u32 offset,u16 * data)400 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
401 u32 offset, u16 *data)
402 {
403 s32 ret_val;
404 u32 page_select;
405 u16 temp;
406
407 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
408
409 ret_val = e1000_acquire_phy_80003es2lan(hw);
410 if (ret_val)
411 return ret_val;
412
413 /* Select Configuration Page */
414 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
415 page_select = GG82563_PHY_PAGE_SELECT;
416 } else {
417 /* Use Alternative Page Select register to access
418 * registers 30 and 31
419 */
420 page_select = GG82563_PHY_PAGE_SELECT_ALT;
421 }
422
423 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
424 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
425 if (ret_val) {
426 e1000_release_phy_80003es2lan(hw);
427 return ret_val;
428 }
429
430 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
431 /* The "ready" bit in the MDIC register may be incorrectly set
432 * before the device has completed the "Page Select" MDI
433 * transaction. So we wait 200us after each MDI command...
434 */
435 usec_delay(200);
436
437 /* ...and verify the command was successful. */
438 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
439
440 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
441 e1000_release_phy_80003es2lan(hw);
442 return -E1000_ERR_PHY;
443 }
444
445 usec_delay(200);
446
447 ret_val = e1000_read_phy_reg_mdic(hw,
448 MAX_PHY_REG_ADDRESS & offset,
449 data);
450
451 usec_delay(200);
452 } else {
453 ret_val = e1000_read_phy_reg_mdic(hw,
454 MAX_PHY_REG_ADDRESS & offset,
455 data);
456 }
457
458 e1000_release_phy_80003es2lan(hw);
459
460 return ret_val;
461 }
462
463 /**
464 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
465 * @hw: pointer to the HW structure
466 * @offset: offset of the register to read
467 * @data: value to write to the register
468 *
469 * Write to the GG82563 PHY register.
470 **/
e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw * hw,u32 offset,u16 data)471 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
472 u32 offset, u16 data)
473 {
474 s32 ret_val;
475 u32 page_select;
476 u16 temp;
477
478 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
479
480 ret_val = e1000_acquire_phy_80003es2lan(hw);
481 if (ret_val)
482 return ret_val;
483
484 /* Select Configuration Page */
485 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
486 page_select = GG82563_PHY_PAGE_SELECT;
487 } else {
488 /* Use Alternative Page Select register to access
489 * registers 30 and 31
490 */
491 page_select = GG82563_PHY_PAGE_SELECT_ALT;
492 }
493
494 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
495 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
496 if (ret_val) {
497 e1000_release_phy_80003es2lan(hw);
498 return ret_val;
499 }
500
501 if (hw->dev_spec._80003es2lan.mdic_wa_enable) {
502 /* The "ready" bit in the MDIC register may be incorrectly set
503 * before the device has completed the "Page Select" MDI
504 * transaction. So we wait 200us after each MDI command...
505 */
506 usec_delay(200);
507
508 /* ...and verify the command was successful. */
509 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
510
511 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
512 e1000_release_phy_80003es2lan(hw);
513 return -E1000_ERR_PHY;
514 }
515
516 usec_delay(200);
517
518 ret_val = e1000_write_phy_reg_mdic(hw,
519 MAX_PHY_REG_ADDRESS & offset,
520 data);
521
522 usec_delay(200);
523 } else {
524 ret_val = e1000_write_phy_reg_mdic(hw,
525 MAX_PHY_REG_ADDRESS & offset,
526 data);
527 }
528
529 e1000_release_phy_80003es2lan(hw);
530
531 return ret_val;
532 }
533
534 /**
535 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
536 * @hw: pointer to the HW structure
537 * @offset: offset of the register to read
538 * @words: number of words to write
539 * @data: buffer of data to write to the NVM
540 *
541 * Write "words" of data to the ESB2 NVM.
542 **/
e1000_write_nvm_80003es2lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)543 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
544 u16 words, u16 *data)
545 {
546 DEBUGFUNC("e1000_write_nvm_80003es2lan");
547
548 return e1000_write_nvm_spi(hw, offset, words, data);
549 }
550
551 /**
552 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
553 * @hw: pointer to the HW structure
554 *
555 * Wait a specific amount of time for manageability processes to complete.
556 * This is a function pointer entry point called by the phy module.
557 **/
e1000_get_cfg_done_80003es2lan(struct e1000_hw * hw)558 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
559 {
560 s32 timeout = PHY_CFG_TIMEOUT;
561 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
562
563 DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
564
565 if (hw->bus.func == 1)
566 mask = E1000_NVM_CFG_DONE_PORT_1;
567
568 while (timeout) {
569 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
570 break;
571 msec_delay(1);
572 timeout--;
573 }
574 if (!timeout) {
575 DEBUGOUT("MNG configuration cycle has not completed.\n");
576 return -E1000_ERR_RESET;
577 }
578
579 return E1000_SUCCESS;
580 }
581
582 /**
583 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
584 * @hw: pointer to the HW structure
585 *
586 * Force the speed and duplex settings onto the PHY. This is a
587 * function pointer entry point called by the phy module.
588 **/
e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw * hw)589 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
590 {
591 s32 ret_val;
592 u16 phy_data;
593 bool link;
594
595 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
596
597 if (!(hw->phy.ops.read_reg))
598 return E1000_SUCCESS;
599
600 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
601 * forced whenever speed and duplex are forced.
602 */
603 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
604 if (ret_val)
605 return ret_val;
606
607 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
608 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
609 if (ret_val)
610 return ret_val;
611
612 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data);
613
614 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
615 if (ret_val)
616 return ret_val;
617
618 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
619
620 /* Reset the phy to commit changes. */
621 phy_data |= MII_CR_RESET;
622
623 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
624 if (ret_val)
625 return ret_val;
626
627 usec_delay(1);
628
629 if (hw->phy.autoneg_wait_to_complete) {
630 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
631
632 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
633 100000, &link);
634 if (ret_val)
635 return ret_val;
636
637 if (!link) {
638 /* We didn't get link.
639 * Reset the DSP and cross our fingers.
640 */
641 ret_val = e1000_phy_reset_dsp_generic(hw);
642 if (ret_val)
643 return ret_val;
644 }
645
646 /* Try once more */
647 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
648 100000, &link);
649 if (ret_val)
650 return ret_val;
651 }
652
653 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
654 &phy_data);
655 if (ret_val)
656 return ret_val;
657
658 /* Resetting the phy means we need to verify the TX_CLK corresponds
659 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
660 */
661 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
662 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
663 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
664 else
665 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
666
667 /* In addition, we must re-enable CRS on Tx for both half and full
668 * duplex.
669 */
670 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
671 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
672 phy_data);
673
674 return ret_val;
675 }
676
677 /**
678 * e1000_get_cable_length_80003es2lan - Set approximate cable length
679 * @hw: pointer to the HW structure
680 *
681 * Find the approximate cable length as measured by the GG82563 PHY.
682 * This is a function pointer entry point called by the phy module.
683 **/
e1000_get_cable_length_80003es2lan(struct e1000_hw * hw)684 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
685 {
686 struct e1000_phy_info *phy = &hw->phy;
687 s32 ret_val;
688 u16 phy_data, index;
689
690 DEBUGFUNC("e1000_get_cable_length_80003es2lan");
691
692 if (!(hw->phy.ops.read_reg))
693 return E1000_SUCCESS;
694
695 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
696 if (ret_val)
697 return ret_val;
698
699 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
700
701 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
702 return -E1000_ERR_PHY;
703
704 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
705 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
706
707 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
708
709 return E1000_SUCCESS;
710 }
711
712 /**
713 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
714 * @hw: pointer to the HW structure
715 * @speed: pointer to speed buffer
716 * @duplex: pointer to duplex buffer
717 *
718 * Retrieve the current speed and duplex configuration.
719 **/
e1000_get_link_up_info_80003es2lan(struct e1000_hw * hw,u16 * speed,u16 * duplex)720 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
721 u16 *duplex)
722 {
723 s32 ret_val;
724
725 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
726
727 if (hw->phy.media_type == e1000_media_type_copper) {
728 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
729 duplex);
730 hw->phy.ops.cfg_on_link_up(hw);
731 } else {
732 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
733 speed,
734 duplex);
735 }
736
737 return ret_val;
738 }
739
740 /**
741 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
742 * @hw: pointer to the HW structure
743 *
744 * Perform a global reset to the ESB2 controller.
745 **/
e1000_reset_hw_80003es2lan(struct e1000_hw * hw)746 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
747 {
748 u32 ctrl;
749 s32 ret_val;
750 u16 kum_reg_data;
751
752 DEBUGFUNC("e1000_reset_hw_80003es2lan");
753
754 /* Prevent the PCI-E bus from sticking if there is no TLP connection
755 * on the last TLP read/write transaction when MAC is reset.
756 */
757 ret_val = e1000_disable_pcie_master_generic(hw);
758 if (ret_val)
759 DEBUGOUT("PCI-E Master disable polling has failed.\n");
760
761 DEBUGOUT("Masking off all interrupts\n");
762 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
763
764 E1000_WRITE_REG(hw, E1000_RCTL, 0);
765 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
766 E1000_WRITE_FLUSH(hw);
767
768 msec_delay(10);
769
770 ctrl = E1000_READ_REG(hw, E1000_CTRL);
771
772 ret_val = e1000_acquire_phy_80003es2lan(hw);
773 if (ret_val)
774 return ret_val;
775
776 DEBUGOUT("Issuing a global reset to MAC\n");
777 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
778 e1000_release_phy_80003es2lan(hw);
779
780 /* Disable IBIST slave mode (far-end loopback) */
781 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
782 E1000_KMRNCTRLSTA_INBAND_PARAM, &kum_reg_data);
783 if (!ret_val) {
784 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
785 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
786 E1000_KMRNCTRLSTA_INBAND_PARAM,
787 kum_reg_data);
788 if (ret_val)
789 DEBUGOUT("Error disabling far-end loopback\n");
790 } else
791 DEBUGOUT("Error disabling far-end loopback\n");
792
793 ret_val = e1000_get_auto_rd_done_generic(hw);
794 if (ret_val)
795 /* We don't want to continue accessing MAC registers. */
796 return ret_val;
797
798 /* Clear any pending interrupt events. */
799 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
800 E1000_READ_REG(hw, E1000_ICR);
801
802 return e1000_check_alt_mac_addr_generic(hw);
803 }
804
805 /**
806 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
807 * @hw: pointer to the HW structure
808 *
809 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
810 **/
e1000_init_hw_80003es2lan(struct e1000_hw * hw)811 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
812 {
813 struct e1000_mac_info *mac = &hw->mac;
814 u32 reg_data;
815 s32 ret_val;
816 u16 kum_reg_data;
817 u16 i;
818
819 DEBUGFUNC("e1000_init_hw_80003es2lan");
820
821 e1000_initialize_hw_bits_80003es2lan(hw);
822
823 /* Initialize identification LED */
824 ret_val = mac->ops.id_led_init(hw);
825 /* An error is not fatal and we should not stop init due to this */
826 if (ret_val)
827 DEBUGOUT("Error initializing identification LED\n");
828
829 /* Disabling VLAN filtering */
830 DEBUGOUT("Initializing the IEEE VLAN\n");
831 mac->ops.clear_vfta(hw);
832
833 /* Setup the receive address. */
834 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
835
836 /* Zero out the Multicast HASH table */
837 DEBUGOUT("Zeroing the MTA\n");
838 for (i = 0; i < mac->mta_reg_count; i++)
839 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
840
841 /* Setup link and flow control */
842 ret_val = mac->ops.setup_link(hw);
843 if (ret_val)
844 return ret_val;
845
846 /* Disable IBIST slave mode (far-end loopback) */
847 ret_val =
848 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
849 &kum_reg_data);
850 if (!ret_val) {
851 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
852 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
853 E1000_KMRNCTRLSTA_INBAND_PARAM,
854 kum_reg_data);
855 if (ret_val)
856 DEBUGOUT("Error disabling far-end loopback\n");
857 } else
858 DEBUGOUT("Error disabling far-end loopback\n");
859
860 /* Set the transmit descriptor write-back policy */
861 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
862 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
863 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
864 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
865
866 /* ...for both queues. */
867 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
868 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
869 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
870 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
871
872 /* Enable retransmit on late collisions */
873 reg_data = E1000_READ_REG(hw, E1000_TCTL);
874 reg_data |= E1000_TCTL_RTLC;
875 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
876
877 /* Configure Gigabit Carry Extend Padding */
878 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);
879 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
880 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
881 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);
882
883 /* Configure Transmit Inter-Packet Gap */
884 reg_data = E1000_READ_REG(hw, E1000_TIPG);
885 reg_data &= ~E1000_TIPG_IPGT_MASK;
886 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
887 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
888
889 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
890 reg_data &= ~0x00100000;
891 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
892
893 /* default to true to enable the MDIC W/A */
894 hw->dev_spec._80003es2lan.mdic_wa_enable = true;
895
896 ret_val =
897 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
898 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
899 if (!ret_val) {
900 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
901 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
902 hw->dev_spec._80003es2lan.mdic_wa_enable = false;
903 }
904
905 /* Clear all of the statistics registers (clear on read). It is
906 * important that we do this after we have tried to establish link
907 * because the symbol error count will increment wildly if there
908 * is no link.
909 */
910 e1000_clear_hw_cntrs_80003es2lan(hw);
911
912 return ret_val;
913 }
914
915 /**
916 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
917 * @hw: pointer to the HW structure
918 *
919 * Initializes required hardware-dependent bits needed for normal operation.
920 **/
e1000_initialize_hw_bits_80003es2lan(struct e1000_hw * hw)921 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
922 {
923 u32 reg;
924
925 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
926
927 /* Transmit Descriptor Control 0 */
928 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
929 reg |= (1 << 22);
930 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
931
932 /* Transmit Descriptor Control 1 */
933 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
934 reg |= (1 << 22);
935 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
936
937 /* Transmit Arbitration Control 0 */
938 reg = E1000_READ_REG(hw, E1000_TARC(0));
939 reg &= ~(0xF << 27); /* 30:27 */
940 if (hw->phy.media_type != e1000_media_type_copper)
941 reg &= ~(1 << 20);
942 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
943
944 /* Transmit Arbitration Control 1 */
945 reg = E1000_READ_REG(hw, E1000_TARC(1));
946 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
947 reg &= ~(1 << 28);
948 else
949 reg |= (1 << 28);
950 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
951
952 /* Disable IPv6 extension header parsing because some malformed
953 * IPv6 headers can hang the Rx.
954 */
955 reg = E1000_READ_REG(hw, E1000_RFCTL);
956 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
957 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
958
959 return;
960 }
961
962 /**
963 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
964 * @hw: pointer to the HW structure
965 *
966 * Setup some GG82563 PHY registers for obtaining link
967 **/
e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw * hw)968 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
969 {
970 struct e1000_phy_info *phy = &hw->phy;
971 s32 ret_val;
972 u32 reg;
973 u16 data;
974
975 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
976
977 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
978 if (ret_val)
979 return ret_val;
980
981 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
982 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
983 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
984
985 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
986 if (ret_val)
987 return ret_val;
988
989 /* Options:
990 * MDI/MDI-X = 0 (default)
991 * 0 - Auto for all speeds
992 * 1 - MDI mode
993 * 2 - MDI-X mode
994 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
995 */
996 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
997 if (ret_val)
998 return ret_val;
999
1000 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1001
1002 switch (phy->mdix) {
1003 case 1:
1004 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1005 break;
1006 case 2:
1007 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1008 break;
1009 case 0:
1010 default:
1011 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1012 break;
1013 }
1014
1015 /* Options:
1016 * disable_polarity_correction = 0 (default)
1017 * Automatic Correction for Reversed Cable Polarity
1018 * 0 - Disabled
1019 * 1 - Enabled
1020 */
1021 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1022 if (phy->disable_polarity_correction)
1023 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1024
1025 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1026 if (ret_val)
1027 return ret_val;
1028
1029 /* SW Reset the PHY so all changes take effect */
1030 ret_val = hw->phy.ops.commit(hw);
1031 if (ret_val) {
1032 DEBUGOUT("Error Resetting the PHY\n");
1033 return ret_val;
1034 }
1035
1036 /* Bypass Rx and Tx FIFO's */
1037 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
1038 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1039 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1040 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1041 if (ret_val)
1042 return ret_val;
1043
1044 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
1045 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
1046 if (ret_val)
1047 return ret_val;
1048 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1049 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
1050 if (ret_val)
1051 return ret_val;
1052
1053 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1054 if (ret_val)
1055 return ret_val;
1056
1057 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1058 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1059 if (ret_val)
1060 return ret_val;
1061
1062 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1063 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1064 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1065
1066 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1067 if (ret_val)
1068 return ret_val;
1069
1070 /* Do not init these registers when the HW is in IAMT mode, since the
1071 * firmware will have already initialized them. We only initialize
1072 * them if the HW is not in IAMT mode.
1073 */
1074 if (!hw->mac.ops.check_mng_mode(hw)) {
1075 /* Enable Electrical Idle on the PHY */
1076 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1077 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1078 data);
1079 if (ret_val)
1080 return ret_val;
1081
1082 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1083 &data);
1084 if (ret_val)
1085 return ret_val;
1086
1087 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1088 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1089 data);
1090 if (ret_val)
1091 return ret_val;
1092 }
1093
1094 /* Workaround: Disable padding in Kumeran interface in the MAC
1095 * and in the PHY to avoid CRC errors.
1096 */
1097 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1098 if (ret_val)
1099 return ret_val;
1100
1101 data |= GG82563_ICR_DIS_PADDING;
1102 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1103 if (ret_val)
1104 return ret_val;
1105
1106 return E1000_SUCCESS;
1107 }
1108
1109 /**
1110 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1111 * @hw: pointer to the HW structure
1112 *
1113 * Essentially a wrapper for setting up all things "copper" related.
1114 * This is a function pointer entry point called by the mac module.
1115 **/
e1000_setup_copper_link_80003es2lan(struct e1000_hw * hw)1116 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1117 {
1118 u32 ctrl;
1119 s32 ret_val;
1120 u16 reg_data;
1121
1122 DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1123
1124 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1125 ctrl |= E1000_CTRL_SLU;
1126 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1127 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1128
1129 /* Set the mac to wait the maximum time between each
1130 * iteration and increase the max iterations when
1131 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1132 */
1133 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1134 0xFFFF);
1135 if (ret_val)
1136 return ret_val;
1137 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1138 ®_data);
1139 if (ret_val)
1140 return ret_val;
1141 reg_data |= 0x3F;
1142 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1143 reg_data);
1144 if (ret_val)
1145 return ret_val;
1146 ret_val =
1147 e1000_read_kmrn_reg_80003es2lan(hw,
1148 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1149 ®_data);
1150 if (ret_val)
1151 return ret_val;
1152 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1153 ret_val =
1154 e1000_write_kmrn_reg_80003es2lan(hw,
1155 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1156 reg_data);
1157 if (ret_val)
1158 return ret_val;
1159
1160 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1161 if (ret_val)
1162 return ret_val;
1163
1164 return e1000_setup_copper_link_generic(hw);
1165 }
1166
1167 /**
1168 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1169 * @hw: pointer to the HW structure
1170 *
1171 * Configure the KMRN interface by applying last minute quirks for
1172 * 10/100 operation.
1173 **/
e1000_cfg_on_link_up_80003es2lan(struct e1000_hw * hw)1174 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1175 {
1176 s32 ret_val = E1000_SUCCESS;
1177 u16 speed;
1178 u16 duplex;
1179
1180 DEBUGFUNC("e1000_configure_on_link_up");
1181
1182 if (hw->phy.media_type == e1000_media_type_copper) {
1183 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1184 &duplex);
1185 if (ret_val)
1186 return ret_val;
1187
1188 if (speed == SPEED_1000)
1189 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1190 else
1191 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1192 }
1193
1194 return ret_val;
1195 }
1196
1197 /**
1198 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1199 * @hw: pointer to the HW structure
1200 * @duplex: current duplex setting
1201 *
1202 * Configure the KMRN interface by applying last minute quirks for
1203 * 10/100 operation.
1204 **/
e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw * hw,u16 duplex)1205 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1206 {
1207 s32 ret_val;
1208 u32 tipg;
1209 u32 i = 0;
1210 u16 reg_data, reg_data2;
1211
1212 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1213
1214 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1215 ret_val =
1216 e1000_write_kmrn_reg_80003es2lan(hw,
1217 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1218 reg_data);
1219 if (ret_val)
1220 return ret_val;
1221
1222 /* Configure Transmit Inter-Packet Gap */
1223 tipg = E1000_READ_REG(hw, E1000_TIPG);
1224 tipg &= ~E1000_TIPG_IPGT_MASK;
1225 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1226 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1227
1228 do {
1229 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1230 ®_data);
1231 if (ret_val)
1232 return ret_val;
1233
1234 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1235 ®_data2);
1236 if (ret_val)
1237 return ret_val;
1238 i++;
1239 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1240
1241 if (duplex == HALF_DUPLEX)
1242 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1243 else
1244 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1245
1246 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1247 }
1248
1249 /**
1250 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1251 * @hw: pointer to the HW structure
1252 *
1253 * Configure the KMRN interface by applying last minute quirks for
1254 * gigabit operation.
1255 **/
e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw * hw)1256 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1257 {
1258 s32 ret_val;
1259 u16 reg_data, reg_data2;
1260 u32 tipg;
1261 u32 i = 0;
1262
1263 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1264
1265 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1266 ret_val =
1267 e1000_write_kmrn_reg_80003es2lan(hw,
1268 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1269 reg_data);
1270 if (ret_val)
1271 return ret_val;
1272
1273 /* Configure Transmit Inter-Packet Gap */
1274 tipg = E1000_READ_REG(hw, E1000_TIPG);
1275 tipg &= ~E1000_TIPG_IPGT_MASK;
1276 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1277 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1278
1279 do {
1280 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1281 ®_data);
1282 if (ret_val)
1283 return ret_val;
1284
1285 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1286 ®_data2);
1287 if (ret_val)
1288 return ret_val;
1289 i++;
1290 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1291
1292 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1293
1294 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1295 }
1296
1297 /**
1298 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1299 * @hw: pointer to the HW structure
1300 * @offset: register offset to be read
1301 * @data: pointer to the read data
1302 *
1303 * Acquire semaphore, then read the PHY register at offset
1304 * using the kumeran interface. The information retrieved is stored in data.
1305 * Release the semaphore before exiting.
1306 **/
e1000_read_kmrn_reg_80003es2lan(struct e1000_hw * hw,u32 offset,u16 * data)1307 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1308 u16 *data)
1309 {
1310 u32 kmrnctrlsta;
1311 s32 ret_val;
1312
1313 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1314
1315 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1316 if (ret_val)
1317 return ret_val;
1318
1319 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1320 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1321 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1322 E1000_WRITE_FLUSH(hw);
1323
1324 usec_delay(2);
1325
1326 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1327 *data = (u16)kmrnctrlsta;
1328
1329 e1000_release_mac_csr_80003es2lan(hw);
1330
1331 return ret_val;
1332 }
1333
1334 /**
1335 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1336 * @hw: pointer to the HW structure
1337 * @offset: register offset to write to
1338 * @data: data to write at register offset
1339 *
1340 * Acquire semaphore, then write the data to PHY register
1341 * at the offset using the kumeran interface. Release semaphore
1342 * before exiting.
1343 **/
e1000_write_kmrn_reg_80003es2lan(struct e1000_hw * hw,u32 offset,u16 data)1344 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1345 u16 data)
1346 {
1347 u32 kmrnctrlsta;
1348 s32 ret_val;
1349
1350 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1351
1352 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1353 if (ret_val)
1354 return ret_val;
1355
1356 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1357 E1000_KMRNCTRLSTA_OFFSET) | data;
1358 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1359 E1000_WRITE_FLUSH(hw);
1360
1361 usec_delay(2);
1362
1363 e1000_release_mac_csr_80003es2lan(hw);
1364
1365 return ret_val;
1366 }
1367
1368 /**
1369 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1370 * @hw: pointer to the HW structure
1371 **/
e1000_read_mac_addr_80003es2lan(struct e1000_hw * hw)1372 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1373 {
1374 s32 ret_val;
1375
1376 DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
1377
1378 /* If there's an alternate MAC address place it in RAR0
1379 * so that it will override the Si installed default perm
1380 * address.
1381 */
1382 ret_val = e1000_check_alt_mac_addr_generic(hw);
1383 if (ret_val)
1384 return ret_val;
1385
1386 return e1000_read_mac_addr_generic(hw);
1387 }
1388
1389 /**
1390 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1391 * @hw: pointer to the HW structure
1392 *
1393 * In the case of a PHY power down to save power, or to turn off link during a
1394 * driver unload, or wake on lan is not enabled, remove the link.
1395 **/
e1000_power_down_phy_copper_80003es2lan(struct e1000_hw * hw)1396 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1397 {
1398 /* If the management interface is not enabled, then power down */
1399 if (!(hw->mac.ops.check_mng_mode(hw) ||
1400 hw->phy.ops.check_reset_block(hw)))
1401 e1000_power_down_phy_copper(hw);
1402
1403 return;
1404 }
1405
1406 /**
1407 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1408 * @hw: pointer to the HW structure
1409 *
1410 * Clears the hardware counters by reading the counter registers.
1411 **/
e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw * hw)1412 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1413 {
1414 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1415
1416 e1000_clear_hw_cntrs_base_generic(hw);
1417
1418 E1000_READ_REG(hw, E1000_PRC64);
1419 E1000_READ_REG(hw, E1000_PRC127);
1420 E1000_READ_REG(hw, E1000_PRC255);
1421 E1000_READ_REG(hw, E1000_PRC511);
1422 E1000_READ_REG(hw, E1000_PRC1023);
1423 E1000_READ_REG(hw, E1000_PRC1522);
1424 E1000_READ_REG(hw, E1000_PTC64);
1425 E1000_READ_REG(hw, E1000_PTC127);
1426 E1000_READ_REG(hw, E1000_PTC255);
1427 E1000_READ_REG(hw, E1000_PTC511);
1428 E1000_READ_REG(hw, E1000_PTC1023);
1429 E1000_READ_REG(hw, E1000_PTC1522);
1430
1431 E1000_READ_REG(hw, E1000_ALGNERRC);
1432 E1000_READ_REG(hw, E1000_RXERRC);
1433 E1000_READ_REG(hw, E1000_TNCRS);
1434 E1000_READ_REG(hw, E1000_CEXTERR);
1435 E1000_READ_REG(hw, E1000_TSCTC);
1436 E1000_READ_REG(hw, E1000_TSCTFC);
1437
1438 E1000_READ_REG(hw, E1000_MGTPRC);
1439 E1000_READ_REG(hw, E1000_MGTPDC);
1440 E1000_READ_REG(hw, E1000_MGTPTC);
1441
1442 E1000_READ_REG(hw, E1000_IAC);
1443 E1000_READ_REG(hw, E1000_ICRXOC);
1444
1445 E1000_READ_REG(hw, E1000_ICRXPTC);
1446 E1000_READ_REG(hw, E1000_ICRXATC);
1447 E1000_READ_REG(hw, E1000_ICTXPTC);
1448 E1000_READ_REG(hw, E1000_ICTXATC);
1449 E1000_READ_REG(hw, E1000_ICTXQEC);
1450 E1000_READ_REG(hw, E1000_ICTXQMTC);
1451 E1000_READ_REG(hw, E1000_ICRXDMTC);
1452 }
1453