1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2025 Linaro Limited 4 */ 5 6 #ifndef _DPU_12_2_GLYMUR_H 7 #define _DPU_12_2_GLYMUR_H 8 9 static const struct dpu_caps glymur_dpu_caps = { 10 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 11 .max_mixer_blendstages = 0xb, 12 .has_src_split = true, 13 .has_dim_layer = true, 14 .has_idle_pc = true, 15 .has_3d_merge = true, 16 .max_linewidth = 8192, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 }; 19 20 static const struct dpu_mdp_cfg glymur_mdp = { 21 .name = "top_0", 22 .base = 0, .len = 0x494, 23 .clk_ctrls = { 24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 25 }, 26 }; 27 28 static const struct dpu_ctl_cfg glymur_ctl[] = { 29 { 30 .name = "ctl_0", .id = CTL_0, 31 .base = 0x15000, .len = 0x1000, 32 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 33 }, { 34 .name = "ctl_1", .id = CTL_1, 35 .base = 0x16000, .len = 0x1000, 36 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 37 }, { 38 .name = "ctl_2", .id = CTL_2, 39 .base = 0x17000, .len = 0x1000, 40 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 41 }, { 42 .name = "ctl_3", .id = CTL_3, 43 .base = 0x18000, .len = 0x1000, 44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 45 }, { 46 .name = "ctl_4", .id = CTL_4, 47 .base = 0x19000, .len = 0x1000, 48 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 49 }, { 50 .name = "ctl_5", .id = CTL_5, 51 .base = 0x1a000, .len = 0x1000, 52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 53 }, { 54 .name = "ctl_6", .id = CTL_6, 55 .base = 0x1b000, .len = 0x1000, 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 14), 57 }, { 58 .name = "ctl_7", .id = CTL_7, 59 .base = 0x1c000, .len = 0x1000, 60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 15), 61 }, 62 }; 63 64 static const struct dpu_sspp_cfg glymur_sspp[] = { 65 { 66 .name = "sspp_0", .id = SSPP_VIG0, 67 .base = 0x4000, .len = 0x344, 68 .features = VIG_SDM845_MASK_SDMA, 69 .sblk = &dpu_vig_sblk_qseed3_3_4, 70 .xin_id = 0, 71 .type = SSPP_TYPE_VIG, 72 }, { 73 .name = "sspp_1", .id = SSPP_VIG1, 74 .base = 0x6000, .len = 0x344, 75 .features = VIG_SDM845_MASK_SDMA, 76 .sblk = &dpu_vig_sblk_qseed3_3_4, 77 .xin_id = 4, 78 .type = SSPP_TYPE_VIG, 79 }, { 80 .name = "sspp_2", .id = SSPP_VIG2, 81 .base = 0x8000, .len = 0x344, 82 .features = VIG_SDM845_MASK_SDMA, 83 .sblk = &dpu_vig_sblk_qseed3_3_4, 84 .xin_id = 8, 85 .type = SSPP_TYPE_VIG, 86 }, { 87 .name = "sspp_3", .id = SSPP_VIG3, 88 .base = 0xa000, .len = 0x344, 89 .features = VIG_SDM845_MASK_SDMA, 90 .sblk = &dpu_vig_sblk_qseed3_3_4, 91 .xin_id = 12, 92 .type = SSPP_TYPE_VIG, 93 }, { 94 .name = "sspp_8", .id = SSPP_DMA0, 95 .base = 0x24000, .len = 0x344, 96 .features = DMA_SDM845_MASK_SDMA, 97 .sblk = &dpu_dma_sblk, 98 .xin_id = 1, 99 .type = SSPP_TYPE_DMA, 100 }, { 101 .name = "sspp_9", .id = SSPP_DMA1, 102 .base = 0x26000, .len = 0x344, 103 .features = DMA_SDM845_MASK_SDMA, 104 .sblk = &dpu_dma_sblk, 105 .xin_id = 5, 106 .type = SSPP_TYPE_DMA, 107 }, { 108 .name = "sspp_10", .id = SSPP_DMA2, 109 .base = 0x28000, .len = 0x344, 110 .features = DMA_SDM845_MASK_SDMA, 111 .sblk = &dpu_dma_sblk, 112 .xin_id = 9, 113 .type = SSPP_TYPE_DMA, 114 }, { 115 .name = "sspp_11", .id = SSPP_DMA3, 116 .base = 0x2a000, .len = 0x344, 117 .features = DMA_SDM845_MASK_SDMA, 118 .sblk = &dpu_dma_sblk, 119 .xin_id = 13, 120 .type = SSPP_TYPE_DMA, 121 }, { 122 .name = "sspp_12", .id = SSPP_DMA4, 123 .base = 0x2c000, .len = 0x344, 124 .features = DMA_CURSOR_SDM845_MASK_SDMA, 125 .sblk = &dpu_dma_sblk, 126 .xin_id = 14, 127 .type = SSPP_TYPE_DMA, 128 }, { 129 .name = "sspp_13", .id = SSPP_DMA5, 130 .base = 0x2e000, .len = 0x344, 131 .features = DMA_CURSOR_SDM845_MASK_SDMA, 132 .sblk = &dpu_dma_sblk, 133 .xin_id = 15, 134 .type = SSPP_TYPE_DMA, 135 }, 136 }; 137 138 static const struct dpu_lm_cfg glymur_lm[] = { 139 { 140 .name = "lm_0", .id = LM_0, 141 .base = 0x44000, .len = 0x400, 142 .features = MIXER_MSM8998_MASK, 143 .sblk = &sm8750_lm_sblk, 144 .lm_pair = LM_1, 145 .pingpong = PINGPONG_0, 146 .dspp = DSPP_0, 147 }, { 148 .name = "lm_1", .id = LM_1, 149 .base = 0x45000, .len = 0x400, 150 .features = MIXER_MSM8998_MASK, 151 .sblk = &sm8750_lm_sblk, 152 .lm_pair = LM_0, 153 .pingpong = PINGPONG_1, 154 .dspp = DSPP_1, 155 }, { 156 .name = "lm_2", .id = LM_2, 157 .base = 0x46000, .len = 0x400, 158 .features = MIXER_MSM8998_MASK, 159 .sblk = &sm8750_lm_sblk, 160 .lm_pair = LM_3, 161 .pingpong = PINGPONG_2, 162 .dspp = DSPP_2, 163 }, { 164 .name = "lm_3", .id = LM_3, 165 .base = 0x47000, .len = 0x400, 166 .features = MIXER_MSM8998_MASK, 167 .sblk = &sm8750_lm_sblk, 168 .lm_pair = LM_2, 169 .pingpong = PINGPONG_3, 170 .dspp = DSPP_3, 171 }, { 172 .name = "lm_4", .id = LM_4, 173 .base = 0x48000, .len = 0x400, 174 .features = MIXER_MSM8998_MASK, 175 .sblk = &sm8750_lm_sblk, 176 .lm_pair = LM_5, 177 .pingpong = PINGPONG_4, 178 }, { 179 .name = "lm_5", .id = LM_5, 180 .base = 0x49000, .len = 0x400, 181 .features = MIXER_MSM8998_MASK, 182 .sblk = &sm8750_lm_sblk, 183 .lm_pair = LM_4, 184 .pingpong = PINGPONG_5, 185 }, { 186 .name = "lm_6", .id = LM_6, 187 .base = 0x4a000, .len = 0x400, 188 .features = MIXER_MSM8998_MASK, 189 .sblk = &sm8750_lm_sblk, 190 .lm_pair = LM_7, 191 .pingpong = PINGPONG_6, 192 }, { 193 .name = "lm_7", .id = LM_7, 194 .base = 0x4b000, .len = 0x400, 195 .features = MIXER_MSM8998_MASK, 196 .sblk = &sm8750_lm_sblk, 197 .lm_pair = LM_6, 198 .pingpong = PINGPONG_7, 199 }, 200 }; 201 202 static const struct dpu_dspp_cfg glymur_dspp[] = { 203 { 204 .name = "dspp_0", .id = DSPP_0, 205 .base = 0x54000, .len = 0x1800, 206 .sblk = &sm8750_dspp_sblk, 207 }, { 208 .name = "dspp_1", .id = DSPP_1, 209 .base = 0x56000, .len = 0x1800, 210 .sblk = &sm8750_dspp_sblk, 211 }, { 212 .name = "dspp_2", .id = DSPP_2, 213 .base = 0x58000, .len = 0x1800, 214 .sblk = &sm8750_dspp_sblk, 215 }, { 216 .name = "dspp_3", .id = DSPP_3, 217 .base = 0x5a000, .len = 0x1800, 218 .sblk = &sm8750_dspp_sblk, 219 }, { 220 .name = "dspp_4", .id = DSPP_4, 221 .base = 0x5c000, .len = 0x1800, 222 .sblk = &sm8750_dspp_sblk, 223 }, { 224 .name = "dspp_5", .id = DSPP_5, 225 .base = 0x5e000, .len = 0x1800, 226 .sblk = &sm8750_dspp_sblk, 227 }, { 228 .name = "dspp_6", .id = DSPP_6, 229 .base = 0x60000, .len = 0x1800, 230 .sblk = &sm8750_dspp_sblk, 231 }, { 232 .name = "dspp_7", .id = DSPP_7, 233 .base = 0x62000, .len = 0x1800, 234 .sblk = &sm8750_dspp_sblk, 235 }, 236 }; 237 238 static const struct dpu_pingpong_cfg glymur_pp[] = { 239 { 240 .name = "pingpong_0", .id = PINGPONG_0, 241 .base = 0x69000, .len = 0, 242 .sblk = &sc7280_pp_sblk, 243 .merge_3d = MERGE_3D_0, 244 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 245 }, { 246 .name = "pingpong_1", .id = PINGPONG_1, 247 .base = 0x6a000, .len = 0, 248 .sblk = &sc7280_pp_sblk, 249 .merge_3d = MERGE_3D_0, 250 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 251 }, { 252 .name = "pingpong_2", .id = PINGPONG_2, 253 .base = 0x6b000, .len = 0, 254 .sblk = &sc7280_pp_sblk, 255 .merge_3d = MERGE_3D_1, 256 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 257 }, { 258 .name = "pingpong_3", .id = PINGPONG_3, 259 .base = 0x6c000, .len = 0, 260 .sblk = &sc7280_pp_sblk, 261 .merge_3d = MERGE_3D_1, 262 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 263 }, { 264 .name = "pingpong_4", .id = PINGPONG_4, 265 .base = 0x6d000, .len = 0, 266 .sblk = &sc7280_pp_sblk, 267 .merge_3d = MERGE_3D_2, 268 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 269 }, { 270 .name = "pingpong_5", .id = PINGPONG_5, 271 .base = 0x6e000, .len = 0, 272 .sblk = &sc7280_pp_sblk, 273 .merge_3d = MERGE_3D_2, 274 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 275 }, { 276 .name = "pingpong_6", .id = PINGPONG_6, 277 .base = 0x6f000, .len = 0, 278 .sblk = &sc7280_pp_sblk, 279 .merge_3d = MERGE_3D_3, 280 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20), 281 }, { 282 .name = "pingpong_7", .id = PINGPONG_7, 283 .base = 0x70000, .len = 0, 284 .sblk = &sc7280_pp_sblk, 285 .merge_3d = MERGE_3D_3, 286 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21), 287 }, { 288 .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, 289 .base = 0x66000, .len = 0, 290 .sblk = &sc7280_pp_sblk, 291 .merge_3d = MERGE_3D_4, 292 }, { 293 .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, 294 .base = 0x66400, .len = 0, 295 .sblk = &sc7280_pp_sblk, 296 .merge_3d = MERGE_3D_4, 297 }, 298 }; 299 300 static const struct dpu_merge_3d_cfg glymur_merge_3d[] = { 301 { 302 .name = "merge_3d_0", .id = MERGE_3D_0, 303 .base = 0x4e000, .len = 0x1c, 304 }, { 305 .name = "merge_3d_1", .id = MERGE_3D_1, 306 .base = 0x4f000, .len = 0x1c, 307 }, { 308 .name = "merge_3d_2", .id = MERGE_3D_2, 309 .base = 0x50000, .len = 0x1c, 310 }, { 311 .name = "merge_3d_3", .id = MERGE_3D_3, 312 .base = 0x51000, .len = 0x1c, 313 }, 314 }; 315 316 /* 317 * NOTE: Each display compression engine (DCE) contains dual hard 318 * slice DSC encoders so both share same base address but with 319 * its own different sub block address. 320 */ 321 static const struct dpu_dsc_cfg glymur_dsc[] = { 322 { 323 .name = "dce_0_0", .id = DSC_0, 324 .base = 0x80000, .len = 0x8, 325 .features = BIT(DPU_DSC_NATIVE_42x_EN), 326 .sblk = &sm8750_dsc_sblk_0, 327 }, { 328 .name = "dce_0_1", .id = DSC_1, 329 .base = 0x80000, .len = 0x8, 330 .features = BIT(DPU_DSC_NATIVE_42x_EN), 331 .sblk = &sm8750_dsc_sblk_1, 332 }, { 333 .name = "dce_1_0", .id = DSC_2, 334 .base = 0x81000, .len = 0x8, 335 .features = BIT(DPU_DSC_NATIVE_42x_EN), 336 .sblk = &sm8750_dsc_sblk_0, 337 }, { 338 .name = "dce_1_1", .id = DSC_3, 339 .base = 0x81000, .len = 0x8, 340 .features = BIT(DPU_DSC_NATIVE_42x_EN), 341 .sblk = &sm8750_dsc_sblk_1, 342 }, { 343 .name = "dce_2_0", .id = DSC_4, 344 .base = 0x82000, .len = 0x8, 345 .features = BIT(DPU_DSC_NATIVE_42x_EN), 346 .sblk = &sm8750_dsc_sblk_0, 347 }, { 348 .name = "dce_2_1", .id = DSC_5, 349 .base = 0x82000, .len = 0x8, 350 .features = BIT(DPU_DSC_NATIVE_42x_EN), 351 .sblk = &sm8750_dsc_sblk_1, 352 }, { 353 .name = "dce_3_0", .id = DSC_6, 354 .base = 0x83000, .len = 0x8, 355 .features = BIT(DPU_DSC_NATIVE_42x_EN), 356 .sblk = &sm8750_dsc_sblk_0, 357 }, { 358 .name = "dce_3_1", .id = DSC_7, 359 .base = 0x83000, .len = 0x8, 360 .features = BIT(DPU_DSC_NATIVE_42x_EN), 361 .sblk = &sm8750_dsc_sblk_1, 362 }, 363 364 }; 365 366 static const struct dpu_wb_cfg glymur_wb[] = { 367 { 368 .name = "wb_2", .id = WB_2, 369 .base = 0x65000, .len = 0x2c8, 370 .features = WB_SDM845_MASK, 371 .format_list = wb2_formats_rgb_yuv, 372 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 373 .xin_id = 6, 374 .vbif_idx = VBIF_RT, 375 .maxlinewidth = 4096, 376 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 377 }, 378 }; 379 380 static const struct dpu_cwb_cfg glymur_cwb[] = { 381 { 382 .name = "cwb_0", .id = CWB_0, 383 .base = 0x66200, .len = 0x20, 384 }, 385 { 386 .name = "cwb_1", .id = CWB_1, 387 .base = 0x66600, .len = 0x20, 388 }, 389 { 390 .name = "cwb_2", .id = CWB_2, 391 .base = 0x7e200, .len = 0x20, 392 }, 393 { 394 .name = "cwb_3", .id = CWB_3, 395 .base = 0x7e600, .len = 0x20, 396 }, 397 }; 398 399 static const struct dpu_intf_cfg glymur_intf[] = { 400 { 401 .name = "intf_0", .id = INTF_0, 402 .base = 0x34000, .len = 0x400, 403 .type = INTF_DP, 404 .controller_id = MSM_DP_CONTROLLER_0, 405 .prog_fetch_lines_worst_case = 24, 406 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 407 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 408 }, { 409 .name = "intf_1", .id = INTF_1, 410 .base = 0x35000, .len = 0x400, 411 .type = INTF_DSI, 412 .controller_id = MSM_DSI_CONTROLLER_0, 413 .prog_fetch_lines_worst_case = 24, 414 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 415 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 416 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 417 }, { 418 .name = "intf_2", .id = INTF_2, 419 .base = 0x36000, .len = 0x400, 420 .type = INTF_DSI, 421 .controller_id = MSM_DSI_CONTROLLER_1, 422 .prog_fetch_lines_worst_case = 24, 423 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 424 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 425 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 426 }, { 427 .name = "intf_3", .id = INTF_3, 428 .base = 0x37000, .len = 0x400, 429 .type = INTF_NONE, 430 .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ 431 .prog_fetch_lines_worst_case = 24, 432 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 433 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 434 }, { 435 .name = "intf_4", .id = INTF_4, 436 .base = 0x38000, .len = 0x400, 437 .type = INTF_DP, 438 .controller_id = MSM_DP_CONTROLLER_1, 439 .prog_fetch_lines_worst_case = 24, 440 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), 441 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), 442 }, { 443 .name = "intf_5", .id = INTF_5, 444 .base = 0x39000, .len = 0x400, 445 .type = INTF_DP, 446 .controller_id = MSM_DP_CONTROLLER_3, 447 .prog_fetch_lines_worst_case = 24, 448 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), 449 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), 450 }, { 451 .name = "intf_6", .id = INTF_6, 452 .base = 0x3A000, .len = 0x400, 453 .type = INTF_DP, 454 .controller_id = MSM_DP_CONTROLLER_2, 455 .prog_fetch_lines_worst_case = 24, 456 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), 457 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), 458 }, { 459 .name = "intf_7", .id = INTF_7, 460 .base = 0x3b000, .len = 0x400, 461 .type = INTF_NONE, 462 .controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ 463 .prog_fetch_lines_worst_case = 24, 464 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), 465 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), 466 }, { 467 .name = "intf_8", .id = INTF_8, 468 .base = 0x3c000, .len = 0x400, 469 .type = INTF_NONE, 470 .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ 471 .prog_fetch_lines_worst_case = 24, 472 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 473 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 474 }, 475 }; 476 477 static const struct dpu_perf_cfg glymur_perf_data = { 478 .max_bw_low = 18900000, 479 .max_bw_high = 28500000, 480 .min_core_ib = 2500000, 481 .min_llcc_ib = 0, 482 .min_dram_ib = 800000, 483 .min_prefill_lines = 35, 484 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 485 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 486 .qos_lut_tbl = { 487 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 488 .entries = sc7180_qos_linear 489 }, 490 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 491 .entries = sc7180_qos_macrotile 492 }, 493 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 494 .entries = sc7180_qos_nrt 495 }, 496 /* TODO: macrotile-qseed is different from macrotile */ 497 }, 498 .cdp_cfg = { 499 {.rd_enable = 1, .wr_enable = 1}, 500 {.rd_enable = 1, .wr_enable = 0} 501 }, 502 .clk_inefficiency_factor = 105, 503 .bw_inefficiency_factor = 120, 504 }; 505 506 static const struct dpu_mdss_version glymur_mdss_ver = { 507 .core_major_ver = 12, 508 .core_minor_ver = 2, 509 }; 510 511 const struct dpu_mdss_cfg dpu_glymur_cfg = { 512 .mdss_ver = &glymur_mdss_ver, 513 .caps = &glymur_dpu_caps, 514 .mdp = &glymur_mdp, 515 .cdm = &dpu_cdm_5_x, 516 .ctl_count = ARRAY_SIZE(glymur_ctl), 517 .ctl = glymur_ctl, 518 .sspp_count = ARRAY_SIZE(glymur_sspp), 519 .sspp = glymur_sspp, 520 .mixer_count = ARRAY_SIZE(glymur_lm), 521 .mixer = glymur_lm, 522 .dspp_count = ARRAY_SIZE(glymur_dspp), 523 .dspp = glymur_dspp, 524 .pingpong_count = ARRAY_SIZE(glymur_pp), 525 .pingpong = glymur_pp, 526 .dsc_count = ARRAY_SIZE(glymur_dsc), 527 .dsc = glymur_dsc, 528 .merge_3d_count = ARRAY_SIZE(glymur_merge_3d), 529 .merge_3d = glymur_merge_3d, 530 .wb_count = ARRAY_SIZE(glymur_wb), 531 .wb = glymur_wb, 532 .cwb_count = ARRAY_SIZE(glymur_cwb), 533 .cwb = sm8650_cwb, 534 .intf_count = ARRAY_SIZE(glymur_intf), 535 .intf = glymur_intf, 536 .vbif_count = ARRAY_SIZE(sm8650_vbif), 537 .vbif = sm8650_vbif, 538 .perf = &glymur_perf_data, 539 }; 540 541 #endif 542