1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * This header provides constants for J721E WIZ. 4 */ 5 6 #ifndef _DT_BINDINGS_J721E_WIZ 7 #define _DT_BINDINGS_J721E_WIZ 8 9 #define SERDES0_LANE0_QSGMII_LANE1 0x0 10 #define SERDES0_LANE0_PCIE0_LANE0 0x1 11 #define SERDES0_LANE0_USB3_0_SWAP 0x2 12 13 #define SERDES0_LANE1_QSGMII_LANE2 0x0 14 #define SERDES0_LANE1_PCIE0_LANE1 0x1 15 #define SERDES0_LANE1_USB3_0 0x2 16 17 #define SERDES1_LANE0_QSGMII_LANE3 0x0 18 #define SERDES1_LANE0_PCIE1_LANE0 0x1 19 #define SERDES1_LANE0_USB3_1_SWAP 0x2 20 #define SERDES1_LANE0_SGMII_LANE0 0x3 21 22 #define SERDES1_LANE1_QSGMII_LANE4 0x0 23 #define SERDES1_LANE1_PCIE1_LANE1 0x1 24 #define SERDES1_LANE1_USB3_1 0x2 25 #define SERDES1_LANE1_SGMII_LANE1 0x3 26 27 #define SERDES2_LANE0_PCIE2_LANE0 0x1 28 #define SERDES2_LANE0_SGMII_LANE0 0x3 29 #define SERDES2_LANE0_USB3_1_SWAP 0x2 30 31 #define SERDES2_LANE1_PCIE2_LANE1 0x1 32 #define SERDES2_LANE1_USB3_1 0x2 33 #define SERDES2_LANE1_SGMII_LANE1 0x3 34 35 #define SERDES3_LANE0_PCIE3_LANE0 0x1 36 #define SERDES3_LANE0_USB3_0_SWAP 0x2 37 38 #define SERDES3_LANE1_PCIE3_LANE1 0x1 39 #define SERDES3_LANE1_USB3_0 0x2 40 41 #define SERDES4_LANE0_EDP_LANE0 0x0 42 #define SERDES4_LANE0_QSGMII_LANE5 0x2 43 44 #define SERDES4_LANE1_EDP_LANE1 0x0 45 #define SERDES4_LANE1_QSGMII_LANE6 0x2 46 47 #define SERDES4_LANE2_EDP_LANE2 0x0 48 #define SERDES4_LANE2_QSGMII_LANE7 0x2 49 50 #define SERDES4_LANE3_EDP_LANE3 0x0 51 #define SERDES4_LANE3_QSGMII_LANE8 0x2 52 53 #endif /* _DT_BINDINGS_J721E_WIZ */ 54