1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2024 Collabora Ltd.
5 *
6 * Author: Algea Cao <algea.cao@rock-chips.com>
7 * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
8 */
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/rational.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23
24 #define GRF_HDPTX_CON0 0x00
25 #define HDPTX_I_PLL_EN BIT(7)
26 #define HDPTX_I_BIAS_EN BIT(6)
27 #define HDPTX_I_BGR_EN BIT(5)
28 #define HDPTX_MODE_SEL BIT(0)
29 #define GRF_HDPTX_STATUS 0x80
30 #define HDPTX_O_PLL_LOCK_DONE BIT(3)
31 #define HDPTX_O_PHY_CLK_RDY BIT(2)
32 #define HDPTX_O_PHY_RDY BIT(1)
33 #define HDPTX_O_SB_RDY BIT(0)
34
35 #define HDTPX_REG(_n, _min, _max) \
36 ( \
37 BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \
38 BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \
39 ((0x##_n) * 4) \
40 )
41
42 #define CMN_REG(n) HDTPX_REG(n, 0000, 00a7)
43 #define SB_REG(n) HDTPX_REG(n, 0100, 0129)
44 #define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229)
45 #define LANE_REG(n) HDTPX_REG(n, 0300, 062d)
46
47 /* CMN_REG(0008) */
48 #define OVRD_LCPLL_EN_MASK BIT(7)
49 #define LCPLL_EN_MASK BIT(6)
50 #define LCPLL_LCVCO_MODE_EN_MASK BIT(4)
51 /* CMN_REG(001e) */
52 #define LCPLL_PI_EN_MASK BIT(5)
53 #define LCPLL_100M_CLK_EN_MASK BIT(0)
54 /* CMN_REG(0025) */
55 #define LCPLL_PMS_IQDIV_RSTN_MASK BIT(4)
56 /* CMN_REG(0028) */
57 #define LCPLL_SDC_FRAC_EN_MASK BIT(2)
58 #define LCPLL_SDC_FRAC_RSTN_MASK BIT(0)
59 /* CMN_REG(002d) */
60 #define LCPLL_SDC_N_MASK GENMASK(3, 1)
61 /* CMN_REG(002e) */
62 #define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0)
63 /* CMN_REG(002f) */
64 #define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2)
65 #define LCPLL_SDC_NDIV_RSTN_MASK BIT(0)
66 /* CMN_REG(003c) */
67 #define ANA_LCPLL_RESERVED7_MASK BIT(7)
68 /* CMN_REG(003d) */
69 #define OVRD_ROPLL_EN_MASK BIT(7)
70 #define ROPLL_EN_MASK BIT(6)
71 #define ROPLL_LCVCO_EN_MASK BIT(4)
72 /* CMN_REG(0046) */
73 #define ROPLL_ANA_CPP_CTRL_COARSE_MASK GENMASK(7, 4)
74 #define ROPLL_ANA_CPP_CTRL_FINE_MASK GENMASK(3, 0)
75 /* CMN_REG(0047) */
76 #define ROPLL_ANA_LPF_C_SEL_COARSE_MASK GENMASK(5, 3)
77 #define ROPLL_ANA_LPF_C_SEL_FINE_MASK GENMASK(2, 0)
78 /* CMN_REG(004e) */
79 #define ROPLL_PI_EN_MASK BIT(5)
80 /* CMN_REG(0051) */
81 #define ROPLL_PMS_MDIV_MASK GENMASK(7, 0)
82 /* CMN_REG(0055) */
83 #define ROPLL_PMS_MDIV_AFC_MASK GENMASK(7, 0)
84 /* CMN_REG(0059) */
85 #define ANA_ROPLL_PMS_PDIV_MASK GENMASK(7, 4)
86 #define ANA_ROPLL_PMS_REFDIV_MASK GENMASK(3, 0)
87 /* CMN_REG(005a) */
88 #define ROPLL_PMS_SDIV_RBR_MASK GENMASK(7, 4)
89 #define ROPLL_PMS_SDIV_HBR_MASK GENMASK(3, 0)
90 /* CMN_REG(005b) */
91 #define ROPLL_PMS_SDIV_HBR2_MASK GENMASK(7, 4)
92 /* CMN_REG(005c) */
93 #define ROPLL_PMS_IQDIV_RSTN_MASK BIT(5)
94 /* CMN_REG(005e) */
95 #define ROPLL_SDM_EN_MASK BIT(6)
96 #define OVRD_ROPLL_SDM_RSTN_MASK BIT(5)
97 #define ROPLL_SDM_RSTN_MASK BIT(4)
98 #define ROPLL_SDC_FRAC_EN_RBR_MASK BIT(3)
99 #define ROPLL_SDC_FRAC_EN_HBR_MASK BIT(2)
100 #define ROPLL_SDC_FRAC_EN_HBR2_MASK BIT(1)
101 #define ROPLL_SDM_FRAC_EN_HBR3_MASK BIT(0)
102 /* CMN_REG(005f) */
103 #define OVRD_ROPLL_SDC_RSTN_MASK BIT(5)
104 #define ROPLL_SDC_RSTN_MASK BIT(4)
105 /* CMN_REG(0060) */
106 #define ROPLL_SDM_DENOMINATOR_MASK GENMASK(7, 0)
107 /* CMN_REG(0064) */
108 #define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3)
109 #define ROPLL_SDM_NUM_SIGN_HBR_MASK BIT(2)
110 #define ROPLL_SDM_NUM_SIGN_HBR2_MASK BIT(1)
111 /* CMN_REG(0065) */
112 #define ROPLL_SDM_NUM_MASK GENMASK(7, 0)
113 /* CMN_REG(0069) */
114 #define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0)
115 /* CMN_REG(006a) */
116 #define ROPLL_SDC_N_HBR_MASK GENMASK(5, 3)
117 #define ROPLL_SDC_N_HBR2_MASK GENMASK(2, 0)
118 /* CMN_REG(006b) */
119 #define ROPLL_SDC_N_HBR3_MASK GENMASK(3, 1)
120 /* CMN_REG(006c) */
121 #define ROPLL_SDC_NUM_MASK GENMASK(5, 0)
122 /* cmn_reg0070 */
123 #define ROPLL_SDC_DENO_MASK GENMASK(5, 0)
124 /* CMN_REG(0074) */
125 #define OVRD_ROPLL_SDC_NDIV_RSTN_MASK BIT(3)
126 #define ROPLL_SDC_NDIV_RSTN_MASK BIT(2)
127 #define OVRD_ROPLL_SSC_EN_MASK BIT(1)
128 #define ROPLL_SSC_EN_MASK BIT(0)
129 /* CMN_REG(0075) */
130 #define ANA_ROPLL_SSC_FM_DEVIATION_MASK GENMASK(5, 0)
131 /* CMN_REG(0076) */
132 #define ANA_ROPLL_SSC_FM_FREQ_MASK GENMASK(6, 2)
133 /* CMN_REG(0077) */
134 #define ANA_ROPLL_SSC_CLK_DIV_SEL_MASK GENMASK(6, 3)
135 /* CMN_REG(0081) */
136 #define OVRD_PLL_CD_CLK_EN_MASK BIT(8)
137 #define ANA_PLL_CD_TX_SER_RATE_SEL_MASK BIT(3)
138 #define ANA_PLL_CD_HSCLK_WEST_EN_MASK BIT(1)
139 #define ANA_PLL_CD_HSCLK_EAST_EN_MASK BIT(0)
140 /* CMN_REG(0082) */
141 #define ANA_PLL_CD_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
142 /* CMN_REG(0083) */
143 #define ANA_PLL_CD_VREG_ICTRL_MASK GENMASK(6, 5)
144 /* CMN_REG(0084) */
145 #define PLL_LCRO_CLK_SEL_MASK BIT(5)
146 /* CMN_REG(0085) */
147 #define ANA_PLL_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0)
148 /* CMN_REG(0086) */
149 #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4)
150 #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1)
151 #define PLL_PCG_CLK_EN_MASK BIT(0)
152 /* CMN_REG(0087) */
153 #define ANA_PLL_FRL_MODE_EN_MASK BIT(3)
154 #define ANA_PLL_TX_HS_CLK_EN_MASK BIT(2)
155 /* CMN_REG(0089) */
156 #define LCPLL_ALONE_MODE_MASK BIT(1)
157 /* CMN_REG(0095) */
158 #define DP_TX_LINK_BW_MASK GENMASK(1, 0)
159 /* CMN_REG(0097) */
160 #define DIG_CLK_SEL_MASK BIT(1)
161 #define LCPLL_REF BIT(1)
162 #define ROPLL_REF 0
163 /* CMN_REG(0099) */
164 #define SSC_EN_MASK GENMASK(7, 6)
165 #define CMN_ROPLL_ALONE_MODE_MASK BIT(2)
166 #define ROPLL_ALONE_MODE BIT(2)
167 /* CMN_REG(009a) */
168 #define HS_SPEED_SEL_MASK BIT(0)
169 #define DIV_10_CLOCK BIT(0)
170 /* CMN_REG(009b) */
171 #define LS_SPEED_SEL_MASK BIT(4)
172 #define LINK_SYMBOL_CLOCK BIT(4)
173 #define LINK_SYMBOL_CLOCK1_2 0
174
175 /* SB_REG(0102) */
176 #define OVRD_SB_RXTERM_EN_MASK BIT(5)
177 #define SB_RXTERM_EN_MASK BIT(4)
178 #define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0)
179 /* SB_REG(0103) */
180 #define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3)
181 #define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1)
182 #define SB_RX_RESCAL_DONE_MASK BIT(0)
183 /* SB_REG(0104) */
184 #define OVRD_SB_EN_MASK BIT(5)
185 #define SB_EN_MASK BIT(4)
186 #define OVRD_SB_AUX_EN_MASK BIT(1)
187 #define SB_AUX_EN_MASK BIT(0)
188 /* SB_REG(0105) */
189 #define OVRD_SB_EARC_CMDC_EN_MASK BIT(6)
190 #define SB_EARC_CMDC_EN_MASK BIT(5)
191 #define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0)
192 /* SB_REG(0106) */
193 #define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4)
194 /* SB_REG(0109) */
195 #define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0)
196 /* SB_REG(010d) */
197 #define ANA_SB_DMRX_LPBK_DATA_MASK BIT(4)
198 /* SB_REG(010f) */
199 #define OVRD_SB_VREG_EN_MASK BIT(7)
200 #define SB_VREG_EN_MASK BIT(6)
201 #define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5)
202 #define SB_VREG_LPF_BYPASS_MASK BIT(4)
203 #define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
204 /* SB_REG(0110) */
205 #define ANA_SB_VREG_OUT_SEL_MASK BIT(1)
206 #define ANA_SB_VREG_REF_SEL_MASK BIT(0)
207 /* SB_REG(0113) */
208 #define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4)
209 #define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0)
210 /* SB_REG(0114) */
211 #define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3)
212 #define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0)
213 /* SB_REG(0115) */
214 #define SB_READY_DELAY_TIME_MASK GENMASK(5, 3)
215 #define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0)
216 /* SB_REG(0116) */
217 #define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4)
218 /* SB_REG(0117) */
219 #define FAST_PULSE_TIME_MASK GENMASK(3, 0)
220 /* SB_REG(0118) */
221 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK GENMASK(7, 0)
222 /* SB_REG(011a) */
223 #define SB_TG_CNT_RUN_NO_7_0_MASK GENMASK(7, 0)
224 /* SB_REG(011b) */
225 #define SB_EARC_SIG_DET_BYPASS_MASK BIT(4)
226 #define SB_AFC_TOL_MASK GENMASK(3, 0)
227 /* SB_REG(011c) */
228 #define SB_AFC_STB_NUM_MASK GENMASK(3, 0)
229 /* SB_REG(011d) */
230 #define SB_TG_OSC_CNT_MIN_MASK GENMASK(7, 0)
231 /* SB_REG(011e) */
232 #define SB_TG_OSC_CNT_MAX_MASK GENMASK(7, 0)
233 /* SB_REG(011f) */
234 #define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2)
235 #define SB_RCAL_RSTN_MASK BIT(1)
236 /* SB_REG(0120) */
237 #define SB_AUX_EN_IN_MASK BIT(7)
238 #define SB_EARC_EN_MASK BIT(1)
239 #define SB_EARC_AFC_EN_MASK BIT(2)
240 /* SB_REG(0123) */
241 #define OVRD_SB_READY_MASK BIT(5)
242 #define SB_READY_MASK BIT(4)
243
244 /* LNTOP_REG(0200) */
245 #define PROTOCOL_SEL_MASK BIT(2)
246 #define HDMI_MODE BIT(2)
247 #define HDMI_TMDS_FRL_SEL BIT(1)
248 /* LNTOP_REG(0206) */
249 #define DATA_BUS_WIDTH_MASK GENMASK(2, 1)
250 #define DATA_BUS_WIDTH_SEL_MASK BIT(0)
251 #define DATA_BUS_36_40 BIT(0)
252 /* LNTOP_REG(0207) */
253 #define LANE_EN_MASK 0xf
254 #define ALL_LANE_EN 0xf
255
256 /* LANE_REG(0301) */
257 #define OVRD_LN_TX_DRV_EI_EN_MASK BIT(7)
258 #define LN_TX_DRV_EI_EN_MASK BIT(6)
259 /* LANE_REG(0303) */
260 #define OVRD_LN_TX_DRV_LVL_CTRL_MASK BIT(5)
261 #define LN_TX_DRV_LVL_CTRL_MASK GENMASK(4, 0)
262 /* LANE_REG(0304) */
263 #define OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK BIT(4)
264 #define LN_TX_DRV_POST_LVL_CTRL_MASK GENMASK(3, 0)
265 /* LANE_REG(0305) */
266 #define OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK BIT(6)
267 #define LN_TX_DRV_PRE_LVL_CTRL_MASK GENMASK(5, 2)
268 /* LANE_REG(0306) */
269 #define LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK GENMASK(7, 5)
270 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK GENMASK(4, 2)
271 #define LN_ANA_TX_DRV_ACCDRV_EN_MASK BIT(0)
272 /* LANE_REG(0307) */
273 #define LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK BIT(6)
274 #define LN_ANA_TX_DRV_ACCDRV_CTRL_MASK GENMASK(5, 3)
275 /* LANE_REG(030a) */
276 #define LN_ANA_TX_JEQ_EN_MASK BIT(4)
277 #define LN_TX_JEQ_EVEN_CTRL_RBR_MASK GENMASK(3, 0)
278 /* LANE_REG(030b) */
279 #define LN_TX_JEQ_EVEN_CTRL_HBR_MASK GENMASK(7, 4)
280 #define LN_TX_JEQ_EVEN_CTRL_HBR2_MASK GENMASK(3, 0)
281 /* LANE_REG(030c) */
282 #define LN_TX_JEQ_ODD_CTRL_RBR_MASK GENMASK(3, 0)
283 /* LANE_REG(030d) */
284 #define LN_TX_JEQ_ODD_CTRL_HBR_MASK GENMASK(7, 4)
285 #define LN_TX_JEQ_ODD_CTRL_HBR2_MASK GENMASK(3, 0)
286 /* LANE_REG(0310) */
287 #define LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0)
288 /* LANE_REG(0311) */
289 #define LN_TX_SER_40BIT_EN_RBR_MASK BIT(3)
290 #define LN_TX_SER_40BIT_EN_HBR_MASK BIT(2)
291 #define LN_TX_SER_40BIT_EN_HBR2_MASK BIT(1)
292 /* LANE_REG(0312) */
293 #define LN0_TX_SER_RATE_SEL_RBR_MASK BIT(5)
294 #define LN0_TX_SER_RATE_SEL_HBR_MASK BIT(4)
295 #define LN0_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
296 #define LN0_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
297 /* LANE_REG(0316) */
298 #define LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
299 /* LANE_REG(031B) */
300 #define LN_ANA_TX_RESERVED_MASK GENMASK(7, 0)
301 /* LANE_REG(031e) */
302 #define LN_POLARITY_INV_MASK BIT(2)
303 #define LN_LANE_MODE_MASK BIT(1)
304
305 /* LANE_REG(0412) */
306 #define LN1_TX_SER_RATE_SEL_RBR_MASK BIT(5)
307 #define LN1_TX_SER_RATE_SEL_HBR_MASK BIT(4)
308 #define LN1_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
309 #define LN1_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
310
311 /* LANE_REG(0512) */
312 #define LN2_TX_SER_RATE_SEL_RBR_MASK BIT(5)
313 #define LN2_TX_SER_RATE_SEL_HBR_MASK BIT(4)
314 #define LN2_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
315 #define LN2_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
316
317 /* LANE_REG(0612) */
318 #define LN3_TX_SER_RATE_SEL_RBR_MASK BIT(5)
319 #define LN3_TX_SER_RATE_SEL_HBR_MASK BIT(4)
320 #define LN3_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
321 #define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
322
323 #define HDMI14_MAX_RATE 340000000
324 #define HDMI20_MAX_RATE 600000000
325
326 enum dp_link_rate {
327 DP_BW_RBR,
328 DP_BW_HBR,
329 DP_BW_HBR2,
330 };
331
332 struct ropll_config {
333 unsigned long long rate;
334 u8 pms_mdiv;
335 u8 pms_mdiv_afc;
336 u8 pms_pdiv;
337 u8 pms_refdiv;
338 u8 pms_sdiv;
339 u8 pms_iqdiv_rstn;
340 u8 ref_clk_sel;
341 u8 sdm_en;
342 u8 sdm_rstn;
343 u8 sdc_frac_en;
344 u8 sdc_rstn;
345 u8 sdm_clk_div;
346 u8 sdm_deno;
347 u8 sdm_num_sign;
348 u8 sdm_num;
349 u8 sdc_n;
350 u8 sdc_num;
351 u8 sdc_deno;
352 u8 sdc_ndiv_rstn;
353 u8 ssc_en;
354 u8 ssc_fm_dev;
355 u8 ssc_fm_freq;
356 u8 ssc_clk_div_sel;
357 u8 ana_cpp_ctrl;
358 u8 ana_lpf_c_sel;
359 u8 cd_tx_ser_rate_sel;
360 };
361
362 struct tx_drv_ctrl {
363 u8 tx_drv_lvl_ctrl;
364 u8 tx_drv_post_lvl_ctrl;
365 u8 ana_tx_drv_idrv_idn_ctrl;
366 u8 ana_tx_drv_idrv_iup_ctrl;
367 u8 ana_tx_drv_accdrv_en;
368 u8 ana_tx_drv_accdrv_ctrl;
369 u8 tx_drv_pre_lvl_ctrl;
370 u8 ana_tx_jeq_en;
371 u8 tx_jeq_even_ctrl;
372 u8 tx_jeq_odd_ctrl;
373 };
374
375 enum rk_hdptx_reset {
376 RST_APB = 0,
377 RST_INIT,
378 RST_CMN,
379 RST_LANE,
380 RST_MAX
381 };
382
383 #define MAX_HDPTX_PHY_NUM 2
384
385 struct rk_hdptx_phy_cfg {
386 unsigned int num_phys;
387 unsigned int phy_ids[MAX_HDPTX_PHY_NUM];
388 };
389
390 struct rk_hdptx_phy {
391 struct device *dev;
392 struct regmap *regmap;
393 struct regmap *grf;
394
395 int phy_id;
396 struct phy *phy;
397 struct phy_configure_opts_hdmi hdmi_cfg;
398 struct clk_bulk_data *clks;
399 int nr_clks;
400 struct reset_control_bulk_data rsts[RST_MAX];
401
402 /* clk provider */
403 struct clk_hw hw;
404 unsigned long hw_rate;
405 bool restrict_rate_change;
406
407 atomic_t usage_count;
408
409 /* used for dp mode */
410 unsigned int link_rate;
411 unsigned int lanes;
412 };
413
414 static const struct ropll_config ropll_tmds_cfg[] = {
415 { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
416 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
417 { 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
418 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
419 { 297000000ULL, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
420 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
421 { 162000000ULL, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10,
422 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
423 { 185625000ULL, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
424 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
425 { 154000000ULL, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1,
426 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
427 { 148500000ULL, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5,
428 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
429 { 146250000ULL, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1,
430 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
431 { 119000000ULL, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1,
432 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
433 { 106500000ULL, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1,
434 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
435 { 108000000ULL, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
436 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
437 { 85500000ULL, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1,
438 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
439 { 83500000ULL, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0,
440 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
441 { 92812500ULL, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
442 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
443 { 74250000ULL, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
444 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
445 { 65000000ULL, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
446 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
447 { 50250000ULL, 84, 84, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 11, 1, 4, 5,
448 4, 11, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
449 { 33750000ULL, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5,
450 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
451 { 40000000ULL, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
452 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
453 { 27000000ULL, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
454 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
455 { 25175000ULL, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1,
456 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
457 };
458
459 static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
460 REG_SEQ0(CMN_REG(0009), 0x0c),
461 REG_SEQ0(CMN_REG(000a), 0x83),
462 REG_SEQ0(CMN_REG(000b), 0x06),
463 REG_SEQ0(CMN_REG(000c), 0x20),
464 REG_SEQ0(CMN_REG(000d), 0xb8),
465 REG_SEQ0(CMN_REG(000e), 0x0f),
466 REG_SEQ0(CMN_REG(000f), 0x0f),
467 REG_SEQ0(CMN_REG(0010), 0x04),
468 REG_SEQ0(CMN_REG(0011), 0x00),
469 REG_SEQ0(CMN_REG(0012), 0x26),
470 REG_SEQ0(CMN_REG(0013), 0x22),
471 REG_SEQ0(CMN_REG(0014), 0x24),
472 REG_SEQ0(CMN_REG(0015), 0x77),
473 REG_SEQ0(CMN_REG(0016), 0x08),
474 REG_SEQ0(CMN_REG(0017), 0x00),
475 REG_SEQ0(CMN_REG(0018), 0x04),
476 REG_SEQ0(CMN_REG(0019), 0x48),
477 REG_SEQ0(CMN_REG(001a), 0x01),
478 REG_SEQ0(CMN_REG(001b), 0x00),
479 REG_SEQ0(CMN_REG(001c), 0x01),
480 REG_SEQ0(CMN_REG(001d), 0x64),
481 REG_SEQ0(CMN_REG(001f), 0x00),
482 REG_SEQ0(CMN_REG(0026), 0x53),
483 REG_SEQ0(CMN_REG(0029), 0x01),
484 REG_SEQ0(CMN_REG(0030), 0x00),
485 REG_SEQ0(CMN_REG(0031), 0x20),
486 REG_SEQ0(CMN_REG(0032), 0x30),
487 REG_SEQ0(CMN_REG(0033), 0x0b),
488 REG_SEQ0(CMN_REG(0034), 0x23),
489 REG_SEQ0(CMN_REG(0035), 0x00),
490 REG_SEQ0(CMN_REG(0038), 0x00),
491 REG_SEQ0(CMN_REG(0039), 0x00),
492 REG_SEQ0(CMN_REG(003a), 0x00),
493 REG_SEQ0(CMN_REG(003b), 0x00),
494 REG_SEQ0(CMN_REG(003c), 0x80),
495 REG_SEQ0(CMN_REG(003e), 0x0c),
496 REG_SEQ0(CMN_REG(003f), 0x83),
497 REG_SEQ0(CMN_REG(0040), 0x06),
498 REG_SEQ0(CMN_REG(0041), 0x20),
499 REG_SEQ0(CMN_REG(0042), 0xb8),
500 REG_SEQ0(CMN_REG(0043), 0x00),
501 REG_SEQ0(CMN_REG(0044), 0x46),
502 REG_SEQ0(CMN_REG(0045), 0x24),
503 REG_SEQ0(CMN_REG(0047), 0x00),
504 REG_SEQ0(CMN_REG(0049), 0xfa),
505 REG_SEQ0(CMN_REG(004a), 0x08),
506 REG_SEQ0(CMN_REG(004b), 0x00),
507 REG_SEQ0(CMN_REG(004c), 0x01),
508 REG_SEQ0(CMN_REG(004d), 0x64),
509 REG_SEQ0(CMN_REG(004e), 0x14),
510 REG_SEQ0(CMN_REG(004f), 0x00),
511 REG_SEQ0(CMN_REG(0050), 0x00),
512 REG_SEQ0(CMN_REG(005d), 0x0c),
513 REG_SEQ0(CMN_REG(005f), 0x01),
514 REG_SEQ0(CMN_REG(006b), 0x04),
515 REG_SEQ0(CMN_REG(0073), 0x30),
516 REG_SEQ0(CMN_REG(0074), 0x00),
517 REG_SEQ0(CMN_REG(0075), 0x20),
518 REG_SEQ0(CMN_REG(0076), 0x30),
519 REG_SEQ0(CMN_REG(0077), 0x08),
520 REG_SEQ0(CMN_REG(0078), 0x0c),
521 REG_SEQ0(CMN_REG(0079), 0x00),
522 REG_SEQ0(CMN_REG(007b), 0x00),
523 REG_SEQ0(CMN_REG(007c), 0x00),
524 REG_SEQ0(CMN_REG(007d), 0x00),
525 REG_SEQ0(CMN_REG(007e), 0x00),
526 REG_SEQ0(CMN_REG(007f), 0x00),
527 REG_SEQ0(CMN_REG(0080), 0x00),
528 REG_SEQ0(CMN_REG(0081), 0x09),
529 REG_SEQ0(CMN_REG(0082), 0x04),
530 REG_SEQ0(CMN_REG(0083), 0x24),
531 REG_SEQ0(CMN_REG(0084), 0x20),
532 REG_SEQ0(CMN_REG(0085), 0x03),
533 REG_SEQ0(CMN_REG(0086), 0x01),
534 REG_SEQ0(CMN_REG(0087), 0x0c),
535 REG_SEQ0(CMN_REG(008a), 0x55),
536 REG_SEQ0(CMN_REG(008b), 0x25),
537 REG_SEQ0(CMN_REG(008c), 0x2c),
538 REG_SEQ0(CMN_REG(008d), 0x22),
539 REG_SEQ0(CMN_REG(008e), 0x14),
540 REG_SEQ0(CMN_REG(008f), 0x20),
541 REG_SEQ0(CMN_REG(0090), 0x00),
542 REG_SEQ0(CMN_REG(0091), 0x00),
543 REG_SEQ0(CMN_REG(0092), 0x00),
544 REG_SEQ0(CMN_REG(0093), 0x00),
545 REG_SEQ0(CMN_REG(009a), 0x11),
546 REG_SEQ0(CMN_REG(009b), 0x10),
547 };
548
549 static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
550 REG_SEQ0(CMN_REG(0008), 0x00),
551 REG_SEQ0(CMN_REG(0011), 0x01),
552 REG_SEQ0(CMN_REG(0017), 0x20),
553 REG_SEQ0(CMN_REG(001e), 0x14),
554 REG_SEQ0(CMN_REG(0020), 0x00),
555 REG_SEQ0(CMN_REG(0021), 0x00),
556 REG_SEQ0(CMN_REG(0022), 0x11),
557 REG_SEQ0(CMN_REG(0023), 0x00),
558 REG_SEQ0(CMN_REG(0024), 0x00),
559 REG_SEQ0(CMN_REG(0025), 0x53),
560 REG_SEQ0(CMN_REG(0026), 0x00),
561 REG_SEQ0(CMN_REG(0027), 0x00),
562 REG_SEQ0(CMN_REG(0028), 0x01),
563 REG_SEQ0(CMN_REG(002a), 0x00),
564 REG_SEQ0(CMN_REG(002b), 0x00),
565 REG_SEQ0(CMN_REG(002c), 0x00),
566 REG_SEQ0(CMN_REG(002d), 0x00),
567 REG_SEQ0(CMN_REG(002e), 0x04),
568 REG_SEQ0(CMN_REG(002f), 0x00),
569 REG_SEQ0(CMN_REG(0030), 0x20),
570 REG_SEQ0(CMN_REG(0031), 0x30),
571 REG_SEQ0(CMN_REG(0032), 0x0b),
572 REG_SEQ0(CMN_REG(0033), 0x23),
573 REG_SEQ0(CMN_REG(0034), 0x00),
574 REG_SEQ0(CMN_REG(003d), 0x40),
575 REG_SEQ0(CMN_REG(0042), 0x78),
576 REG_SEQ0(CMN_REG(0046), 0xdd),
577 REG_SEQ0(CMN_REG(0048), 0x11),
578 REG_SEQ0(CMN_REG(004e), 0x34),
579 REG_SEQ0(CMN_REG(005c), 0x25),
580 REG_SEQ0(CMN_REG(005e), 0x4f),
581 REG_SEQ0(CMN_REG(0074), 0x04),
582 REG_SEQ0(CMN_REG(0081), 0x01),
583 REG_SEQ0(CMN_REG(0087), 0x04),
584 REG_SEQ0(CMN_REG(0089), 0x00),
585 REG_SEQ0(CMN_REG(0095), 0x00),
586 REG_SEQ0(CMN_REG(0097), 0x02),
587 REG_SEQ0(CMN_REG(0099), 0x04),
588 REG_SEQ0(CMN_REG(009b), 0x00),
589 };
590
591 static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
592 REG_SEQ0(SB_REG(0114), 0x00),
593 REG_SEQ0(SB_REG(0115), 0x00),
594 REG_SEQ0(SB_REG(0116), 0x00),
595 REG_SEQ0(SB_REG(0117), 0x00),
596 };
597
598 static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = {
599 REG_SEQ0(LNTOP_REG(0201), 0x00),
600 REG_SEQ0(LNTOP_REG(0202), 0x00),
601 REG_SEQ0(LNTOP_REG(0203), 0x0f),
602 REG_SEQ0(LNTOP_REG(0204), 0xff),
603 REG_SEQ0(LNTOP_REG(0205), 0xff),
604 };
605
606 static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
607 REG_SEQ0(LNTOP_REG(0201), 0x07),
608 REG_SEQ0(LNTOP_REG(0202), 0xc1),
609 REG_SEQ0(LNTOP_REG(0203), 0xf0),
610 REG_SEQ0(LNTOP_REG(0204), 0x7c),
611 REG_SEQ0(LNTOP_REG(0205), 0x1f),
612 };
613
614 static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
615 REG_SEQ0(LANE_REG(0303), 0x0c),
616 REG_SEQ0(LANE_REG(0307), 0x20),
617 REG_SEQ0(LANE_REG(030a), 0x17),
618 REG_SEQ0(LANE_REG(030b), 0x77),
619 REG_SEQ0(LANE_REG(030c), 0x77),
620 REG_SEQ0(LANE_REG(030d), 0x77),
621 REG_SEQ0(LANE_REG(030e), 0x38),
622 REG_SEQ0(LANE_REG(0310), 0x03),
623 REG_SEQ0(LANE_REG(0311), 0x0f),
624 REG_SEQ0(LANE_REG(0316), 0x02),
625 REG_SEQ0(LANE_REG(031b), 0x01),
626 REG_SEQ0(LANE_REG(031f), 0x15),
627 REG_SEQ0(LANE_REG(0320), 0xa0),
628 REG_SEQ0(LANE_REG(0403), 0x0c),
629 REG_SEQ0(LANE_REG(0407), 0x20),
630 REG_SEQ0(LANE_REG(040a), 0x17),
631 REG_SEQ0(LANE_REG(040b), 0x77),
632 REG_SEQ0(LANE_REG(040c), 0x77),
633 REG_SEQ0(LANE_REG(040d), 0x77),
634 REG_SEQ0(LANE_REG(040e), 0x38),
635 REG_SEQ0(LANE_REG(0410), 0x03),
636 REG_SEQ0(LANE_REG(0411), 0x0f),
637 REG_SEQ0(LANE_REG(0416), 0x02),
638 REG_SEQ0(LANE_REG(041b), 0x01),
639 REG_SEQ0(LANE_REG(041f), 0x15),
640 REG_SEQ0(LANE_REG(0420), 0xa0),
641 REG_SEQ0(LANE_REG(0503), 0x0c),
642 REG_SEQ0(LANE_REG(0507), 0x20),
643 REG_SEQ0(LANE_REG(050a), 0x17),
644 REG_SEQ0(LANE_REG(050b), 0x77),
645 REG_SEQ0(LANE_REG(050c), 0x77),
646 REG_SEQ0(LANE_REG(050d), 0x77),
647 REG_SEQ0(LANE_REG(050e), 0x38),
648 REG_SEQ0(LANE_REG(0510), 0x03),
649 REG_SEQ0(LANE_REG(0511), 0x0f),
650 REG_SEQ0(LANE_REG(0516), 0x02),
651 REG_SEQ0(LANE_REG(051b), 0x01),
652 REG_SEQ0(LANE_REG(051f), 0x15),
653 REG_SEQ0(LANE_REG(0520), 0xa0),
654 REG_SEQ0(LANE_REG(0603), 0x0c),
655 REG_SEQ0(LANE_REG(0607), 0x20),
656 REG_SEQ0(LANE_REG(060a), 0x17),
657 REG_SEQ0(LANE_REG(060b), 0x77),
658 REG_SEQ0(LANE_REG(060c), 0x77),
659 REG_SEQ0(LANE_REG(060d), 0x77),
660 REG_SEQ0(LANE_REG(060e), 0x38),
661 REG_SEQ0(LANE_REG(0610), 0x03),
662 REG_SEQ0(LANE_REG(0611), 0x0f),
663 REG_SEQ0(LANE_REG(0616), 0x02),
664 REG_SEQ0(LANE_REG(061b), 0x01),
665 REG_SEQ0(LANE_REG(061f), 0x15),
666 REG_SEQ0(LANE_REG(0620), 0xa0),
667 };
668
669 static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
670 REG_SEQ0(LANE_REG(0312), 0x00),
671 REG_SEQ0(LANE_REG(0412), 0x00),
672 REG_SEQ0(LANE_REG(0512), 0x00),
673 REG_SEQ0(LANE_REG(0612), 0x00),
674 REG_SEQ0(LANE_REG(0303), 0x2f),
675 REG_SEQ0(LANE_REG(0403), 0x2f),
676 REG_SEQ0(LANE_REG(0503), 0x2f),
677 REG_SEQ0(LANE_REG(0603), 0x2f),
678 REG_SEQ0(LANE_REG(0305), 0x03),
679 REG_SEQ0(LANE_REG(0405), 0x03),
680 REG_SEQ0(LANE_REG(0505), 0x03),
681 REG_SEQ0(LANE_REG(0605), 0x03),
682 REG_SEQ0(LANE_REG(0306), 0x1c),
683 REG_SEQ0(LANE_REG(0406), 0x1c),
684 REG_SEQ0(LANE_REG(0506), 0x1c),
685 REG_SEQ0(LANE_REG(0606), 0x1c),
686 /* Keep Inter-Pair Skew in the limits */
687 REG_SEQ0(LANE_REG(031e), 0x02),
688 REG_SEQ0(LANE_REG(041e), 0x02),
689 REG_SEQ0(LANE_REG(051e), 0x02),
690 REG_SEQ0(LANE_REG(061e), 0x0a),
691 };
692
693 static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = {
694 /* voltage swing 0, pre-emphasis 0->3 */
695 {
696 { 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
697 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
698 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
699 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
700 },
701
702 /* voltage swing 1, pre-emphasis 0->2 */
703 {
704 { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
705 { 0x9, 0x5, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
706 { 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
707 },
708
709 /* voltage swing 2, pre-emphasis 0->1 */
710 {
711 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
712 { 0xc, 0x5, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
713 },
714
715 /* voltage swing 3, pre-emphasis 0 */
716 {
717 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
718 }
719 };
720
721 static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = {
722 /* voltage swing 0, pre-emphasis 0->3 */
723 {
724 { 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
725 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
726 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
727 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
728 },
729
730 /* voltage swing 1, pre-emphasis 0->2 */
731 {
732 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
733 { 0xa, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
734 { 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
735 },
736
737 /* voltage swing 2, pre-emphasis 0->1 */
738 {
739 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
740 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
741 },
742
743 /* voltage swing 3, pre-emphasis 0 */
744 {
745 { 0xc, 0x1, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
746 }
747 };
748
749 static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = {
750 /* voltage swing 0, pre-emphasis 0->3 */
751 {
752 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
753 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
754 { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4, 0x0, 0x1, 0x7, 0x7 },
755 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
756 },
757
758 /* voltage swing 1, pre-emphasis 0->2 */
759 {
760 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
761 { 0xb, 0x7, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
762 { 0xd, 0x9, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
763 },
764
765 /* voltage swing 2, pre-emphasis 0->1 */
766 {
767 { 0x8, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
768 { 0xc, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
769 },
770
771 /* voltage swing 3, pre-emphasis 0 */
772 {
773 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
774 }
775 };
776
rk_hdptx_phy_is_rw_reg(struct device * dev,unsigned int reg)777 static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg)
778 {
779 switch (reg) {
780 case 0x0000 ... 0x029c: /* CMN Register */
781 case 0x0400 ... 0x04a4: /* Sideband Register */
782 case 0x0800 ... 0x08a4: /* Lane Top Register */
783 case 0x0c00 ... 0x0cb4: /* Lane 0 Register */
784 case 0x1000 ... 0x10b4: /* Lane 1 Register */
785 case 0x1400 ... 0x14b4: /* Lane 2 Register */
786 case 0x1800 ... 0x18b4: /* Lane 3 Register */
787 return true;
788 }
789
790 return false;
791 }
792
793 static const struct regmap_config rk_hdptx_phy_regmap_config = {
794 .reg_bits = 32,
795 .reg_stride = 4,
796 .val_bits = 32,
797 .writeable_reg = rk_hdptx_phy_is_rw_reg,
798 .readable_reg = rk_hdptx_phy_is_rw_reg,
799 .max_register = 0x18b4,
800 };
801
802 #define rk_hdptx_multi_reg_write(hdptx, seq) \
803 regmap_multi_reg_write((hdptx)->regmap, seq, ARRAY_SIZE(seq))
804
rk_hdptx_pre_power_up(struct rk_hdptx_phy * hdptx)805 static void rk_hdptx_pre_power_up(struct rk_hdptx_phy *hdptx)
806 {
807 u32 val;
808
809 reset_control_assert(hdptx->rsts[RST_APB].rstc);
810 usleep_range(20, 25);
811 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
812
813 reset_control_assert(hdptx->rsts[RST_LANE].rstc);
814 reset_control_assert(hdptx->rsts[RST_CMN].rstc);
815 reset_control_assert(hdptx->rsts[RST_INIT].rstc);
816
817 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
818 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
819 }
820
rk_hdptx_post_enable_lane(struct rk_hdptx_phy * hdptx)821 static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx)
822 {
823 u32 val;
824 int ret;
825
826 reset_control_deassert(hdptx->rsts[RST_LANE].rstc);
827
828 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
829 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
830 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
831
832 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
833 (val & HDPTX_O_PHY_RDY) &&
834 (val & HDPTX_O_PLL_LOCK_DONE),
835 100, 5000);
836 if (ret) {
837 dev_err(hdptx->dev, "Failed to get PHY lane lock: %d\n", ret);
838 return ret;
839 }
840
841 dev_dbg(hdptx->dev, "PHY lane locked\n");
842
843 return 0;
844 }
845
rk_hdptx_post_enable_pll(struct rk_hdptx_phy * hdptx)846 static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx)
847 {
848 u32 val;
849 int ret;
850
851 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
852 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
853 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
854
855 usleep_range(10, 15);
856 reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
857
858 usleep_range(10, 15);
859 val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN;
860 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
861
862 usleep_range(10, 15);
863 reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
864
865 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
866 val & HDPTX_O_PHY_CLK_RDY, 20, 400);
867 if (ret) {
868 dev_err(hdptx->dev, "Failed to get PHY clk ready: %d\n", ret);
869 return ret;
870 }
871
872 dev_dbg(hdptx->dev, "PHY clk ready\n");
873
874 return 0;
875 }
876
rk_hdptx_phy_disable(struct rk_hdptx_phy * hdptx)877 static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
878 {
879 u32 val;
880
881 reset_control_assert(hdptx->rsts[RST_APB].rstc);
882 usleep_range(20, 30);
883 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
884
885 regmap_write(hdptx->regmap, LANE_REG(0300), 0x82);
886 regmap_write(hdptx->regmap, SB_REG(010f), 0xc1);
887 regmap_write(hdptx->regmap, SB_REG(0110), 0x1);
888 regmap_write(hdptx->regmap, LANE_REG(0301), 0x80);
889 regmap_write(hdptx->regmap, LANE_REG(0401), 0x80);
890 regmap_write(hdptx->regmap, LANE_REG(0501), 0x80);
891 regmap_write(hdptx->regmap, LANE_REG(0601), 0x80);
892
893 reset_control_assert(hdptx->rsts[RST_LANE].rstc);
894 reset_control_assert(hdptx->rsts[RST_CMN].rstc);
895 reset_control_assert(hdptx->rsts[RST_INIT].rstc);
896
897 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
898 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
899 }
900
rk_hdptx_phy_clk_pll_calc(unsigned long long rate,struct ropll_config * cfg)901 static bool rk_hdptx_phy_clk_pll_calc(unsigned long long rate,
902 struct ropll_config *cfg)
903 {
904 const unsigned int fout = div_u64(rate, 200), fref = 24000;
905 unsigned long k = 0, lc, k_sub, lc_sub;
906 unsigned int fvco, sdc;
907 u32 mdiv, sdiv, n = 8;
908
909 if (fout > 0xfffffff)
910 return false;
911
912 for (sdiv = 16; sdiv >= 1; sdiv--) {
913 if (sdiv % 2 && sdiv != 1)
914 continue;
915
916 fvco = fout * sdiv;
917
918 if (fvco < 2000000 || fvco > 4000000)
919 continue;
920
921 mdiv = DIV_ROUND_UP(fvco, fref);
922 if (mdiv < 20 || mdiv > 255)
923 continue;
924
925 if (fref * mdiv - fvco) {
926 for (sdc = 264000; sdc <= 750000; sdc += fref)
927 if (sdc * n > fref * mdiv)
928 break;
929
930 if (sdc > 750000)
931 continue;
932
933 rational_best_approximation(fref * mdiv - fvco,
934 sdc / 16,
935 GENMASK(6, 0),
936 GENMASK(7, 0),
937 &k, &lc);
938
939 rational_best_approximation(sdc * n - fref * mdiv,
940 sdc,
941 GENMASK(6, 0),
942 GENMASK(7, 0),
943 &k_sub, &lc_sub);
944 }
945
946 break;
947 }
948
949 if (sdiv < 1)
950 return false;
951
952 if (cfg) {
953 cfg->pms_mdiv = mdiv;
954 cfg->pms_mdiv_afc = mdiv;
955 cfg->pms_pdiv = 1;
956 cfg->pms_refdiv = 1;
957 cfg->pms_sdiv = sdiv - 1;
958
959 cfg->sdm_en = k > 0 ? 1 : 0;
960 if (cfg->sdm_en) {
961 cfg->sdm_deno = lc;
962 cfg->sdm_num_sign = 1;
963 cfg->sdm_num = k;
964 cfg->sdc_n = n - 3;
965 cfg->sdc_num = k_sub;
966 cfg->sdc_deno = lc_sub;
967 }
968 }
969
970 return true;
971 }
972
rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy * hdptx)973 static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
974 {
975 const struct ropll_config *cfg = NULL;
976 struct ropll_config rc = {0};
977 int ret, i;
978
979 if (!hdptx->hdmi_cfg.tmds_char_rate)
980 return 0;
981
982 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
983 if (hdptx->hdmi_cfg.tmds_char_rate == ropll_tmds_cfg[i].rate) {
984 cfg = &ropll_tmds_cfg[i];
985 break;
986 }
987
988 if (!cfg) {
989 if (!rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.tmds_char_rate, &rc)) {
990 dev_err(hdptx->dev, "%s cannot find pll cfg for rate=%llu\n",
991 __func__, hdptx->hdmi_cfg.tmds_char_rate);
992 return -EINVAL;
993 }
994
995 cfg = &rc;
996 }
997
998 dev_dbg(hdptx->dev, "%s rate=%llu mdiv=%u sdiv=%u sdm_en=%u k_sign=%u k=%u lc=%u\n",
999 __func__, hdptx->hdmi_cfg.tmds_char_rate, cfg->pms_mdiv, cfg->pms_sdiv + 1,
1000 cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
1001
1002 rk_hdptx_pre_power_up(hdptx);
1003
1004 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
1005 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq);
1006
1007 regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv);
1008 regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc);
1009 regmap_write(hdptx->regmap, CMN_REG(0059),
1010 (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
1011 regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4);
1012
1013 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK,
1014 FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en));
1015 if (!cfg->sdm_en)
1016 regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0);
1017
1018 regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK,
1019 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign));
1020
1021 regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno);
1022 regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num);
1023
1024 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK,
1025 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n));
1026
1027 regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num);
1028 regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno);
1029
1030 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
1031 FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
1032
1033 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK,
1034 FIELD_PREP(PLL_PCG_CLK_SEL_MASK, (hdptx->hdmi_cfg.bpc - 8) >> 1));
1035
1036 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK,
1037 FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1));
1038
1039 ret = rk_hdptx_post_enable_pll(hdptx);
1040 if (!ret)
1041 hdptx->hw_rate = DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8,
1042 hdptx->hdmi_cfg.bpc);
1043
1044 return ret;
1045 }
1046
rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy * hdptx)1047 static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx)
1048 {
1049 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
1050
1051 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
1052
1053 if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) {
1054 /* For 1/40 bitrate clk */
1055 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
1056 } else {
1057 /* For 1/10 bitrate clk */
1058 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq);
1059 }
1060
1061 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
1062 regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
1063
1064 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
1065 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
1066
1067 return rk_hdptx_post_enable_lane(hdptx);
1068 }
1069
rk_hdptx_dp_reset(struct rk_hdptx_phy * hdptx)1070 static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx)
1071 {
1072 reset_control_assert(hdptx->rsts[RST_LANE].rstc);
1073 reset_control_assert(hdptx->rsts[RST_CMN].rstc);
1074 reset_control_assert(hdptx->rsts[RST_INIT].rstc);
1075
1076 reset_control_assert(hdptx->rsts[RST_APB].rstc);
1077 udelay(10);
1078 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
1079
1080 regmap_update_bits(hdptx->regmap, LANE_REG(0301),
1081 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK,
1082 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) |
1083 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0));
1084 regmap_update_bits(hdptx->regmap, LANE_REG(0401),
1085 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK,
1086 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) |
1087 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0));
1088 regmap_update_bits(hdptx->regmap, LANE_REG(0501),
1089 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK,
1090 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) |
1091 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0));
1092 regmap_update_bits(hdptx->regmap, LANE_REG(0601),
1093 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK,
1094 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) |
1095 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0));
1096
1097 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1098 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0));
1099 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1100 HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x0));
1101 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1102 HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x0));
1103 }
1104
rk_hdptx_phy_consumer_get(struct rk_hdptx_phy * hdptx)1105 static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx)
1106 {
1107 enum phy_mode mode = phy_get_mode(hdptx->phy);
1108 u32 status;
1109 int ret;
1110
1111 if (atomic_inc_return(&hdptx->usage_count) > 1)
1112 return 0;
1113
1114 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
1115 if (ret)
1116 goto dec_usage;
1117
1118 if (status & HDPTX_O_PLL_LOCK_DONE)
1119 dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n");
1120
1121 if (mode == PHY_MODE_DP) {
1122 rk_hdptx_dp_reset(hdptx);
1123 } else {
1124 ret = rk_hdptx_ropll_tmds_cmn_config(hdptx);
1125 if (ret)
1126 goto dec_usage;
1127 }
1128
1129 return 0;
1130
1131 dec_usage:
1132 atomic_dec(&hdptx->usage_count);
1133 return ret;
1134 }
1135
rk_hdptx_phy_consumer_put(struct rk_hdptx_phy * hdptx,bool force)1136 static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force)
1137 {
1138 enum phy_mode mode = phy_get_mode(hdptx->phy);
1139 u32 status;
1140 int ret;
1141
1142 ret = atomic_dec_return(&hdptx->usage_count);
1143 if (ret > 0)
1144 return 0;
1145
1146 if (ret < 0) {
1147 dev_warn(hdptx->dev, "Usage count underflow!\n");
1148 ret = -EINVAL;
1149 } else {
1150 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
1151 if (!ret) {
1152 if (status & HDPTX_O_PLL_LOCK_DONE) {
1153 if (mode == PHY_MODE_DP)
1154 rk_hdptx_dp_reset(hdptx);
1155 else
1156 rk_hdptx_phy_disable(hdptx);
1157 }
1158 return 0;
1159 } else if (force) {
1160 return 0;
1161 }
1162 }
1163
1164 atomic_inc(&hdptx->usage_count);
1165 return ret;
1166 }
1167
rk_hdptx_dp_pll_init(struct rk_hdptx_phy * hdptx)1168 static void rk_hdptx_dp_pll_init(struct rk_hdptx_phy *hdptx)
1169 {
1170 regmap_update_bits(hdptx->regmap, CMN_REG(003c), ANA_LCPLL_RESERVED7_MASK,
1171 FIELD_PREP(ANA_LCPLL_RESERVED7_MASK, 0x1));
1172
1173 regmap_update_bits(hdptx->regmap, CMN_REG(0046),
1174 ROPLL_ANA_CPP_CTRL_COARSE_MASK | ROPLL_ANA_CPP_CTRL_FINE_MASK,
1175 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE_MASK, 0xe) |
1176 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE_MASK, 0xe));
1177 regmap_update_bits(hdptx->regmap, CMN_REG(0047),
1178 ROPLL_ANA_LPF_C_SEL_COARSE_MASK |
1179 ROPLL_ANA_LPF_C_SEL_FINE_MASK,
1180 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE_MASK, 0x4) |
1181 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE_MASK, 0x4));
1182
1183 regmap_write(hdptx->regmap, CMN_REG(0051), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x87));
1184 regmap_write(hdptx->regmap, CMN_REG(0052), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x71));
1185 regmap_write(hdptx->regmap, CMN_REG(0053), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x71));
1186
1187 regmap_write(hdptx->regmap, CMN_REG(0055),
1188 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x87));
1189 regmap_write(hdptx->regmap, CMN_REG(0056),
1190 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x71));
1191 regmap_write(hdptx->regmap, CMN_REG(0057),
1192 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x71));
1193
1194 regmap_write(hdptx->regmap, CMN_REG(0059),
1195 FIELD_PREP(ANA_ROPLL_PMS_PDIV_MASK, 0x1) |
1196 FIELD_PREP(ANA_ROPLL_PMS_REFDIV_MASK, 0x1));
1197 regmap_write(hdptx->regmap, CMN_REG(005a),
1198 FIELD_PREP(ROPLL_PMS_SDIV_RBR_MASK, 0x3) |
1199 FIELD_PREP(ROPLL_PMS_SDIV_HBR_MASK, 0x1));
1200 regmap_update_bits(hdptx->regmap, CMN_REG(005b), ROPLL_PMS_SDIV_HBR2_MASK,
1201 FIELD_PREP(ROPLL_PMS_SDIV_HBR2_MASK, 0x0));
1202
1203 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK,
1204 FIELD_PREP(ROPLL_SDM_EN_MASK, 0x1));
1205 regmap_update_bits(hdptx->regmap, CMN_REG(005e),
1206 OVRD_ROPLL_SDM_RSTN_MASK | ROPLL_SDM_RSTN_MASK,
1207 FIELD_PREP(OVRD_ROPLL_SDM_RSTN_MASK, 0x1) |
1208 FIELD_PREP(ROPLL_SDM_RSTN_MASK, 0x1));
1209 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_RBR_MASK,
1210 FIELD_PREP(ROPLL_SDC_FRAC_EN_RBR_MASK, 0x1));
1211 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_HBR_MASK,
1212 FIELD_PREP(ROPLL_SDC_FRAC_EN_HBR_MASK, 0x1));
1213 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_HBR2_MASK,
1214 FIELD_PREP(ROPLL_SDC_FRAC_EN_HBR2_MASK, 0x1));
1215
1216 regmap_update_bits(hdptx->regmap, CMN_REG(005f),
1217 OVRD_ROPLL_SDC_RSTN_MASK | ROPLL_SDC_RSTN_MASK,
1218 FIELD_PREP(OVRD_ROPLL_SDC_RSTN_MASK, 0x1) |
1219 FIELD_PREP(ROPLL_SDC_RSTN_MASK, 0x1));
1220 regmap_write(hdptx->regmap, CMN_REG(0060),
1221 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x21));
1222 regmap_write(hdptx->regmap, CMN_REG(0061),
1223 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x27));
1224 regmap_write(hdptx->regmap, CMN_REG(0062),
1225 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x27));
1226
1227 regmap_update_bits(hdptx->regmap, CMN_REG(0064),
1228 ROPLL_SDM_NUM_SIGN_RBR_MASK |
1229 ROPLL_SDM_NUM_SIGN_HBR_MASK |
1230 ROPLL_SDM_NUM_SIGN_HBR2_MASK,
1231 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, 0x0) |
1232 FIELD_PREP(ROPLL_SDM_NUM_SIGN_HBR_MASK, 0x1) |
1233 FIELD_PREP(ROPLL_SDM_NUM_SIGN_HBR2_MASK, 0x1));
1234 regmap_write(hdptx->regmap, CMN_REG(0065),
1235 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0x0));
1236 regmap_write(hdptx->regmap, CMN_REG(0066),
1237 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0xd));
1238 regmap_write(hdptx->regmap, CMN_REG(0067),
1239 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0xd));
1240
1241 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK,
1242 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, 0x2));
1243
1244 regmap_update_bits(hdptx->regmap, CMN_REG(006a),
1245 ROPLL_SDC_N_HBR_MASK | ROPLL_SDC_N_HBR2_MASK,
1246 FIELD_PREP(ROPLL_SDC_N_HBR_MASK, 0x1) |
1247 FIELD_PREP(ROPLL_SDC_N_HBR2_MASK, 0x1));
1248
1249 regmap_write(hdptx->regmap, CMN_REG(006c),
1250 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x3));
1251 regmap_write(hdptx->regmap, CMN_REG(006d),
1252 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x7));
1253 regmap_write(hdptx->regmap, CMN_REG(006e),
1254 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x7));
1255
1256 regmap_write(hdptx->regmap, CMN_REG(0070),
1257 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x8));
1258 regmap_write(hdptx->regmap, CMN_REG(0071),
1259 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x18));
1260 regmap_write(hdptx->regmap, CMN_REG(0072),
1261 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x18));
1262
1263 regmap_update_bits(hdptx->regmap, CMN_REG(0074),
1264 OVRD_ROPLL_SDC_NDIV_RSTN_MASK | ROPLL_SDC_NDIV_RSTN_MASK,
1265 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN_MASK, 0x1) |
1266 FIELD_PREP(ROPLL_SDC_NDIV_RSTN_MASK, 0x1));
1267
1268 regmap_update_bits(hdptx->regmap, CMN_REG(0077), ANA_ROPLL_SSC_CLK_DIV_SEL_MASK,
1269 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL_MASK, 0x1));
1270
1271 regmap_update_bits(hdptx->regmap, CMN_REG(0081), ANA_PLL_CD_TX_SER_RATE_SEL_MASK,
1272 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL_MASK, 0x0));
1273 regmap_update_bits(hdptx->regmap, CMN_REG(0081),
1274 ANA_PLL_CD_HSCLK_EAST_EN_MASK | ANA_PLL_CD_HSCLK_WEST_EN_MASK,
1275 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN_MASK, 0x1) |
1276 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN_MASK, 0x0));
1277
1278 regmap_update_bits(hdptx->regmap, CMN_REG(0082), ANA_PLL_CD_VREG_GAIN_CTRL_MASK,
1279 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL_MASK, 0x4));
1280 regmap_update_bits(hdptx->regmap, CMN_REG(0083), ANA_PLL_CD_VREG_ICTRL_MASK,
1281 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL_MASK, 0x1));
1282 regmap_update_bits(hdptx->regmap, CMN_REG(0084), PLL_LCRO_CLK_SEL_MASK,
1283 FIELD_PREP(PLL_LCRO_CLK_SEL_MASK, 0x1));
1284 regmap_update_bits(hdptx->regmap, CMN_REG(0085), ANA_PLL_SYNC_LOSS_DET_MODE_MASK,
1285 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE_MASK, 0x3));
1286
1287 regmap_update_bits(hdptx->regmap, CMN_REG(0087), ANA_PLL_TX_HS_CLK_EN_MASK,
1288 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN_MASK, 0x1));
1289
1290 regmap_update_bits(hdptx->regmap, CMN_REG(0097), DIG_CLK_SEL_MASK,
1291 FIELD_PREP(DIG_CLK_SEL_MASK, 0x1));
1292
1293 regmap_update_bits(hdptx->regmap, CMN_REG(0099), CMN_ROPLL_ALONE_MODE_MASK,
1294 FIELD_PREP(CMN_ROPLL_ALONE_MODE_MASK, 0x1));
1295 regmap_update_bits(hdptx->regmap, CMN_REG(009a), HS_SPEED_SEL_MASK,
1296 FIELD_PREP(HS_SPEED_SEL_MASK, 0x1));
1297 regmap_update_bits(hdptx->regmap, CMN_REG(009b), LS_SPEED_SEL_MASK,
1298 FIELD_PREP(LS_SPEED_SEL_MASK, 0x1));
1299 }
1300
rk_hdptx_dp_aux_init(struct rk_hdptx_phy * hdptx)1301 static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy *hdptx)
1302 {
1303 u32 status;
1304 int ret;
1305
1306 regmap_update_bits(hdptx->regmap, SB_REG(0102), ANA_SB_RXTERM_OFFSP_MASK,
1307 FIELD_PREP(ANA_SB_RXTERM_OFFSP_MASK, 0x3));
1308 regmap_update_bits(hdptx->regmap, SB_REG(0103), ANA_SB_RXTERM_OFFSN_MASK,
1309 FIELD_PREP(ANA_SB_RXTERM_OFFSN_MASK, 0x3));
1310 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_AUX_EN_MASK,
1311 FIELD_PREP(SB_AUX_EN_MASK, 0x1));
1312 regmap_update_bits(hdptx->regmap, SB_REG(0105), ANA_SB_TX_HLVL_PROG_MASK,
1313 FIELD_PREP(ANA_SB_TX_HLVL_PROG_MASK, 0x7));
1314 regmap_update_bits(hdptx->regmap, SB_REG(0106), ANA_SB_TX_LLVL_PROG_MASK,
1315 FIELD_PREP(ANA_SB_TX_LLVL_PROG_MASK, 0x7));
1316
1317 regmap_update_bits(hdptx->regmap, SB_REG(010d), ANA_SB_DMRX_LPBK_DATA_MASK,
1318 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA_MASK, 0x1));
1319
1320 regmap_update_bits(hdptx->regmap, SB_REG(010f), ANA_SB_VREG_GAIN_CTRL_MASK,
1321 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL_MASK, 0x0));
1322 regmap_update_bits(hdptx->regmap, SB_REG(0110),
1323 ANA_SB_VREG_OUT_SEL_MASK | ANA_SB_VREG_REF_SEL_MASK,
1324 FIELD_PREP(ANA_SB_VREG_OUT_SEL_MASK, 0x1) |
1325 FIELD_PREP(ANA_SB_VREG_REF_SEL_MASK, 0x1));
1326
1327 regmap_update_bits(hdptx->regmap, SB_REG(0113),
1328 SB_RX_RCAL_OPT_CODE_MASK | SB_RX_RTERM_CTRL_MASK,
1329 FIELD_PREP(SB_RX_RCAL_OPT_CODE_MASK, 0x1) |
1330 FIELD_PREP(SB_RX_RTERM_CTRL_MASK, 0x3));
1331 regmap_update_bits(hdptx->regmap, SB_REG(0114),
1332 SB_TG_SB_EN_DELAY_TIME_MASK | SB_TG_RXTERM_EN_DELAY_TIME_MASK,
1333 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME_MASK, 0x2) |
1334 FIELD_PREP(SB_TG_RXTERM_EN_DELAY_TIME_MASK, 0x2));
1335 regmap_update_bits(hdptx->regmap, SB_REG(0115),
1336 SB_READY_DELAY_TIME_MASK | SB_TG_OSC_EN_DELAY_TIME_MASK,
1337 FIELD_PREP(SB_READY_DELAY_TIME_MASK, 0x2) |
1338 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME_MASK, 0x2));
1339 regmap_update_bits(hdptx->regmap, SB_REG(0116),
1340 AFC_RSTN_DELAY_TIME_MASK,
1341 FIELD_PREP(AFC_RSTN_DELAY_TIME_MASK, 0x2));
1342 regmap_update_bits(hdptx->regmap, SB_REG(0117),
1343 FAST_PULSE_TIME_MASK,
1344 FIELD_PREP(FAST_PULSE_TIME_MASK, 0x4));
1345 regmap_update_bits(hdptx->regmap, SB_REG(0118),
1346 SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK,
1347 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK, 0xa));
1348
1349 regmap_update_bits(hdptx->regmap, SB_REG(011a), SB_TG_CNT_RUN_NO_7_0_MASK,
1350 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0_MASK, 0x3));
1351 regmap_update_bits(hdptx->regmap, SB_REG(011b),
1352 SB_EARC_SIG_DET_BYPASS_MASK | SB_AFC_TOL_MASK,
1353 FIELD_PREP(SB_EARC_SIG_DET_BYPASS_MASK, 0x1) |
1354 FIELD_PREP(SB_AFC_TOL_MASK, 0x3));
1355 regmap_update_bits(hdptx->regmap, SB_REG(011c), SB_AFC_STB_NUM_MASK,
1356 FIELD_PREP(SB_AFC_STB_NUM_MASK, 0x4));
1357 regmap_update_bits(hdptx->regmap, SB_REG(011d), SB_TG_OSC_CNT_MIN_MASK,
1358 FIELD_PREP(SB_TG_OSC_CNT_MIN_MASK, 0x67));
1359 regmap_update_bits(hdptx->regmap, SB_REG(011e), SB_TG_OSC_CNT_MAX_MASK,
1360 FIELD_PREP(SB_TG_OSC_CNT_MAX_MASK, 0x6a));
1361 regmap_update_bits(hdptx->regmap, SB_REG(011f), SB_PWM_AFC_CTRL_MASK,
1362 FIELD_PREP(SB_PWM_AFC_CTRL_MASK, 0x5));
1363 regmap_update_bits(hdptx->regmap, SB_REG(011f), SB_RCAL_RSTN_MASK,
1364 FIELD_PREP(SB_RCAL_RSTN_MASK, 0x1));
1365 regmap_update_bits(hdptx->regmap, SB_REG(0120), SB_AUX_EN_IN_MASK,
1366 FIELD_PREP(SB_AUX_EN_IN_MASK, 0x1));
1367
1368 regmap_update_bits(hdptx->regmap, SB_REG(0102), OVRD_SB_RXTERM_EN_MASK,
1369 FIELD_PREP(OVRD_SB_RXTERM_EN_MASK, 0x1));
1370 regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK,
1371 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 0x1));
1372 regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_EN_MASK,
1373 FIELD_PREP(OVRD_SB_EN_MASK, 0x1));
1374 regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_AUX_EN_MASK,
1375 FIELD_PREP(OVRD_SB_AUX_EN_MASK, 0x1));
1376
1377 regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_EN_MASK,
1378 FIELD_PREP(OVRD_SB_VREG_EN_MASK, 0x1));
1379
1380 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1381 HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x1));
1382 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1383 HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x1));
1384 usleep_range(20, 25);
1385
1386 reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
1387 usleep_range(20, 25);
1388 reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
1389 usleep_range(20, 25);
1390
1391 regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK,
1392 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 0x1));
1393 usleep_range(100, 110);
1394 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_EN_MASK,
1395 FIELD_PREP(SB_EN_MASK, 0x1));
1396 usleep_range(100, 110);
1397 regmap_update_bits(hdptx->regmap, SB_REG(0102), SB_RXTERM_EN_MASK,
1398 FIELD_PREP(SB_RXTERM_EN_MASK, 0x1));
1399 usleep_range(20, 25);
1400 regmap_update_bits(hdptx->regmap, SB_REG(010f), SB_VREG_EN_MASK,
1401 FIELD_PREP(SB_VREG_EN_MASK, 0x1));
1402 usleep_range(20, 25);
1403 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_AUX_EN_MASK,
1404 FIELD_PREP(SB_AUX_EN_MASK, 0x1));
1405 usleep_range(100, 110);
1406
1407 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS,
1408 status, FIELD_GET(HDPTX_O_SB_RDY, status),
1409 50, 1000);
1410 if (ret) {
1411 dev_err(hdptx->dev, "Failed to get phy sb ready: %d\n", ret);
1412 return ret;
1413 }
1414
1415 return 0;
1416 }
1417
rk_hdptx_phy_power_on(struct phy * phy)1418 static int rk_hdptx_phy_power_on(struct phy *phy)
1419 {
1420 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
1421 enum phy_mode mode = phy_get_mode(phy);
1422 int ret, lane;
1423
1424 if (mode != PHY_MODE_DP) {
1425 if (!hdptx->hdmi_cfg.tmds_char_rate) {
1426 /*
1427 * FIXME: Temporary workaround to setup TMDS char rate
1428 * from the RK DW HDMI QP bridge driver.
1429 * Will be removed as soon the switch to the HDMI PHY
1430 * configuration API has been completed on both ends.
1431 */
1432 hdptx->hdmi_cfg.tmds_char_rate = phy_get_bus_width(hdptx->phy) & 0xfffffff;
1433 hdptx->hdmi_cfg.tmds_char_rate *= 100;
1434 }
1435
1436 dev_dbg(hdptx->dev, "%s rate=%llu bpc=%u\n", __func__,
1437 hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc);
1438 }
1439
1440 ret = rk_hdptx_phy_consumer_get(hdptx);
1441 if (ret)
1442 return ret;
1443
1444 if (mode == PHY_MODE_DP) {
1445 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1446 HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x1));
1447
1448 for (lane = 0; lane < 4; lane++) {
1449 regmap_update_bits(hdptx->regmap, LANE_REG(031e) + 0x400 * lane,
1450 LN_POLARITY_INV_MASK | LN_LANE_MODE_MASK,
1451 FIELD_PREP(LN_POLARITY_INV_MASK, 0) |
1452 FIELD_PREP(LN_LANE_MODE_MASK, 1));
1453 }
1454
1455 regmap_update_bits(hdptx->regmap, LNTOP_REG(0200), PROTOCOL_SEL_MASK,
1456 FIELD_PREP(PROTOCOL_SEL_MASK, 0x0));
1457 regmap_update_bits(hdptx->regmap, LNTOP_REG(0206), DATA_BUS_WIDTH_MASK,
1458 FIELD_PREP(DATA_BUS_WIDTH_MASK, 0x1));
1459 regmap_update_bits(hdptx->regmap, LNTOP_REG(0206), DATA_BUS_WIDTH_SEL_MASK,
1460 FIELD_PREP(DATA_BUS_WIDTH_SEL_MASK, 0x0));
1461
1462 rk_hdptx_dp_pll_init(hdptx);
1463
1464 ret = rk_hdptx_dp_aux_init(hdptx);
1465 if (ret)
1466 rk_hdptx_phy_consumer_put(hdptx, true);
1467 } else {
1468 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1469 HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0));
1470
1471 ret = rk_hdptx_ropll_tmds_mode_config(hdptx);
1472 if (ret)
1473 rk_hdptx_phy_consumer_put(hdptx, true);
1474 }
1475
1476 return ret;
1477 }
1478
rk_hdptx_phy_power_off(struct phy * phy)1479 static int rk_hdptx_phy_power_off(struct phy *phy)
1480 {
1481 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
1482
1483 return rk_hdptx_phy_consumer_put(hdptx, false);
1484 }
1485
rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy * hdptx,struct phy_configure_opts_hdmi * hdmi)1486 static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx,
1487 struct phy_configure_opts_hdmi *hdmi)
1488 {
1489 int i;
1490
1491 if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE)
1492 return -EINVAL;
1493
1494 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
1495 if (hdmi->tmds_char_rate == ropll_tmds_cfg[i].rate)
1496 break;
1497
1498 if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
1499 !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL))
1500 return -EINVAL;
1501
1502 if (!hdmi->bpc)
1503 hdmi->bpc = 8;
1504
1505 switch (hdmi->bpc) {
1506 case 8:
1507 case 10:
1508 case 12:
1509 case 16:
1510 break;
1511 default:
1512 return -EINVAL;
1513 }
1514
1515 return 0;
1516 }
1517
rk_hdptx_phy_verify_dp_config(struct rk_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)1518 static int rk_hdptx_phy_verify_dp_config(struct rk_hdptx_phy *hdptx,
1519 struct phy_configure_opts_dp *dp)
1520 {
1521 int i;
1522
1523 if (dp->set_rate) {
1524 switch (dp->link_rate) {
1525 case 1620:
1526 case 2700:
1527 case 5400:
1528 break;
1529 default:
1530 return -EINVAL;
1531 }
1532 }
1533
1534 if (dp->set_lanes) {
1535 switch (dp->lanes) {
1536 case 1:
1537 case 2:
1538 case 4:
1539 break;
1540 default:
1541 return -EINVAL;
1542 }
1543 }
1544
1545 if (dp->set_voltages) {
1546 for (i = 0; i < hdptx->lanes; i++) {
1547 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
1548 return -EINVAL;
1549
1550 if (dp->voltage[i] + dp->pre[i] > 3)
1551 return -EINVAL;
1552 }
1553 }
1554
1555 return 0;
1556 }
1557
rk_hdptx_phy_set_rate(struct rk_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)1558 static int rk_hdptx_phy_set_rate(struct rk_hdptx_phy *hdptx,
1559 struct phy_configure_opts_dp *dp)
1560 {
1561 u32 bw, status;
1562 int ret;
1563
1564 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1565 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0));
1566
1567 switch (dp->link_rate) {
1568 case 1620:
1569 bw = DP_BW_RBR;
1570 break;
1571 case 2700:
1572 bw = DP_BW_HBR;
1573 break;
1574 case 5400:
1575 bw = DP_BW_HBR2;
1576 break;
1577 default:
1578 return -EINVAL;
1579 }
1580 hdptx->link_rate = dp->link_rate;
1581
1582 regmap_update_bits(hdptx->regmap, CMN_REG(0008), OVRD_LCPLL_EN_MASK | LCPLL_EN_MASK,
1583 FIELD_PREP(OVRD_LCPLL_EN_MASK, 0x1) |
1584 FIELD_PREP(LCPLL_EN_MASK, 0x0));
1585
1586 regmap_update_bits(hdptx->regmap, CMN_REG(003d), OVRD_ROPLL_EN_MASK | ROPLL_EN_MASK,
1587 FIELD_PREP(OVRD_ROPLL_EN_MASK, 0x1) |
1588 FIELD_PREP(ROPLL_EN_MASK, 0x1));
1589
1590 if (dp->ssc) {
1591 regmap_update_bits(hdptx->regmap, CMN_REG(0074),
1592 OVRD_ROPLL_SSC_EN_MASK | ROPLL_SSC_EN_MASK,
1593 FIELD_PREP(OVRD_ROPLL_SSC_EN_MASK, 0x1) |
1594 FIELD_PREP(ROPLL_SSC_EN_MASK, 0x1));
1595 regmap_write(hdptx->regmap, CMN_REG(0075),
1596 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION_MASK, 0xc));
1597 regmap_update_bits(hdptx->regmap, CMN_REG(0076),
1598 ANA_ROPLL_SSC_FM_FREQ_MASK,
1599 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ_MASK, 0x1f));
1600
1601 regmap_update_bits(hdptx->regmap, CMN_REG(0099), SSC_EN_MASK,
1602 FIELD_PREP(SSC_EN_MASK, 0x2));
1603 } else {
1604 regmap_update_bits(hdptx->regmap, CMN_REG(0074),
1605 OVRD_ROPLL_SSC_EN_MASK | ROPLL_SSC_EN_MASK,
1606 FIELD_PREP(OVRD_ROPLL_SSC_EN_MASK, 0x1) |
1607 FIELD_PREP(ROPLL_SSC_EN_MASK, 0x0));
1608 regmap_write(hdptx->regmap, CMN_REG(0075),
1609 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION_MASK, 0x20));
1610 regmap_update_bits(hdptx->regmap, CMN_REG(0076),
1611 ANA_ROPLL_SSC_FM_FREQ_MASK,
1612 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ_MASK, 0xc));
1613
1614 regmap_update_bits(hdptx->regmap, CMN_REG(0099), SSC_EN_MASK,
1615 FIELD_PREP(SSC_EN_MASK, 0x0));
1616 }
1617
1618 regmap_update_bits(hdptx->regmap, CMN_REG(0095), DP_TX_LINK_BW_MASK,
1619 FIELD_PREP(DP_TX_LINK_BW_MASK, bw));
1620
1621 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1622 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x1));
1623
1624 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS,
1625 status, FIELD_GET(HDPTX_O_PLL_LOCK_DONE, status),
1626 50, 1000);
1627 if (ret) {
1628 dev_err(hdptx->dev, "Failed to get phy pll lock: %d\n", ret);
1629 return ret;
1630 }
1631
1632 return 0;
1633 }
1634
rk_hdptx_phy_set_lanes(struct rk_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)1635 static int rk_hdptx_phy_set_lanes(struct rk_hdptx_phy *hdptx,
1636 struct phy_configure_opts_dp *dp)
1637 {
1638 hdptx->lanes = dp->lanes;
1639
1640 regmap_update_bits(hdptx->regmap, LNTOP_REG(0207), LANE_EN_MASK,
1641 FIELD_PREP(LANE_EN_MASK, GENMASK(hdptx->lanes - 1, 0)));
1642
1643 return 0;
1644 }
1645
rk_hdptx_phy_set_voltage(struct rk_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp,u8 lane)1646 static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
1647 struct phy_configure_opts_dp *dp,
1648 u8 lane)
1649 {
1650 const struct tx_drv_ctrl *ctrl;
1651 u32 offset = lane * 0x400;
1652
1653 switch (hdptx->link_rate) {
1654 case 1620:
1655 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]];
1656 regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
1657 LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
1658 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
1659 ctrl->tx_jeq_even_ctrl));
1660 regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset,
1661 LN_TX_JEQ_ODD_CTRL_RBR_MASK,
1662 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK,
1663 ctrl->tx_jeq_odd_ctrl));
1664 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
1665 LN_TX_SER_40BIT_EN_RBR_MASK,
1666 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1));
1667 break;
1668 case 2700:
1669 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]];
1670 regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
1671 LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
1672 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
1673 ctrl->tx_jeq_even_ctrl));
1674 regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
1675 LN_TX_JEQ_ODD_CTRL_HBR_MASK,
1676 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK,
1677 ctrl->tx_jeq_odd_ctrl));
1678 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
1679 LN_TX_SER_40BIT_EN_HBR_MASK,
1680 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1));
1681 break;
1682 case 5400:
1683 default:
1684 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]];
1685 regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
1686 LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
1687 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
1688 ctrl->tx_jeq_even_ctrl));
1689 regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
1690 LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
1691 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
1692 ctrl->tx_jeq_odd_ctrl));
1693 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
1694 LN_TX_SER_40BIT_EN_HBR2_MASK,
1695 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1));
1696 break;
1697 }
1698
1699 regmap_update_bits(hdptx->regmap, LANE_REG(0303) + offset,
1700 OVRD_LN_TX_DRV_LVL_CTRL_MASK | LN_TX_DRV_LVL_CTRL_MASK,
1701 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL_MASK, 0x1) |
1702 FIELD_PREP(LN_TX_DRV_LVL_CTRL_MASK,
1703 ctrl->tx_drv_lvl_ctrl));
1704 regmap_update_bits(hdptx->regmap, LANE_REG(0304) + offset,
1705 OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK |
1706 LN_TX_DRV_POST_LVL_CTRL_MASK,
1707 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK, 0x1) |
1708 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK,
1709 ctrl->tx_drv_post_lvl_ctrl));
1710 regmap_update_bits(hdptx->regmap, LANE_REG(0305) + offset,
1711 OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK |
1712 LN_TX_DRV_PRE_LVL_CTRL_MASK,
1713 FIELD_PREP(OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK, 0x1) |
1714 FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK,
1715 ctrl->tx_drv_pre_lvl_ctrl));
1716 regmap_update_bits(hdptx->regmap, LANE_REG(0306) + offset,
1717 LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK |
1718 LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK |
1719 LN_ANA_TX_DRV_ACCDRV_EN_MASK,
1720 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK,
1721 ctrl->ana_tx_drv_idrv_idn_ctrl) |
1722 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK,
1723 ctrl->ana_tx_drv_idrv_iup_ctrl) |
1724 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN_MASK,
1725 ctrl->ana_tx_drv_accdrv_en));
1726 regmap_update_bits(hdptx->regmap, LANE_REG(0307) + offset,
1727 LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK |
1728 LN_ANA_TX_DRV_ACCDRV_CTRL_MASK,
1729 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK, 0x1) |
1730 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL_MASK,
1731 ctrl->ana_tx_drv_accdrv_ctrl));
1732
1733 regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
1734 LN_ANA_TX_JEQ_EN_MASK,
1735 FIELD_PREP(LN_ANA_TX_JEQ_EN_MASK, ctrl->ana_tx_jeq_en));
1736
1737 regmap_update_bits(hdptx->regmap, LANE_REG(0310) + offset,
1738 LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK,
1739 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK, 0x3));
1740
1741 regmap_update_bits(hdptx->regmap, LANE_REG(0316) + offset,
1742 LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK,
1743 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK, 0x2));
1744
1745 regmap_update_bits(hdptx->regmap, LANE_REG(031b) + offset,
1746 LN_ANA_TX_RESERVED_MASK,
1747 FIELD_PREP(LN_ANA_TX_RESERVED_MASK, 0x1));
1748 }
1749
rk_hdptx_phy_set_voltages(struct rk_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)1750 static int rk_hdptx_phy_set_voltages(struct rk_hdptx_phy *hdptx,
1751 struct phy_configure_opts_dp *dp)
1752 {
1753 u8 lane;
1754 u32 status;
1755 int ret;
1756
1757 for (lane = 0; lane < hdptx->lanes; lane++)
1758 rk_hdptx_phy_set_voltage(hdptx, dp, lane);
1759
1760 reset_control_deassert(hdptx->rsts[RST_LANE].rstc);
1761
1762 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS,
1763 status, FIELD_GET(HDPTX_O_PHY_RDY, status),
1764 50, 5000);
1765 if (ret) {
1766 dev_err(hdptx->dev, "Failed to get phy ready: %d\n", ret);
1767 return ret;
1768 }
1769
1770 return 0;
1771 }
1772
rk_hdptx_phy_configure(struct phy * phy,union phy_configure_opts * opts)1773 static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opts)
1774 {
1775 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
1776 enum phy_mode mode = phy_get_mode(phy);
1777 int ret;
1778
1779 if (mode != PHY_MODE_DP) {
1780 ret = rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi);
1781 if (ret) {
1782 dev_err(hdptx->dev, "invalid hdmi params for phy configure\n");
1783 } else {
1784 hdptx->hdmi_cfg = opts->hdmi;
1785 hdptx->restrict_rate_change = true;
1786 }
1787
1788 dev_dbg(hdptx->dev, "%s rate=%llu bpc=%u\n", __func__,
1789 hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc);
1790 return ret;
1791 }
1792
1793 ret = rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp);
1794 if (ret) {
1795 dev_err(hdptx->dev, "invalid dp params for phy configure\n");
1796 return ret;
1797 }
1798
1799 if (opts->dp.set_rate) {
1800 ret = rk_hdptx_phy_set_rate(hdptx, &opts->dp);
1801 if (ret) {
1802 dev_err(hdptx->dev, "failed to set rate: %d\n", ret);
1803 return ret;
1804 }
1805 }
1806
1807 if (opts->dp.set_lanes) {
1808 ret = rk_hdptx_phy_set_lanes(hdptx, &opts->dp);
1809 if (ret) {
1810 dev_err(hdptx->dev, "failed to set lanes: %d\n", ret);
1811 return ret;
1812 }
1813 }
1814
1815 if (opts->dp.set_voltages) {
1816 ret = rk_hdptx_phy_set_voltages(hdptx, &opts->dp);
1817 if (ret) {
1818 dev_err(hdptx->dev, "failed to set voltages: %d\n",
1819 ret);
1820 return ret;
1821 }
1822 }
1823
1824 return 0;
1825 }
1826
rk_hdptx_phy_validate(struct phy * phy,enum phy_mode mode,int submode,union phy_configure_opts * opts)1827 static int rk_hdptx_phy_validate(struct phy *phy, enum phy_mode mode,
1828 int submode, union phy_configure_opts *opts)
1829 {
1830 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
1831
1832 if (mode != PHY_MODE_DP)
1833 return rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi);
1834
1835 return rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp);
1836 }
1837
1838 static const struct phy_ops rk_hdptx_phy_ops = {
1839 .power_on = rk_hdptx_phy_power_on,
1840 .power_off = rk_hdptx_phy_power_off,
1841 .configure = rk_hdptx_phy_configure,
1842 .validate = rk_hdptx_phy_validate,
1843 .owner = THIS_MODULE,
1844 };
1845
to_rk_hdptx_phy(struct clk_hw * hw)1846 static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw)
1847 {
1848 return container_of(hw, struct rk_hdptx_phy, hw);
1849 }
1850
rk_hdptx_phy_clk_prepare(struct clk_hw * hw)1851 static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw)
1852 {
1853 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1854
1855 return rk_hdptx_phy_consumer_get(hdptx);
1856 }
1857
rk_hdptx_phy_clk_unprepare(struct clk_hw * hw)1858 static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
1859 {
1860 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1861
1862 rk_hdptx_phy_consumer_put(hdptx, true);
1863 }
1864
rk_hdptx_phy_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1865 static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
1866 unsigned long parent_rate)
1867 {
1868 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1869
1870 return hdptx->hw_rate;
1871 }
1872
rk_hdptx_phy_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)1873 static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1874 unsigned long *parent_rate)
1875 {
1876 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1877
1878 /*
1879 * FIXME: Temporarily allow altering TMDS char rate via CCF.
1880 * To be dropped as soon as the RK DW HDMI QP bridge driver
1881 * switches to make use of phy_configure().
1882 */
1883 if (!hdptx->restrict_rate_change && rate != hdptx->hdmi_cfg.tmds_char_rate) {
1884 struct phy_configure_opts_hdmi hdmi = {
1885 .tmds_char_rate = rate,
1886 };
1887 int ret = rk_hdptx_phy_verify_hdmi_config(hdptx, &hdmi);
1888
1889 if (ret)
1890 return ret;
1891
1892 hdptx->hdmi_cfg = hdmi;
1893 }
1894
1895 /*
1896 * The TMDS char rate shall be adjusted via phy_configure() only,
1897 * hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with
1898 * a different rate argument.
1899 */
1900 return DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8, hdptx->hdmi_cfg.bpc);
1901 }
1902
rk_hdptx_phy_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1903 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1904 unsigned long parent_rate)
1905 {
1906 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1907 unsigned long long tmds_rate = DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi_cfg.bpc, 8);
1908
1909 /* Revert any unlikely TMDS char rate change since round_rate() */
1910 if (hdptx->hdmi_cfg.tmds_char_rate != tmds_rate) {
1911 dev_warn(hdptx->dev, "Reverting unexpected rate change from %llu to %llu\n",
1912 tmds_rate, hdptx->hdmi_cfg.tmds_char_rate);
1913 hdptx->hdmi_cfg.tmds_char_rate = tmds_rate;
1914 }
1915
1916 /*
1917 * The TMDS char rate would be normally programmed in HW during
1918 * phy_ops.power_on() or clk_ops.prepare() callbacks, but it might
1919 * happen that the former gets fired too late, i.e. after this call,
1920 * while the latter being executed only once, i.e. when clock remains
1921 * in the prepared state during rate changes.
1922 */
1923 return rk_hdptx_ropll_tmds_cmn_config(hdptx);
1924 }
1925
1926 static const struct clk_ops hdptx_phy_clk_ops = {
1927 .prepare = rk_hdptx_phy_clk_prepare,
1928 .unprepare = rk_hdptx_phy_clk_unprepare,
1929 .recalc_rate = rk_hdptx_phy_clk_recalc_rate,
1930 .round_rate = rk_hdptx_phy_clk_round_rate,
1931 .set_rate = rk_hdptx_phy_clk_set_rate,
1932 };
1933
rk_hdptx_phy_clk_register(struct rk_hdptx_phy * hdptx)1934 static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx)
1935 {
1936 struct device *dev = hdptx->dev;
1937 const char *name, *pname;
1938 struct clk *refclk;
1939 int ret;
1940
1941 refclk = devm_clk_get(dev, "ref");
1942 if (IS_ERR(refclk))
1943 return dev_err_probe(dev, PTR_ERR(refclk),
1944 "Failed to get ref clock\n");
1945
1946 name = hdptx->phy_id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0";
1947 pname = __clk_get_name(refclk);
1948
1949 hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops,
1950 CLK_GET_RATE_NOCACHE);
1951
1952 ret = devm_clk_hw_register(dev, &hdptx->hw);
1953 if (ret)
1954 return dev_err_probe(dev, ret, "Failed to register clock\n");
1955
1956 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw);
1957 if (ret)
1958 return dev_err_probe(dev, ret,
1959 "Failed to register clk provider\n");
1960 return 0;
1961 }
1962
rk_hdptx_phy_runtime_suspend(struct device * dev)1963 static int rk_hdptx_phy_runtime_suspend(struct device *dev)
1964 {
1965 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
1966
1967 clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks);
1968
1969 return 0;
1970 }
1971
rk_hdptx_phy_runtime_resume(struct device * dev)1972 static int rk_hdptx_phy_runtime_resume(struct device *dev)
1973 {
1974 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
1975 int ret;
1976
1977 ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks);
1978 if (ret)
1979 dev_err(hdptx->dev, "Failed to enable clocks: %d\n", ret);
1980
1981 return ret;
1982 }
1983
rk_hdptx_phy_probe(struct platform_device * pdev)1984 static int rk_hdptx_phy_probe(struct platform_device *pdev)
1985 {
1986 const struct rk_hdptx_phy_cfg *cfgs;
1987 struct phy_provider *phy_provider;
1988 struct device *dev = &pdev->dev;
1989 struct rk_hdptx_phy *hdptx;
1990 struct resource *res;
1991 void __iomem *regs;
1992 int ret, id;
1993
1994 hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL);
1995 if (!hdptx)
1996 return -ENOMEM;
1997
1998 hdptx->dev = dev;
1999 hdptx->hdmi_cfg.bpc = 8;
2000
2001 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2002 if (IS_ERR(regs))
2003 return dev_err_probe(dev, PTR_ERR(regs),
2004 "Failed to ioremap resource\n");
2005
2006 cfgs = device_get_match_data(dev);
2007 if (!cfgs)
2008 return dev_err_probe(dev, -EINVAL, "missing match data\n");
2009
2010 /* find the phy-id from the io address */
2011 hdptx->phy_id = -ENODEV;
2012 for (id = 0; id < cfgs->num_phys; id++) {
2013 if (res->start == cfgs->phy_ids[id]) {
2014 hdptx->phy_id = id;
2015 break;
2016 }
2017 }
2018
2019 if (hdptx->phy_id < 0)
2020 return dev_err_probe(dev, -ENODEV, "no matching device found\n");
2021
2022 ret = devm_clk_bulk_get_all(dev, &hdptx->clks);
2023 if (ret < 0)
2024 return dev_err_probe(dev, ret, "Failed to get clocks\n");
2025 if (ret == 0)
2026 return dev_err_probe(dev, -EINVAL, "Missing clocks\n");
2027
2028 hdptx->nr_clks = ret;
2029
2030 hdptx->regmap = devm_regmap_init_mmio(dev, regs,
2031 &rk_hdptx_phy_regmap_config);
2032 if (IS_ERR(hdptx->regmap))
2033 return dev_err_probe(dev, PTR_ERR(hdptx->regmap),
2034 "Failed to init regmap\n");
2035
2036 hdptx->rsts[RST_APB].id = "apb";
2037 hdptx->rsts[RST_INIT].id = "init";
2038 hdptx->rsts[RST_CMN].id = "cmn";
2039 hdptx->rsts[RST_LANE].id = "lane";
2040
2041 ret = devm_reset_control_bulk_get_exclusive(dev, RST_MAX, hdptx->rsts);
2042 if (ret)
2043 return dev_err_probe(dev, ret, "Failed to get resets\n");
2044
2045 hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
2046 "rockchip,grf");
2047 if (IS_ERR(hdptx->grf))
2048 return dev_err_probe(dev, PTR_ERR(hdptx->grf),
2049 "Could not get GRF syscon\n");
2050
2051 platform_set_drvdata(pdev, hdptx);
2052
2053 ret = devm_pm_runtime_enable(dev);
2054 if (ret)
2055 return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
2056
2057 hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops);
2058 if (IS_ERR(hdptx->phy))
2059 return dev_err_probe(dev, PTR_ERR(hdptx->phy),
2060 "Failed to create HDMI PHY\n");
2061
2062 phy_set_drvdata(hdptx->phy, hdptx);
2063 phy_set_bus_width(hdptx->phy, 8);
2064
2065 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2066 if (IS_ERR(phy_provider))
2067 return dev_err_probe(dev, PTR_ERR(phy_provider),
2068 "Failed to register PHY provider\n");
2069
2070 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
2071 reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
2072 reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
2073
2074 return rk_hdptx_phy_clk_register(hdptx);
2075 }
2076
2077 static const struct dev_pm_ops rk_hdptx_phy_pm_ops = {
2078 RUNTIME_PM_OPS(rk_hdptx_phy_runtime_suspend,
2079 rk_hdptx_phy_runtime_resume, NULL)
2080 };
2081
2082 static const struct rk_hdptx_phy_cfg rk3576_hdptx_phy_cfgs = {
2083 .num_phys = 1,
2084 .phy_ids = {
2085 0x2b000000,
2086 },
2087 };
2088
2089 static const struct rk_hdptx_phy_cfg rk3588_hdptx_phy_cfgs = {
2090 .num_phys = 2,
2091 .phy_ids = {
2092 0xfed60000,
2093 0xfed70000,
2094 },
2095 };
2096
2097 static const struct of_device_id rk_hdptx_phy_of_match[] = {
2098 {
2099 .compatible = "rockchip,rk3576-hdptx-phy",
2100 .data = &rk3576_hdptx_phy_cfgs
2101 },
2102 {
2103 .compatible = "rockchip,rk3588-hdptx-phy",
2104 .data = &rk3588_hdptx_phy_cfgs
2105 },
2106 {}
2107 };
2108 MODULE_DEVICE_TABLE(of, rk_hdptx_phy_of_match);
2109
2110 static struct platform_driver rk_hdptx_phy_driver = {
2111 .probe = rk_hdptx_phy_probe,
2112 .driver = {
2113 .name = "rockchip-hdptx-phy",
2114 .pm = &rk_hdptx_phy_pm_ops,
2115 .of_match_table = rk_hdptx_phy_of_match,
2116 },
2117 };
2118 module_platform_driver(rk_hdptx_phy_driver);
2119
2120 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
2121 MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>");
2122 MODULE_AUTHOR("Damon Ding <damon.ding@rock-chips.com>");
2123 MODULE_DESCRIPTION("Samsung HDMI/eDP Transmitter Combo PHY Driver");
2124 MODULE_LICENSE("GPL");
2125