1 /*-
2 * Copyright (c) 2015 Justin Hibbits
3 * Copyright (c) 2005, Joseph Koshy
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29 #include <sys/param.h>
30 #include <sys/pmc.h>
31 #include <sys/pmckern.h>
32 #include <sys/systm.h>
33
34 #include <machine/pmc_mdep.h>
35 #include <machine/cpu.h>
36
37 #include <ddb/ddb.h>
38
39 #include "hwpmc_powerpc.h"
40
41 struct e500_event_code_map {
42 enum pmc_event pe_ev; /* enum value */
43 uint8_t pe_counter_mask; /* Which counter this can be counted in. */
44 uint8_t pe_code; /* numeric code */
45 uint8_t pe_cpu; /* e500 core (v1,v2,mc), mask */
46 };
47
48 #define E500_MAX_PMCS 4
49 #define PMC_PPC_MASK0 0
50 #define PMC_PPC_MASK1 1
51 #define PMC_PPC_MASK2 2
52 #define PMC_PPC_MASK3 3
53 #define PMC_PPC_MASK_ALL 0x0f
54 #define PMC_PPC_E500V1 1
55 #define PMC_PPC_E500V2 2
56 #define PMC_PPC_E500MC 4
57 #define PMC_PPC_E500_ANY 7
58 #define PMC_E500_EVENT(id, mask, number, core) \
59 [PMC_EV_E500_##id - PMC_EV_E500_FIRST] = \
60 { .pe_ev = PMC_EV_E500_##id, .pe_counter_mask = mask, \
61 .pe_code = number, .pe_cpu = core }
62 #define PMC_E500MC_ONLY(id, number) \
63 PMC_E500_EVENT(id, PMC_PPC_MASK_ALL, number, PMC_PPC_E500MC)
64 #define PMC_E500_COMMON(id, number) \
65 PMC_E500_EVENT(id, PMC_PPC_MASK_ALL, number, PMC_PPC_E500_ANY)
66
67 static struct e500_event_code_map e500_event_codes[] = {
68 PMC_E500_COMMON(CYCLES, 1),
69 PMC_E500_COMMON(INSTR_COMPLETED, 2),
70 PMC_E500_COMMON(UOPS_COMPLETED, 3),
71 PMC_E500_COMMON(INSTR_FETCHED, 4),
72 PMC_E500_COMMON(UOPS_DECODED, 5),
73 PMC_E500_COMMON(PM_EVENT_TRANSITIONS, 6),
74 PMC_E500_COMMON(PM_EVENT_CYCLES, 7),
75 PMC_E500_COMMON(BRANCH_INSTRS_COMPLETED, 8),
76 PMC_E500_COMMON(LOAD_UOPS_COMPLETED, 9),
77 PMC_E500_COMMON(STORE_UOPS_COMPLETED, 10),
78 PMC_E500_COMMON(CQ_REDIRECTS, 11),
79 PMC_E500_COMMON(BRANCHES_FINISHED, 12),
80 PMC_E500_COMMON(TAKEN_BRANCHES_FINISHED, 13),
81 PMC_E500_COMMON(FINISHED_UNCOND_BRANCHES_MISS_BTB, 14),
82 PMC_E500_COMMON(BRANCH_MISPRED, 15),
83 PMC_E500_COMMON(BTB_BRANCH_MISPRED_FROM_DIRECTION, 16),
84 PMC_E500_COMMON(BTB_HITS_PSEUDO_HITS, 17),
85 PMC_E500_COMMON(CYCLES_DECODE_STALLED, 18),
86 PMC_E500_COMMON(CYCLES_ISSUE_STALLED, 19),
87 PMC_E500_COMMON(CYCLES_BRANCH_ISSUE_STALLED, 20),
88 PMC_E500_COMMON(CYCLES_SU1_SCHED_STALLED, 21),
89 PMC_E500_COMMON(CYCLES_SU2_SCHED_STALLED, 22),
90 PMC_E500_COMMON(CYCLES_MU_SCHED_STALLED, 23),
91 PMC_E500_COMMON(CYCLES_LRU_SCHED_STALLED, 24),
92 PMC_E500_COMMON(CYCLES_BU_SCHED_STALLED, 25),
93 PMC_E500_COMMON(TOTAL_TRANSLATED, 26),
94 PMC_E500_COMMON(LOADS_TRANSLATED, 27),
95 PMC_E500_COMMON(STORES_TRANSLATED, 28),
96 PMC_E500_COMMON(TOUCHES_TRANSLATED, 29),
97 PMC_E500_COMMON(CACHEOPS_TRANSLATED, 30),
98 PMC_E500_COMMON(CACHE_INHIBITED_ACCESS_TRANSLATED, 31),
99 PMC_E500_COMMON(GUARDED_LOADS_TRANSLATED, 32),
100 PMC_E500_COMMON(WRITE_THROUGH_STORES_TRANSLATED, 33),
101 PMC_E500_COMMON(MISALIGNED_LOAD_STORE_ACCESS_TRANSLATED, 34),
102 PMC_E500_COMMON(TOTAL_ALLOCATED_TO_DLFB, 35),
103 PMC_E500_COMMON(LOADS_TRANSLATED_ALLOCATED_TO_DLFB, 36),
104 PMC_E500_COMMON(STORES_COMPLETED_ALLOCATED_TO_DLFB, 37),
105 PMC_E500_COMMON(TOUCHES_TRANSLATED_ALLOCATED_TO_DLFB, 38),
106 PMC_E500_COMMON(STORES_COMPLETED, 39),
107 PMC_E500_COMMON(DATA_L1_CACHE_LOCKS, 40),
108 PMC_E500_COMMON(DATA_L1_CACHE_RELOADS, 41),
109 PMC_E500_COMMON(DATA_L1_CACHE_CASTOUTS, 42),
110 PMC_E500_COMMON(LOAD_MISS_DLFB_FULL, 43),
111 PMC_E500_COMMON(LOAD_MISS_LDQ_FULL, 44),
112 PMC_E500_COMMON(LOAD_GUARDED_MISS, 45),
113 PMC_E500_COMMON(STORE_TRANSLATE_WHEN_QUEUE_FULL, 46),
114 PMC_E500_COMMON(ADDRESS_COLLISION, 47),
115 PMC_E500_COMMON(DATA_MMU_MISS, 48),
116 PMC_E500_COMMON(DATA_MMU_BUSY, 49),
117 PMC_E500_COMMON(PART2_MISALIGNED_CACHE_ACCESS, 50),
118 PMC_E500_COMMON(LOAD_MISS_DLFB_FULL_CYCLES, 51),
119 PMC_E500_COMMON(LOAD_MISS_LDQ_FULL_CYCLES, 52),
120 PMC_E500_COMMON(LOAD_GUARDED_MISS_CYCLES, 53),
121 PMC_E500_COMMON(STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLES, 54),
122 PMC_E500_COMMON(ADDRESS_COLLISION_CYCLES, 55),
123 PMC_E500_COMMON(DATA_MMU_MISS_CYCLES, 56),
124 PMC_E500_COMMON(DATA_MMU_BUSY_CYCLES, 57),
125 PMC_E500_COMMON(PART2_MISALIGNED_CACHE_ACCESS_CYCLES, 58),
126 PMC_E500_COMMON(INSTR_L1_CACHE_LOCKS, 59),
127 PMC_E500_COMMON(INSTR_L1_CACHE_RELOADS, 60),
128 PMC_E500_COMMON(INSTR_L1_CACHE_FETCHES, 61),
129 PMC_E500_COMMON(INSTR_MMU_TLB4K_RELOADS, 62),
130 PMC_E500_COMMON(INSTR_MMU_VSP_RELOADS, 63),
131 PMC_E500_COMMON(DATA_MMU_TLB4K_RELOADS, 64),
132 PMC_E500_COMMON(DATA_MMU_VSP_RELOADS, 65),
133 PMC_E500_COMMON(L2MMU_MISSES, 66),
134 PMC_E500_COMMON(BIU_MASTER_REQUESTS, 67),
135 PMC_E500_COMMON(BIU_MASTER_INSTR_SIDE_REQUESTS, 68),
136 PMC_E500_COMMON(BIU_MASTER_DATA_SIDE_REQUESTS, 69),
137 PMC_E500_COMMON(BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTS, 70),
138 PMC_E500_COMMON(BIU_MASTER_RETRIES, 71),
139 PMC_E500_COMMON(SNOOP_REQUESTS, 72),
140 PMC_E500_COMMON(SNOOP_HITS, 73),
141 PMC_E500_COMMON(SNOOP_PUSHES, 74),
142 PMC_E500_COMMON(SNOOP_RETRIES, 75),
143 PMC_E500_EVENT(DLFB_LOAD_MISS_CYCLES, PMC_PPC_MASK0|PMC_PPC_MASK1,
144 76, PMC_PPC_E500_ANY),
145 PMC_E500_EVENT(ILFB_FETCH_MISS_CYCLES, PMC_PPC_MASK0|PMC_PPC_MASK1,
146 77, PMC_PPC_E500_ANY),
147 PMC_E500_EVENT(EXT_INPU_INTR_LATENCY_CYCLES, PMC_PPC_MASK0|PMC_PPC_MASK1,
148 78, PMC_PPC_E500_ANY),
149 PMC_E500_EVENT(CRIT_INPUT_INTR_LATENCY_CYCLES, PMC_PPC_MASK0|PMC_PPC_MASK1,
150 79, PMC_PPC_E500_ANY),
151 PMC_E500_EVENT(EXT_INPUT_INTR_PENDING_LATENCY_CYCLES,
152 PMC_PPC_MASK0|PMC_PPC_MASK1, 80, PMC_PPC_E500_ANY),
153 PMC_E500_EVENT(CRIT_INPUT_INTR_PENDING_LATENCY_CYCLES,
154 PMC_PPC_MASK0|PMC_PPC_MASK1, 81, PMC_PPC_E500_ANY),
155 PMC_E500_COMMON(PMC0_OVERFLOW, 82),
156 PMC_E500_COMMON(PMC1_OVERFLOW, 83),
157 PMC_E500_COMMON(PMC2_OVERFLOW, 84),
158 PMC_E500_COMMON(PMC3_OVERFLOW, 85),
159 PMC_E500_COMMON(INTERRUPTS_TAKEN, 86),
160 PMC_E500_COMMON(EXT_INPUT_INTR_TAKEN, 87),
161 PMC_E500_COMMON(CRIT_INPUT_INTR_TAKEN, 88),
162 PMC_E500_COMMON(SYSCALL_TRAP_INTR, 89),
163 PMC_E500_EVENT(TLB_BIT_TRANSITIONS, PMC_PPC_MASK_ALL, 90,
164 PMC_PPC_E500V2 | PMC_PPC_E500MC),
165 PMC_E500MC_ONLY(L2_LINEFILL_BUFFER, 91),
166 PMC_E500MC_ONLY(LV2_VS, 92),
167 PMC_E500MC_ONLY(CASTOUTS_RELEASED, 93),
168 PMC_E500MC_ONLY(INTV_ALLOCATIONS, 94),
169 PMC_E500MC_ONLY(DLFB_RETRIES_TO_MBAR, 95),
170 PMC_E500MC_ONLY(STORE_RETRIES, 96),
171 PMC_E500MC_ONLY(STASH_L1_HITS, 97),
172 PMC_E500MC_ONLY(STASH_L2_HITS, 98),
173 PMC_E500MC_ONLY(STASH_BUSY_1, 99),
174 PMC_E500MC_ONLY(STASH_BUSY_2, 100),
175 PMC_E500MC_ONLY(STASH_BUSY_3, 101),
176 PMC_E500MC_ONLY(STASH_HITS, 102),
177 PMC_E500MC_ONLY(STASH_HIT_DLFB, 103),
178 PMC_E500MC_ONLY(STASH_REQUESTS, 106),
179 PMC_E500MC_ONLY(STASH_REQUESTS_L1, 107),
180 PMC_E500MC_ONLY(STASH_REQUESTS_L2, 108),
181 PMC_E500MC_ONLY(STALLS_NO_CAQ_OR_COB, 109),
182 PMC_E500MC_ONLY(L2_CACHE_ACCESSES, 110),
183 PMC_E500MC_ONLY(L2_HIT_CACHE_ACCESSES, 111),
184 PMC_E500MC_ONLY(L2_CACHE_DATA_ACCESSES, 112),
185 PMC_E500MC_ONLY(L2_CACHE_DATA_HITS, 113),
186 PMC_E500MC_ONLY(L2_CACHE_INSTR_ACCESSES, 114),
187 PMC_E500MC_ONLY(L2_CACHE_INSTR_HITS, 115),
188 PMC_E500MC_ONLY(L2_CACHE_ALLOCATIONS, 116),
189 PMC_E500MC_ONLY(L2_CACHE_DATA_ALLOCATIONS, 117),
190 PMC_E500MC_ONLY(L2_CACHE_DIRTY_DATA_ALLOCATIONS, 118),
191 PMC_E500MC_ONLY(L2_CACHE_INSTR_ALLOCATIONS, 119),
192 PMC_E500MC_ONLY(L2_CACHE_UPDATES, 120),
193 PMC_E500MC_ONLY(L2_CACHE_CLEAN_UPDATES, 121),
194 PMC_E500MC_ONLY(L2_CACHE_DIRTY_UPDATES, 122),
195 PMC_E500MC_ONLY(L2_CACHE_CLEAN_REDUNDANT_UPDATES, 123),
196 PMC_E500MC_ONLY(L2_CACHE_DIRTY_REDUNDANT_UPDATES, 124),
197 PMC_E500MC_ONLY(L2_CACHE_LOCKS, 125),
198 PMC_E500MC_ONLY(L2_CACHE_CASTOUTS, 126),
199 PMC_E500MC_ONLY(L2_CACHE_DATA_DIRTY_HITS, 127),
200 PMC_E500MC_ONLY(INSTR_LFB_WENT_HIGH_PRIORITY, 128),
201 PMC_E500MC_ONLY(SNOOP_THROTTLING_TURNED_ON, 129),
202 PMC_E500MC_ONLY(L2_CLEAN_LINE_INVALIDATIONS, 130),
203 PMC_E500MC_ONLY(L2_INCOHERENT_LINE_INVALIDATIONS, 131),
204 PMC_E500MC_ONLY(L2_COHERENT_LINE_INVALIDATIONS, 132),
205 PMC_E500MC_ONLY(COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHES, 133),
206 PMC_E500MC_ONLY(IAC1S_DETECTED, 140),
207 PMC_E500MC_ONLY(IAC2S_DETECTED, 141),
208 PMC_E500MC_ONLY(DAC1S_DTECTED, 144),
209 PMC_E500MC_ONLY(DAC2S_DTECTED, 145),
210 PMC_E500MC_ONLY(DVT0_DETECTED, 148),
211 PMC_E500MC_ONLY(DVT1_DETECTED, 149),
212 PMC_E500MC_ONLY(DVT2_DETECTED, 150),
213 PMC_E500MC_ONLY(DVT3_DETECTED, 151),
214 PMC_E500MC_ONLY(DVT4_DETECTED, 152),
215 PMC_E500MC_ONLY(DVT5_DETECTED, 153),
216 PMC_E500MC_ONLY(DVT6_DETECTED, 154),
217 PMC_E500MC_ONLY(DVT7_DETECTED, 155),
218 PMC_E500MC_ONLY(CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULL, 156),
219 PMC_E500MC_ONLY(FPU_DOUBLE_PUMP, 160),
220 PMC_E500MC_ONLY(FPU_FINISH, 161),
221 PMC_E500MC_ONLY(FPU_DIVIDE_CYCLES, 162),
222 PMC_E500MC_ONLY(FPU_DENORM_INPUT_CYCLES, 163),
223 PMC_E500MC_ONLY(FPU_RESULT_STALL_CYCLES, 164),
224 PMC_E500MC_ONLY(FPU_FPSCR_FULL_STALL, 165),
225 PMC_E500MC_ONLY(FPU_PIPE_SYNC_STALLS, 166),
226 PMC_E500MC_ONLY(FPU_INPUT_DATA_STALLS, 167),
227 PMC_E500MC_ONLY(DECORATED_LOADS, 176),
228 PMC_E500MC_ONLY(DECORATED_STORES, 177),
229 PMC_E500MC_ONLY(LOAD_RETRIES, 178),
230 PMC_E500MC_ONLY(STWCX_SUCCESSES, 179),
231 PMC_E500MC_ONLY(STWCX_FAILURES, 180),
232 };
233
234 static pmc_value_t
e500_pmcn_read(unsigned int pmc)235 e500_pmcn_read(unsigned int pmc)
236 {
237 switch (pmc) {
238 case 0:
239 return (mfpmr(PMR_PMC0));
240 case 1:
241 return (mfpmr(PMR_PMC1));
242 case 2:
243 return (mfpmr(PMR_PMC2));
244 case 3:
245 return (mfpmr(PMR_PMC3));
246 default:
247 panic("Invalid PMC number: %d\n", pmc);
248 }
249 }
250
251 static void
e500_pmcn_write(unsigned int pmc,uint32_t val)252 e500_pmcn_write(unsigned int pmc, uint32_t val)
253 {
254 switch (pmc) {
255 case 0:
256 mtpmr(PMR_PMC0, val);
257 break;
258 case 1:
259 mtpmr(PMR_PMC1, val);
260 break;
261 case 2:
262 mtpmr(PMR_PMC2, val);
263 break;
264 case 3:
265 mtpmr(PMR_PMC3, val);
266 break;
267 default:
268 panic("Invalid PMC number: %d\n", pmc);
269 }
270 }
271
272 static void
e500_set_pmc(int cpu,int ri,int config)273 e500_set_pmc(int cpu, int ri, int config)
274 {
275 struct pmc *pm;
276 struct pmc_hw *phw;
277 register_t pmc_pmlc;
278
279 phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
280 pm = phw->phw_pmc;
281 config &= ~POWERPC_PMC_ENABLE;
282
283 if (config != PMCN_NONE) {
284 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
285 config |= PMLCax_CE;
286
287 /* Enable the PMC. */
288 switch (ri) {
289 case 0:
290 mtpmr(PMR_PMLCa0, config);
291 break;
292 case 1:
293 mtpmr(PMR_PMLCa1, config);
294 break;
295 case 2:
296 mtpmr(PMR_PMLCa2, config);
297 break;
298 case 3:
299 mtpmr(PMR_PMLCa3, config);
300 break;
301 }
302 } else {
303 /* Disable the PMC. */
304 switch (ri) {
305 case 0:
306 pmc_pmlc = mfpmr(PMR_PMLCa0);
307 pmc_pmlc |= PMLCax_FC;
308 mtpmr(PMR_PMLCa0, pmc_pmlc);
309 break;
310 case 1:
311 pmc_pmlc = mfpmr(PMR_PMLCa1);
312 pmc_pmlc |= PMLCax_FC;
313 mtpmr(PMR_PMLCa1, pmc_pmlc);
314 break;
315 case 2:
316 pmc_pmlc = mfpmr(PMR_PMLCa2);
317 pmc_pmlc |= PMLCax_FC;
318 mtpmr(PMR_PMLCa2, pmc_pmlc);
319 break;
320 case 3:
321 pmc_pmlc = mfpmr(PMR_PMLCa3);
322 pmc_pmlc |= PMLCax_FC;
323 mtpmr(PMR_PMLCa3, pmc_pmlc);
324 break;
325 }
326 }
327 }
328
329 static int
e500_pcpu_init(struct pmc_mdep * md,int cpu)330 e500_pcpu_init(struct pmc_mdep *md, int cpu)
331 {
332 int i;
333
334 powerpc_pcpu_init(md, cpu);
335
336 /* Freeze all counters. */
337 mtpmr(PMR_PMGC0, PMGC_FAC | PMGC_PMIE | PMGC_FCECE);
338
339 for (i = 0; i < E500_MAX_PMCS; i++)
340 /* Initialize the PMC to stopped */
341 e500_set_pmc(cpu, i, PMCN_NONE);
342
343 /* Unfreeze global register. */
344 mtpmr(PMR_PMGC0, PMGC_PMIE | PMGC_FCECE);
345
346 return (0);
347 }
348
349 static int
e500_pcpu_fini(struct pmc_mdep * md,int cpu)350 e500_pcpu_fini(struct pmc_mdep *md, int cpu)
351 {
352 uint32_t pmgc0 = mfpmr(PMR_PMGC0);
353
354 pmgc0 |= PMGC_FAC;
355 mtpmr(PMR_PMGC0, pmgc0);
356 mtmsr(mfmsr() & ~PSL_PMM);
357
358 return (powerpc_pcpu_fini(md, cpu));
359 }
360
361 static int
e500_allocate_pmc(int cpu,int ri,struct pmc * pm,const struct pmc_op_pmcallocate * a)362 e500_allocate_pmc(int cpu, int ri, struct pmc *pm,
363 const struct pmc_op_pmcallocate *a)
364 {
365 enum pmc_event pe;
366 uint32_t caps, config, counter;
367 struct e500_event_code_map *ev;
368 uint16_t vers;
369 uint8_t pe_cpu_mask;
370
371 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
372 ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
373 KASSERT(ri >= 0 && ri < E500_MAX_PMCS,
374 ("[powerpc,%d] illegal row index %d", __LINE__, ri));
375
376 if (a->pm_class != PMC_CLASS_E500)
377 return (EINVAL);
378
379 caps = a->pm_caps;
380
381 pe = a->pm_ev;
382 config = PMLCax_FCS | PMLCax_FCU |
383 PMLCax_FCM1 | PMLCax_FCM1;
384
385 if (pe < PMC_EV_E500_FIRST || pe > PMC_EV_E500_LAST)
386 return (EINVAL);
387
388 ev = &e500_event_codes[pe-PMC_EV_E500_FIRST];
389 if (ev->pe_code == 0)
390 return (EINVAL);
391
392 vers = mfpvr() >> 16;
393 switch (vers) {
394 case FSL_E500v1:
395 pe_cpu_mask = ev->pe_cpu & PMC_PPC_E500V1;
396 break;
397 case FSL_E500v2:
398 pe_cpu_mask = ev->pe_cpu & PMC_PPC_E500V2;
399 break;
400 case FSL_E500mc:
401 case FSL_E5500:
402 pe_cpu_mask = ev->pe_cpu & PMC_PPC_E500MC;
403 break;
404 }
405 if (pe_cpu_mask == 0)
406 return (EINVAL);
407
408 config |= PMLCax_EVENT(ev->pe_code);
409 counter = ev->pe_counter_mask;
410 if ((counter & (1 << ri)) == 0)
411 return (EINVAL);
412
413 if (caps & PMC_CAP_SYSTEM)
414 config &= ~PMLCax_FCS;
415 if (caps & PMC_CAP_USER)
416 config &= ~PMLCax_FCU;
417 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
418 config &= ~(PMLCax_FCS|PMLCax_FCU);
419
420 pm->pm_md.pm_powerpc.pm_powerpc_evsel = config;
421
422 PMCDBG2(MDP,ALL,2,"powerpc-allocate ri=%d -> config=0x%x", ri, config);
423
424 return 0;
425 }
426
427 static void
e500_resume_pmc(bool ie)428 e500_resume_pmc(bool ie)
429 {
430 /* Re-enable PERF exceptions. */
431 if (ie)
432 mtpmr(PMR_PMGC0, (mfpmr(PMR_PMGC0) & ~PMGC_FAC) | PMGC_PMIE);
433 }
434
435 int
pmc_e500_initialize(struct pmc_mdep * pmc_mdep)436 pmc_e500_initialize(struct pmc_mdep *pmc_mdep)
437 {
438 struct pmc_classdep *pcd;
439
440 pmc_mdep->pmd_cputype = PMC_CPU_PPC_E500;
441
442 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_POWERPC];
443 pcd->pcd_caps = POWERPC_PMC_CAPS;
444 pcd->pcd_class = PMC_CLASS_E500;
445 pcd->pcd_num = E500_MAX_PMCS;
446 pcd->pcd_ri = pmc_mdep->pmd_npmc;
447 pcd->pcd_width = 32;
448
449 pcd->pcd_allocate_pmc = e500_allocate_pmc;
450 pcd->pcd_config_pmc = powerpc_config_pmc;
451 pcd->pcd_pcpu_fini = e500_pcpu_fini;
452 pcd->pcd_pcpu_init = e500_pcpu_init;
453 pcd->pcd_describe = powerpc_describe;
454 pcd->pcd_get_config = powerpc_get_config;
455 pcd->pcd_read_pmc = powerpc_read_pmc;
456 pcd->pcd_release_pmc = powerpc_release_pmc;
457 pcd->pcd_start_pmc = powerpc_start_pmc;
458 pcd->pcd_stop_pmc = powerpc_stop_pmc;
459 pcd->pcd_write_pmc = powerpc_write_pmc;
460
461 pmc_mdep->pmd_npmc += E500_MAX_PMCS;
462 pmc_mdep->pmd_intr = powerpc_pmc_intr;
463
464 ppc_max_pmcs = E500_MAX_PMCS;
465
466 powerpc_set_pmc = e500_set_pmc;
467 powerpc_pmcn_read = e500_pmcn_read;
468 powerpc_pmcn_write = e500_pmcn_write;
469 powerpc_resume_pmc = e500_resume_pmc;
470
471 return (0);
472 }
473