1 #ifndef _GRC_ADDR_H 2 #define _GRC_ADDR_H 3 /* 4 * This file defines GRC base address for every block. 5 * This file is included by chipsim, asm microcode and cpp microcode. 6 * These values are used in Design.xml on regBase attribute 7 * Use the base with the generated offsets of specific registers. 8 */ 9 10 #define GRCBASE_PXPCS 0x000000 // this is the pciex core 11 #define GRCBASE_PCICONFIG 0x002000 12 #define GRCBASE_PCIREG 0x002400 13 #define GRCBASE_EMAC0 0x008000 14 #define GRCBASE_EMAC1 0x008400 15 #define GRCBASE_DBU 0x008800 16 #define GRCBASE_PGLUE_B 0x009000 17 #define GRCBASE_MISC 0x00A000 18 #define GRCBASE_DBG 0x00C000 19 #define GRCBASE_NIG 0x010000 20 #define GRCBASE_XCM 0x020000 21 #define GRCBASE_PRS 0x040000 22 #define GRCBASE_SRCH 0x040400 23 #define GRCBASE_TSDM 0x042000 //Note: regBase is made to fit in 20 bits, for TsdmTB::GrcCmd test 24 #define GRCBASE_TCM 0x050000 25 #define GRCBASE_BRB1 0x060000 26 #define GRCBASE_MCP 0x080000 27 #define GRCBASE_UPB 0x0C1000 28 #define GRCBASE_CSDM 0x0C2000 29 #define GRCBASE_USDM 0x0C4000 30 #define GRCBASE_CCM 0x0D0000 31 #define GRCBASE_UCM 0x0E0000 32 #define GRCBASE_CDU 0x101000 33 #define GRCBASE_DMAE 0x102000 34 #define GRCBASE_PXP 0x103000 // we have 2 pxp blocks now 35 #define GRCBASE_CFC 0x104000 36 #define GRCBASE_HC 0x108000 37 #define GRCBASE_ATC 0x110000 38 #define GRCBASE_PXP2 0x120000 // this is the 2nd pxp 39 #define GRCBASE_IGU 0x130000 40 #define GRCBASE_PBF 0x140000 41 #define GRCBASE_UMAC0 0x160000 42 #define GRCBASE_UMAC1 0x160400 43 #define GRCBASE_XPB 0x161000 // pbf_pb 44 #define GRCBASE_MSTAT0 0x162000 45 #define GRCBASE_MSTAT1 0x162800 46 #define GRCBASE_XMAC0 0x163000 47 #define GRCBASE_XMAC1 0x163800 48 #define GRCBASE_TIMERS 0x164000 49 #define GRCBASE_XSDM 0x166000 50 #define GRCBASE_QM 0x168000 51 #define GRCBASE_QM_4PORT 0x168000 // a dummy block for generating 4-port-specific QM init values 52 #define GRCBASE_DQ 0x170000 53 #define GRCBASE_TSEM 0x180000 // was previously GRCBASE_TSTORM 54 #define GRCBASE_CSEM 0x200000 // was previously GRCBASE_CSTORM 55 #define GRCBASE_XSEM 0x280000 // was previously GRCBASE_XSTORM 56 #define GRCBASE_XSEM_4PORT 0x280000 // a dummy block for generating 4-port-specific XSEM init values 57 #define GRCBASE_USEM 0x300000 // was previously GRCBASE_USTORM 58 #define GRCBASE_MCP_A 0x380000 59 #define GRCBASE_MISC_AEU GRCBASE_MISC // just for driver init 60 #define GRCBASE_Tstorm GRCBASE_TSEM 61 #define GRCBASE_Cstorm GRCBASE_CSEM 62 #define GRCBASE_Xstorm GRCBASE_XSEM 63 #define GRCBASE_Ustorm GRCBASE_USEM 64 65 66 #endif //_GRC_ADRR_H 67 68