1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024 Samsung Electronics Co., Ltd.
4 * Author: Sunyeal Hong <sunyeal.hong@samsung.com>
5 *
6 * Common Clock Framework support for ExynosAuto v920 SoC.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13
14 #include <dt-bindings/clock/samsung,exynosautov920.h>
15
16 #include "clk.h"
17 #include "clk-exynos-arm64.h"
18
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
21 #define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
22 #define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1)
23 #define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
24 #define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1)
25 #define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1)
26
27 /* ---- CMU_TOP ------------------------------------------------------------ */
28
29 /* Register Offset definitions for CMU_TOP (0x11000000) */
30 #define PLL_LOCKTIME_PLL_MMC 0x0004
31 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
32 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
33 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
34 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
35 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
36 #define PLL_LOCKTIME_PLL_SHARED5 0x0018
37 #define PLL_CON0_PLL_MMC 0x0140
38 #define PLL_CON3_PLL_MMC 0x014c
39 #define PLL_CON0_PLL_SHARED0 0x0180
40 #define PLL_CON3_PLL_SHARED0 0x018c
41 #define PLL_CON0_PLL_SHARED1 0x01c0
42 #define PLL_CON3_PLL_SHARED1 0x01cc
43 #define PLL_CON0_PLL_SHARED2 0x0200
44 #define PLL_CON3_PLL_SHARED2 0x020c
45 #define PLL_CON0_PLL_SHARED3 0x0240
46 #define PLL_CON3_PLL_SHARED3 0x024c
47 #define PLL_CON0_PLL_SHARED4 0x0280
48 #define PLL_CON3_PLL_SHARED4 0x028c
49 #define PLL_CON0_PLL_SHARED5 0x02c0
50 #define PLL_CON3_PLL_SHARED5 0x02cc
51
52 /* MUX */
53 #define CLK_CON_MUX_MUX_CLKCMU_ACC_NOC 0x1000
54 #define CLK_CON_MUX_MUX_CLKCMU_APM_NOC 0x1004
55 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
56 #define CLK_CON_MUX_MUX_CLKCMU_AUD_NOC 0x100c
57 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0 0x1010
58 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1 0x1014
59 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2 0x1018
60 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3 0x101c
61 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1020
62 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
63 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1028
64 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
65 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
66 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
67 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER 0x1038
68 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x103c
69 #define CLK_CON_MUX_MUX_CLKCMU_DNC_NOC 0x1040
70 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
71 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC 0x1048
72 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC 0x104c
73 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM 0x1050
74 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC 0x1054
75 #define CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC 0x1058
76 #define CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC 0x105c
77 #define CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC 0x1060
78 #define CLK_CON_MUX_MUX_CLKCMU_DSP_NOC 0x1064
79 #define CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP 0x1068
80 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x106c
81 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC 0x1070
82 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC 0x1074
83 #define CLK_CON_MUX_MUX_CLKCMU_ACC_ORB 0x1078
84 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA 0x107c
85 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD 0x1080
86 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC 0x1084
87 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD 0x1088
88 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET 0x108c
89 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC 0x1090
90 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS 0x1094
91 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x1098
92 #define CLK_CON_MUX_MUX_CLKCMU_ISP_NOC 0x109c
93 #define CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG 0x10a0
94 #define CLK_CON_MUX_MUX_CLKCMU_M2M_NOC 0x10a4
95 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10a8
96 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x10ac
97 #define CLK_CON_MUX_MUX_CLKCMU_MFD_NOC 0x10b0
98 #define CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP 0x10b4
99 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10b8
100 #define CLK_CON_MUX_MUX_CLKCMU_MISC_NOC 0x10bc
101 #define CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC 0x10c0
102 #define CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC 0x10c4
103 #define CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC 0x10c8
104 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10cc
105 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC 0x10d0
106 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10d4
107 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC 0x10d8
108 #define CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC 0x10dc
109 #define CLK_CON_MUX_MUX_CLKCMU_SNW_NOC 0x10e0
110 #define CLK_CON_MUX_MUX_CLKCMU_SSP_NOC 0x10e4
111 #define CLK_CON_MUX_MUX_CLKCMU_TAA_NOC 0x10e8
112 #define CLK_CON_MUX_MUX_CLK_CMU_NOCP 0x10ec
113 #define CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT 0x10f0
114 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4
115
116 /* DIV */
117 #define CLK_CON_DIV_CLKCMU_ACC_NOC 0x1800
118 #define CLK_CON_DIV_CLKCMU_APM_NOC 0x1804
119 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1808
120 #define CLK_CON_DIV_CLKCMU_AUD_NOC 0x180c
121 #define CLK_CON_DIV_CLKCMU_CIS_MCLK0 0x1810
122 #define CLK_CON_DIV_CLKCMU_CIS_MCLK1 0x1814
123 #define CLK_CON_DIV_CLKCMU_CIS_MCLK2 0x1818
124 #define CLK_CON_DIV_CLKCMU_CIS_MCLK3 0x181c
125 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
126 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1824
127 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
128 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
129 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
130 #define CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER 0x1834
131 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1838
132 #define CLK_CON_DIV_CLKCMU_DNC_NOC 0x183c
133 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
134 #define CLK_CON_DIV_CLKCMU_DPTX_DPOSC 0x1844
135 #define CLK_CON_DIV_CLKCMU_DPTX_NOC 0x1848
136 #define CLK_CON_DIV_CLKCMU_DPUB_DSIM 0x184c
137 #define CLK_CON_DIV_CLKCMU_DPUB_NOC 0x1850
138 #define CLK_CON_DIV_CLKCMU_DPUF0_NOC 0x1854
139 #define CLK_CON_DIV_CLKCMU_DPUF1_NOC 0x1858
140 #define CLK_CON_DIV_CLKCMU_DPUF2_NOC 0x185c
141 #define CLK_CON_DIV_CLKCMU_DSP_NOC 0x1860
142 #define CLK_CON_DIV_CLKCMU_G3D_NOCP 0x1864
143 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1868
144 #define CLK_CON_DIV_CLKCMU_GNPU_NOC 0x186c
145 #define CLK_CON_DIV_CLKCMU_HSI0_NOC 0x1870
146 #define CLK_CON_DIV_CLKCMU_ACC_ORB 0x1874
147 #define CLK_CON_DIV_CLKCMU_GNPU_XMAA 0x1878
148 #define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD 0x187c
149 #define CLK_CON_DIV_CLKCMU_HSI1_NOC 0x1880
150 #define CLK_CON_DIV_CLKCMU_HSI1_USBDRD 0x1884
151 #define CLK_CON_DIV_CLKCMU_HSI2_ETHERNET 0x1888
152 #define CLK_CON_DIV_CLKCMU_HSI2_NOC 0x188c
153 #define CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS 0x1890
154 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x1894
155 #define CLK_CON_DIV_CLKCMU_ISP_NOC 0x1898
156 #define CLK_CON_DIV_CLKCMU_M2M_JPEG 0x189c
157 #define CLK_CON_DIV_CLKCMU_M2M_NOC 0x18a0
158 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18a4
159 #define CLK_CON_DIV_CLKCMU_MFC_WFD 0x18a8
160 #define CLK_CON_DIV_CLKCMU_MFD_NOC 0x18ac
161 #define CLK_CON_DIV_CLKCMU_MIF_NOCP 0x18b0
162 #define CLK_CON_DIV_CLKCMU_MISC_NOC 0x18b4
163 #define CLK_CON_DIV_CLKCMU_NOCL0_NOC 0x18b8
164 #define CLK_CON_DIV_CLKCMU_NOCL1_NOC 0x18bc
165 #define CLK_CON_DIV_CLKCMU_NOCL2_NOC 0x18c0
166 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18c4
167 #define CLK_CON_DIV_CLKCMU_PERIC0_NOC 0x18c8
168 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18cc
169 #define CLK_CON_DIV_CLKCMU_PERIC1_NOC 0x18d0
170 #define CLK_CON_DIV_CLKCMU_SDMA_NOC 0x18d4
171 #define CLK_CON_DIV_CLKCMU_SNW_NOC 0x18d8
172 #define CLK_CON_DIV_CLKCMU_SSP_NOC 0x18dc
173 #define CLK_CON_DIV_CLKCMU_TAA_NOC 0x18e0
174 #define CLK_CON_DIV_CLK_ADD_CH_CLK 0x18e4
175 #define CLK_CON_DIV_CLK_CMU_PLLCLKOUT 0x18e8
176 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18ec
177 #define CLK_CON_DIV_DIV_CLK_CMU_NOCP 0x18f0
178
179 static const unsigned long top_clk_regs[] __initconst = {
180 PLL_LOCKTIME_PLL_MMC,
181 PLL_LOCKTIME_PLL_SHARED0,
182 PLL_LOCKTIME_PLL_SHARED1,
183 PLL_LOCKTIME_PLL_SHARED2,
184 PLL_LOCKTIME_PLL_SHARED3,
185 PLL_LOCKTIME_PLL_SHARED4,
186 PLL_LOCKTIME_PLL_SHARED5,
187 PLL_CON0_PLL_MMC,
188 PLL_CON3_PLL_MMC,
189 PLL_CON0_PLL_SHARED0,
190 PLL_CON3_PLL_SHARED0,
191 PLL_CON0_PLL_SHARED1,
192 PLL_CON3_PLL_SHARED1,
193 PLL_CON0_PLL_SHARED2,
194 PLL_CON3_PLL_SHARED2,
195 PLL_CON0_PLL_SHARED3,
196 PLL_CON3_PLL_SHARED3,
197 PLL_CON0_PLL_SHARED4,
198 PLL_CON3_PLL_SHARED4,
199 PLL_CON0_PLL_SHARED5,
200 PLL_CON3_PLL_SHARED5,
201 CLK_CON_MUX_MUX_CLKCMU_ACC_NOC,
202 CLK_CON_MUX_MUX_CLKCMU_APM_NOC,
203 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
204 CLK_CON_MUX_MUX_CLKCMU_AUD_NOC,
205 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0,
206 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1,
207 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2,
208 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3,
209 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
210 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
211 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
212 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
213 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
214 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
215 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER,
216 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
217 CLK_CON_MUX_MUX_CLKCMU_DNC_NOC,
218 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC,
219 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC,
220 CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC,
221 CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM,
222 CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC,
223 CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC,
224 CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC,
225 CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC,
226 CLK_CON_MUX_MUX_CLKCMU_DSP_NOC,
227 CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP,
228 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
229 CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC,
230 CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC,
231 CLK_CON_MUX_MUX_CLKCMU_ACC_ORB,
232 CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA,
233 CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
234 CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC,
235 CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD,
236 CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET,
237 CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC,
238 CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS,
239 CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
240 CLK_CON_MUX_MUX_CLKCMU_ISP_NOC,
241 CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG,
242 CLK_CON_MUX_MUX_CLKCMU_M2M_NOC,
243 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
244 CLK_CON_MUX_MUX_CLKCMU_MFC_WFD,
245 CLK_CON_MUX_MUX_CLKCMU_MFD_NOC,
246 CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP,
247 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
248 CLK_CON_MUX_MUX_CLKCMU_MISC_NOC,
249 CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC,
250 CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC,
251 CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC,
252 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
253 CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC,
254 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
255 CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC,
256 CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC,
257 CLK_CON_MUX_MUX_CLKCMU_SNW_NOC,
258 CLK_CON_MUX_MUX_CLKCMU_SSP_NOC,
259 CLK_CON_MUX_MUX_CLKCMU_TAA_NOC,
260 CLK_CON_MUX_MUX_CLK_CMU_NOCP,
261 CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT,
262 CLK_CON_MUX_MUX_CMU_CMUREF,
263 CLK_CON_DIV_CLKCMU_ACC_NOC,
264 CLK_CON_DIV_CLKCMU_APM_NOC,
265 CLK_CON_DIV_CLKCMU_AUD_CPU,
266 CLK_CON_DIV_CLKCMU_AUD_NOC,
267 CLK_CON_DIV_CLKCMU_CIS_MCLK0,
268 CLK_CON_DIV_CLKCMU_CIS_MCLK1,
269 CLK_CON_DIV_CLKCMU_CIS_MCLK2,
270 CLK_CON_DIV_CLKCMU_CIS_MCLK3,
271 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
272 CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
273 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
274 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
275 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
276 CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER,
277 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
278 CLK_CON_DIV_CLKCMU_DNC_NOC,
279 CLK_CON_DIV_CLKCMU_DPTX_DPGTC,
280 CLK_CON_DIV_CLKCMU_DPTX_DPOSC,
281 CLK_CON_DIV_CLKCMU_DPTX_NOC,
282 CLK_CON_DIV_CLKCMU_DPUB_DSIM,
283 CLK_CON_DIV_CLKCMU_DPUB_NOC,
284 CLK_CON_DIV_CLKCMU_DPUF0_NOC,
285 CLK_CON_DIV_CLKCMU_DPUF1_NOC,
286 CLK_CON_DIV_CLKCMU_DPUF2_NOC,
287 CLK_CON_DIV_CLKCMU_DSP_NOC,
288 CLK_CON_DIV_CLKCMU_G3D_NOCP,
289 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
290 CLK_CON_DIV_CLKCMU_GNPU_NOC,
291 CLK_CON_DIV_CLKCMU_HSI0_NOC,
292 CLK_CON_DIV_CLKCMU_ACC_ORB,
293 CLK_CON_DIV_CLKCMU_GNPU_XMAA,
294 CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
295 CLK_CON_DIV_CLKCMU_HSI1_NOC,
296 CLK_CON_DIV_CLKCMU_HSI1_USBDRD,
297 CLK_CON_DIV_CLKCMU_HSI2_ETHERNET,
298 CLK_CON_DIV_CLKCMU_HSI2_NOC,
299 CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS,
300 CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
301 CLK_CON_DIV_CLKCMU_ISP_NOC,
302 CLK_CON_DIV_CLKCMU_M2M_JPEG,
303 CLK_CON_DIV_CLKCMU_M2M_NOC,
304 CLK_CON_DIV_CLKCMU_MFC_MFC,
305 CLK_CON_DIV_CLKCMU_MFC_WFD,
306 CLK_CON_DIV_CLKCMU_MFD_NOC,
307 CLK_CON_DIV_CLKCMU_MIF_NOCP,
308 CLK_CON_DIV_CLKCMU_MISC_NOC,
309 CLK_CON_DIV_CLKCMU_NOCL0_NOC,
310 CLK_CON_DIV_CLKCMU_NOCL1_NOC,
311 CLK_CON_DIV_CLKCMU_NOCL2_NOC,
312 CLK_CON_DIV_CLKCMU_PERIC0_IP,
313 CLK_CON_DIV_CLKCMU_PERIC0_NOC,
314 CLK_CON_DIV_CLKCMU_PERIC1_IP,
315 CLK_CON_DIV_CLKCMU_PERIC1_NOC,
316 CLK_CON_DIV_CLKCMU_SDMA_NOC,
317 CLK_CON_DIV_CLKCMU_SNW_NOC,
318 CLK_CON_DIV_CLKCMU_SSP_NOC,
319 CLK_CON_DIV_CLKCMU_TAA_NOC,
320 CLK_CON_DIV_CLK_ADD_CH_CLK,
321 CLK_CON_DIV_CLK_CMU_PLLCLKOUT,
322 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
323 CLK_CON_DIV_DIV_CLK_CMU_NOCP,
324 };
325
326 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
327 /* CMU_TOP_PURECLKCOMP */
328 PLL(pll_531x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
329 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
330 PLL(pll_531x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
331 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
332 PLL(pll_531x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
333 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
334 PLL(pll_531x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
335 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
336 PLL(pll_531x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
337 PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
338 PLL(pll_531x, FOUT_SHARED5_PLL, "fout_shared5_pll", "oscclk",
339 PLL_LOCKTIME_PLL_SHARED5, PLL_CON3_PLL_SHARED5, NULL),
340 PLL(pll_531x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
341 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
342 };
343
344 /* List of parent clocks for Muxes in CMU_TOP */
345 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
346 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
347 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
348 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
349 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
350 PNAME(mout_shared5_pll_p) = { "oscclk", "fout_shared5_pll" };
351 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
352
353 PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4",
354 "dout_shared2_div4", "dout_shared4_div4" };
355
356 PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" };
357
358 PNAME(mout_clkcmu_acc_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
359 "dout_shared4_div2", "dout_shared1_div3",
360 "dout_shared2_div3", "dout_shared5_div1",
361 "dout_shared3_div1", "oscclk" };
362
363 PNAME(mout_clkcmu_acc_orb_p) = { "dout_shared2_div2", "dout_shared0_div3",
364 "dout_shared1_div2", "dout_shared1_div3",
365 "dout_shared2_div3", "fout_shared5_pll",
366 "fout_shared3_pll", "oscclk" };
367
368 PNAME(mout_clkcmu_apm_noc_p) = { "dout_shared2_div2", "dout_shared1_div4",
369 "dout_shared2_div4", "dout_shared4_div4" };
370
371 PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
372 "dout_shared2_div2", "dout_shared0_div3",
373 "dout_shared4_div2", "dout_shared1_div3",
374 "dout_shared2_div3", "dout_shared4_div3" };
375
376 PNAME(mout_clkcmu_aud_noc_p) = { "dout_shared2_div2", "dout_shared4_div2",
377 "dout_shared1_div2", "dout_shared2_div3" };
378
379 PNAME(mout_clkcmu_cpucl0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
380 "dout_shared2_div2", "dout_shared4_div2" };
381
382 PNAME(mout_clkcmu_cpucl0_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll",
383 "dout_shared0_div2", "dout_shared1_div2",
384 "dout_shared2_div2", "dout_shared4_div2",
385 "dout_shared2_div3", "fout_shared3_pll" };
386
387 PNAME(mout_clkcmu_cpucl0_dbg_p) = { "dout_shared2_div2", "dout_shared0_div3",
388 "dout_shared4_div2", "dout_shared0_div4" };
389
390 PNAME(mout_clkcmu_cpucl1_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
391 "dout_shared2_div2", "dout_shared4_div2" };
392
393 PNAME(mout_clkcmu_cpucl1_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll",
394 "dout_shared0_div2", "dout_shared1_div2",
395 "dout_shared2_div2", "dout_shared4_div2",
396 "dout_shared2_div3", "fout_shared3_pll" };
397
398 PNAME(mout_clkcmu_cpucl2_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
399 "dout_shared2_div2", "dout_shared4_div2" };
400
401 PNAME(mout_clkcmu_cpucl2_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll",
402 "dout_shared0_div2", "dout_shared1_div2",
403 "dout_shared2_div2", "dout_shared4_div2",
404 "dout_shared2_div3", "fout_shared3_pll" };
405
406 PNAME(mout_clkcmu_dnc_noc_p) = { "dout_shared1_div2", "dout_shared2_div2",
407 "dout_shared0_div3", "dout_shared4_div2",
408 "dout_shared1_div3", "dout_shared2_div3",
409 "dout_shared1_div4", "fout_shared3_pll" };
410
411 PNAME(mout_clkcmu_dptx_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
412 "dout_shared1_div4", "dout_shared2_div4" };
413
414 PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3",
415 "dout_shared2_div4", "dout_shared4_div4" };
416
417 PNAME(mout_clkcmu_dptx_dposc_p) = { "oscclk", "dout_shared2_div4" };
418
419 PNAME(mout_clkcmu_dpub_noc_p) = { "dout_shared4_div2", "dout_shared1_div3",
420 "dout_shared2_div3", "dout_shared1_div4",
421 "dout_shared2_div4", "dout_shared4_div4",
422 "fout_shared3_pll" };
423
424 PNAME(mout_clkcmu_dpub_dsim_p) = { "dout_shared2_div3", "dout_shared2_div4" };
425
426 PNAME(mout_clkcmu_dpuf_noc_p) = { "dout_shared4_div2", "dout_shared1_div3",
427 "dout_shared2_div3", "dout_shared1_div4",
428 "dout_shared2_div4", "dout_shared4_div4",
429 "fout_shared3_pll" };
430
431 PNAME(mout_clkcmu_dsp_noc_p) = { "dout_shared0_div2", "dout_shared1_div2",
432 "dout_shared2_div2", "dout_shared0_div3",
433 "dout_shared4_div2", "dout_shared1_div3",
434 "fout_shared5_pll", "fout_shared3_pll" };
435
436 PNAME(mout_clkcmu_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
437 "dout_shared2_div2", "dout_shared4_div2" };
438
439 PNAME(mout_clkcmu_g3d_nocp_p) = { "dout_shared2_div3", "dout_shared1_div4",
440 "dout_shared2_div4", "dout_shared4_div4" };
441
442 PNAME(mout_clkcmu_gnpu_noc_p) = { "dout_shared0_div2", "dout_shared1_div2",
443 "dout_shared2_div2", "dout_shared0_div3",
444 "dout_shared4_div2", "dout_shared2_div3",
445 "fout_shared5_pll", "fout_shared3_pll" };
446
447 PNAME(mout_clkcmu_hsi0_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
448 "dout_shared1_div4", "dout_shared2_div4" };
449
450 PNAME(mout_clkcmu_hsi1_noc_p) = { "dout_shared2_div3", "dout_shared1_div4",
451 "dout_shared2_div4", "dout_shared4_div4" };
452
453 PNAME(mout_clkcmu_hsi1_usbdrd_p) = { "oscclk", "dout_shared2_div3",
454 "dout_shared2_div4", "dout_shared4_div4" };
455
456 PNAME(mout_clkcmu_hsi1_mmc_card_p) = { "oscclk", "dout_shared2_div2",
457 "dout_shared4_div2", "fout_mmc_pll" };
458
459 PNAME(mout_clkcmu_hsi2_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
460 "dout_shared1_div4", "dout_shared2_div4" };
461
462 PNAME(mout_clkcmu_hsi2_noc_ufs_p) = { "dout_shared4_div2", "dout_shared2_div3",
463 "dout_shared1_div4", "dout_shared2_div2" };
464
465 PNAME(mout_clkcmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared2_div3",
466 "dout_shared2_div4", "dout_shared4_div4" };
467
468 PNAME(mout_clkcmu_hsi2_ethernet_p) = { "oscclk", "dout_shared2_div2",
469 "dout_shared0_div3", "dout_shared1_div3" };
470
471 PNAME(mout_clkcmu_isp_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
472 "dout_shared4_div2", "dout_shared1_div3",
473 "dout_shared2_div3", "fout_shared5_pll",
474 "fout_shared3_pll", "oscclk" };
475
476 PNAME(mout_clkcmu_m2m_noc_p) = { "dout_shared0_div3", "dout_shared4_div2",
477 "dout_shared2_div3", "dout_shared1_div4" };
478
479 PNAME(mout_clkcmu_m2m_jpeg_p) = { "dout_shared0_div3", "dout_shared4_div2",
480 "dout_shared2_div3", "dout_shared1_div4" };
481
482 PNAME(mout_clkcmu_mfc_mfc_p) = { "dout_shared0_div3", "dout_shared4_div2",
483 "dout_shared2_div3", "dout_shared1_div4" };
484
485 PNAME(mout_clkcmu_mfc_wfd_p) = { "dout_shared0_div3", "dout_shared4_div2",
486 "dout_shared2_div3", "dout_shared1_div4" };
487
488 PNAME(mout_clkcmu_mfd_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
489 "dout_shared4_div2", "dout_shared1_div3",
490 "dout_shared2_div3", "fout_shared5_pll",
491 "fout_shared3_pll", "oscclk" };
492
493 PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
494 "fout_shared2_pll", "fout_shared4_pll",
495 "dout_shared0_div2", "dout_shared1_div2",
496 "dout_shared2_div2", "fout_shared5_pll" };
497
498 PNAME(mout_clkcmu_mif_nocp_p) = { "dout_shared2_div3", "dout_shared1_div4",
499 "dout_shared2_div4", "dout_shared4_div4" };
500
501 PNAME(mout_clkcmu_misc_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
502 "dout_shared1_div4", "dout_shared2_div4" };
503
504 PNAME(mout_clkcmu_nocl0_noc_p) = { "dout_shared0_div2", "dout_shared1_div2",
505 "dout_shared2_div2", "dout_shared0_div3",
506 "dout_shared4_div2", "dout_shared1_div3",
507 "dout_shared2_div3", "fout_shared3_pll" };
508
509 PNAME(mout_clkcmu_nocl1_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
510 "dout_shared4_div2", "dout_shared1_div3",
511 "dout_shared2_div3", "fout_shared5_pll",
512 "fout_shared3_pll", "oscclk" };
513
514 PNAME(mout_clkcmu_nocl2_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
515 "dout_shared4_div2", "dout_shared1_div3",
516 "dout_shared2_div3", "fout_shared5_pll",
517 "fout_shared3_pll", "oscclk" };
518
519 PNAME(mout_clkcmu_peric0_noc_p) = { "dout_shared2_div3", "dout_shared2_div4" };
520
521 PNAME(mout_clkcmu_peric0_ip_p) = { "dout_shared2_div3", "dout_shared2_div4" };
522
523 PNAME(mout_clkcmu_peric1_noc_p) = { "dout_shared2_div3", "dout_shared2_div4" };
524
525 PNAME(mout_clkcmu_peric1_ip_p) = { "dout_shared2_div3", "dout_shared2_div4" };
526
527 PNAME(mout_clkcmu_sdma_noc_p) = { "dout_shared1_div2", "dout_shared2_div2",
528 "dout_shared0_div3", "dout_shared4_div2",
529 "dout_shared1_div3", "dout_shared2_div3",
530 "dout_shared1_div4", "fout_shared3_pll" };
531
532 PNAME(mout_clkcmu_snw_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
533 "dout_shared4_div2", "dout_shared1_div3",
534 "dout_shared2_div3", "fout_shared5_pll",
535 "fout_shared3_pll", "oscclk" };
536
537 PNAME(mout_clkcmu_ssp_noc_p) = { "dout_shared2_div3", "dout_shared1_div4",
538 "dout_shared2_div2", "dout_shared4_div4" };
539
540 PNAME(mout_clkcmu_taa_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
541 "dout_shared4_div2", "dout_shared1_div3",
542 "dout_shared2_div3", "fout_shared5_pll",
543 "fout_shared3_pll", "oscclk" };
544
545 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
546 /* CMU_TOP_PURECLKCOMP */
547 MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
548 PLL_CON0_PLL_SHARED0, 4, 1),
549 MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
550 PLL_CON0_PLL_SHARED1, 4, 1),
551 MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
552 PLL_CON0_PLL_SHARED2, 4, 1),
553 MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
554 PLL_CON0_PLL_SHARED3, 4, 1),
555 MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
556 PLL_CON0_PLL_SHARED4, 4, 1),
557 MUX(MOUT_SHARED5_PLL, "mout_shared5_pll", mout_shared5_pll_p,
558 PLL_CON0_PLL_SHARED5, 4, 1),
559 MUX(MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
560 PLL_CON0_PLL_MMC, 4, 1),
561
562 /* BOOST */
563 MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost",
564 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
565 MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref",
566 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
567
568 /* ACC */
569 MUX(MOUT_CLKCMU_ACC_NOC, "mout_clkcmu_acc_noc",
570 mout_clkcmu_acc_noc_p, CLK_CON_MUX_MUX_CLKCMU_ACC_NOC, 0, 3),
571 MUX(MOUT_CLKCMU_ACC_ORB, "mout_clkcmu_acc_orb",
572 mout_clkcmu_acc_orb_p, CLK_CON_MUX_MUX_CLKCMU_ACC_ORB, 0, 3),
573
574 /* APM */
575 MUX(MOUT_CLKCMU_APM_NOC, "mout_clkcmu_apm_noc",
576 mout_clkcmu_apm_noc_p, CLK_CON_MUX_MUX_CLKCMU_APM_NOC, 0, 2),
577
578 /* AUD */
579 MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu",
580 mout_clkcmu_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
581 MUX(MOUT_CLKCMU_AUD_NOC, "mout_clkcmu_aud_noc",
582 mout_clkcmu_aud_noc_p, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 0, 2),
583
584 /* CPUCL0 */
585 MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch",
586 mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
587 0, 2),
588 MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster",
589 mout_clkcmu_cpucl0_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
590 0, 3),
591 MUX(MOUT_CLKCMU_CPUCL0_DBG, "mout_clkcmu_cpucl0_dbg",
592 mout_clkcmu_cpucl0_dbg_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
593 0, 2),
594
595 /* CPUCL1 */
596 MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch",
597 mout_clkcmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
598 0, 2),
599 MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster",
600 mout_clkcmu_cpucl1_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
601 0, 3),
602
603 /* CPUCL2 */
604 MUX(MOUT_CLKCMU_CPUCL2_SWITCH, "mout_clkcmu_cpucl2_switch",
605 mout_clkcmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
606 0, 2),
607 MUX(MOUT_CLKCMU_CPUCL2_CLUSTER, "mout_clkcmu_cpucl2_cluster",
608 mout_clkcmu_cpucl2_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER,
609 0, 3),
610
611 /* DNC */
612 MUX(MOUT_CLKCMU_DNC_NOC, "mout_clkcmu_dnc_noc",
613 mout_clkcmu_dnc_noc_p, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 0, 3),
614
615 /* DPTX */
616 MUX(MOUT_CLKCMU_DPTX_NOC, "mout_clkcmu_dptx_noc",
617 mout_clkcmu_dptx_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC, 0, 2),
618 MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc",
619 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
620 MUX(MOUT_CLKCMU_DPTX_DPOSC, "mout_clkcmu_dptx_dposc",
621 mout_clkcmu_dptx_dposc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC, 0, 1),
622
623 /* DPUB */
624 MUX(MOUT_CLKCMU_DPUB_NOC, "mout_clkcmu_dpub_noc",
625 mout_clkcmu_dpub_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC, 0, 3),
626 MUX(MOUT_CLKCMU_DPUB_DSIM, "mout_clkcmu_dpub_dsim",
627 mout_clkcmu_dpub_dsim_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 0, 1),
628
629 /* DPUF */
630 MUX(MOUT_CLKCMU_DPUF0_NOC, "mout_clkcmu_dpuf0_noc",
631 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC, 0, 3),
632 MUX(MOUT_CLKCMU_DPUF1_NOC, "mout_clkcmu_dpuf1_noc",
633 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC, 0, 3),
634 MUX(MOUT_CLKCMU_DPUF2_NOC, "mout_clkcmu_dpuf2_noc",
635 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC, 0, 3),
636
637 /* DSP */
638 MUX(MOUT_CLKCMU_DSP_NOC, "mout_clkcmu_dsp_noc",
639 mout_clkcmu_dsp_noc_p, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 0, 3),
640
641 /* G3D */
642 MUX(MOUT_CLKCMU_G3D_SWITCH, "mout_clkcmu_g3d_switch",
643 mout_clkcmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
644 MUX(MOUT_CLKCMU_G3D_NOCP, "mout_clkcmu_g3d_nocp",
645 mout_clkcmu_g3d_nocp_p, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 0, 2),
646
647 /* GNPU */
648 MUX(MOUT_CLKCMU_GNPU_NOC, "mout_clkcmu_gnpu_noc",
649 mout_clkcmu_gnpu_noc_p, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 0, 3),
650
651 /* HSI0 */
652 MUX(MOUT_CLKCMU_HSI0_NOC, "mout_clkcmu_hsi0_noc",
653 mout_clkcmu_hsi0_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0, 2),
654
655 /* HSI1 */
656 MUX(MOUT_CLKCMU_HSI1_NOC, "mout_clkcmu_hsi1_noc",
657 mout_clkcmu_hsi1_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC,
658 0, 2),
659 MUX(MOUT_CLKCMU_HSI1_USBDRD, "mout_clkcmu_hsi1_usbdrd",
660 mout_clkcmu_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD,
661 0, 2),
662 MUX(MOUT_CLKCMU_HSI1_MMC_CARD, "mout_clkcmu_hsi1_mmc_card",
663 mout_clkcmu_hsi1_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
664 0, 2),
665
666 /* HSI2 */
667 MUX(MOUT_CLKCMU_HSI2_NOC, "mout_clkcmu_hsi2_noc",
668 mout_clkcmu_hsi2_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC,
669 0, 2),
670 MUX(MOUT_CLKCMU_HSI2_NOC_UFS, "mout_clkcmu_hsi2_noc_ufs",
671 mout_clkcmu_hsi2_noc_ufs_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS,
672 0, 2),
673 MUX(MOUT_CLKCMU_HSI2_UFS_EMBD, "mout_clkcmu_hsi2_ufs_embd",
674 mout_clkcmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
675 0, 2),
676 MUX(MOUT_CLKCMU_HSI2_ETHERNET, "mout_clkcmu_hsi2_ethernet",
677 mout_clkcmu_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET,
678 0, 2),
679
680 /* ISP */
681 MUX(MOUT_CLKCMU_ISP_NOC, "mout_clkcmu_isp_noc",
682 mout_clkcmu_isp_noc_p, CLK_CON_MUX_MUX_CLKCMU_ISP_NOC, 0, 3),
683
684 /* M2M */
685 MUX(MOUT_CLKCMU_M2M_NOC, "mout_clkcmu_m2m_noc",
686 mout_clkcmu_m2m_noc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 0, 2),
687 MUX(MOUT_CLKCMU_M2M_JPEG, "mout_clkcmu_m2m_jpeg",
688 mout_clkcmu_m2m_jpeg_p, CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG, 0, 2),
689
690 /* MFC */
691 MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc",
692 mout_clkcmu_mfc_mfc_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
693 MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd",
694 mout_clkcmu_mfc_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
695
696 /* MFD */
697 MUX(MOUT_CLKCMU_MFD_NOC, "mout_clkcmu_mfd_noc",
698 mout_clkcmu_mfd_noc_p, CLK_CON_MUX_MUX_CLKCMU_MFD_NOC, 0, 3),
699
700 /* MIF */
701 MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch",
702 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
703 MUX(MOUT_CLKCMU_MIF_NOCP, "mout_clkcmu_mif_nocp",
704 mout_clkcmu_mif_nocp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0, 2),
705
706 /* MISC */
707 MUX(MOUT_CLKCMU_MISC_NOC, "mout_clkcmu_misc_noc",
708 mout_clkcmu_misc_noc_p, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC, 0, 2),
709
710 /* NOCL0 */
711 MUX(MOUT_CLKCMU_NOCL0_NOC, "mout_clkcmu_nocl0_noc",
712 mout_clkcmu_nocl0_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0, 3),
713
714 /* NOCL1 */
715 MUX(MOUT_CLKCMU_NOCL1_NOC, "mout_clkcmu_nocl1_noc",
716 mout_clkcmu_nocl1_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC, 0, 3),
717
718 /* NOCL2 */
719 MUX(MOUT_CLKCMU_NOCL2_NOC, "mout_clkcmu_nocl2_noc",
720 mout_clkcmu_nocl2_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC, 0, 3),
721
722 /* PERIC0 */
723 MUX(MOUT_CLKCMU_PERIC0_NOC, "mout_clkcmu_peric0_noc",
724 mout_clkcmu_peric0_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, 0, 1),
725 MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip",
726 mout_clkcmu_peric0_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
727
728 /* PERIC1 */
729 MUX(MOUT_CLKCMU_PERIC1_NOC, "mout_clkcmu_peric1_noc",
730 mout_clkcmu_peric1_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, 0, 1),
731 MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip",
732 mout_clkcmu_peric1_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
733
734 /* SDMA */
735 MUX(MOUT_CLKCMU_SDMA_NOC, "mout_clkcmu_sdma_noc",
736 mout_clkcmu_sdma_noc_p, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, 0, 3),
737
738 /* SNW */
739 MUX(MOUT_CLKCMU_SNW_NOC, "mout_clkcmu_snw_noc",
740 mout_clkcmu_snw_noc_p, CLK_CON_MUX_MUX_CLKCMU_SNW_NOC, 0, 3),
741
742 /* SSP */
743 MUX(MOUT_CLKCMU_SSP_NOC, "mout_clkcmu_ssp_noc",
744 mout_clkcmu_ssp_noc_p, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, 0, 2),
745
746 /* TAA */
747 MUX(MOUT_CLKCMU_TAA_NOC, "mout_clkcmu_taa_noc",
748 mout_clkcmu_taa_noc_p, CLK_CON_MUX_MUX_CLKCMU_TAA_NOC, 0, 3),
749 };
750
751 static const struct samsung_div_clock top_div_clks[] __initconst = {
752 /* CMU_TOP_PURECLKCOMP */
753
754 /* BOOST */
755 DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost",
756 "mout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
757
758 /* ACC */
759 DIV(DOUT_CLKCMU_ACC_NOC, "dout_clkcmu_acc_noc",
760 "mout_clkcmu_acc_noc", CLK_CON_DIV_CLKCMU_ACC_NOC, 0, 4),
761 DIV(DOUT_CLKCMU_ACC_ORB, "dout_clkcmu_acc_orb",
762 "mout_clkcmu_acc_orb", CLK_CON_DIV_CLKCMU_ACC_ORB, 0, 4),
763
764 /* APM */
765 DIV(DOUT_CLKCMU_APM_NOC, "dout_clkcmu_apm_noc",
766 "mout_clkcmu_apm_noc", CLK_CON_DIV_CLKCMU_APM_NOC, 0, 3),
767
768 /* AUD */
769 DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu",
770 "mout_clkcmu_aud_cpu", CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
771 DIV(DOUT_CLKCMU_AUD_NOC, "dout_clkcmu_aud_noc",
772 "mout_clkcmu_aud_noc", CLK_CON_DIV_CLKCMU_AUD_NOC, 0, 4),
773
774 /* CPUCL0 */
775 DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch",
776 "mout_clkcmu_cpucl0_switch",
777 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
778 DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster",
779 "mout_clkcmu_cpucl0_cluster",
780 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER, 0, 3),
781 DIV(DOUT_CLKCMU_CPUCL0_DBG, "dout_clkcmu_cpucl0_dbg",
782 "mout_clkcmu_cpucl0_dbg",
783 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
784
785 /* CPUCL1 */
786 DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch",
787 "mout_clkcmu_cpucl1_switch",
788 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
789 DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster",
790 "mout_clkcmu_cpucl1_cluster",
791 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER, 0, 3),
792
793 /* CPUCL2 */
794 DIV(DOUT_CLKCMU_CPUCL2_SWITCH, "dout_clkcmu_cpucl2_switch",
795 "mout_clkcmu_cpucl2_switch",
796 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
797 DIV(DOUT_CLKCMU_CPUCL2_CLUSTER, "dout_clkcmu_cpucl2_cluster",
798 "mout_clkcmu_cpucl2_cluster",
799 CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER, 0, 3),
800
801 /* DNC */
802 DIV(DOUT_CLKCMU_DNC_NOC, "dout_clkcmu_dnc_noc",
803 "mout_clkcmu_dnc_noc", CLK_CON_DIV_CLKCMU_DNC_NOC, 0, 4),
804
805 /* DPTX */
806 DIV(DOUT_CLKCMU_DPTX_NOC, "dout_clkcmu_dptx_noc",
807 "mout_clkcmu_dptx_noc", CLK_CON_DIV_CLKCMU_DPTX_NOC, 0, 4),
808 DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc",
809 "mout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
810 DIV(DOUT_CLKCMU_DPTX_DPOSC, "dout_clkcmu_dptx_dposc",
811 "mout_clkcmu_dptx_dposc", CLK_CON_DIV_CLKCMU_DPTX_DPOSC, 0, 5),
812
813 /* DPUB */
814 DIV(DOUT_CLKCMU_DPUB_NOC, "dout_clkcmu_dpub_noc",
815 "mout_clkcmu_dpub_noc", CLK_CON_DIV_CLKCMU_DPUB_NOC, 0, 4),
816 DIV(DOUT_CLKCMU_DPUB_DSIM, "dout_clkcmu_dpub_dsim",
817 "mout_clkcmu_dpub_dsim", CLK_CON_DIV_CLKCMU_DPUB_DSIM, 0, 4),
818
819 /* DPUF */
820 DIV(DOUT_CLKCMU_DPUF0_NOC, "dout_clkcmu_dpuf0_noc",
821 "mout_clkcmu_dpuf0_noc", CLK_CON_DIV_CLKCMU_DPUF0_NOC, 0, 4),
822 DIV(DOUT_CLKCMU_DPUF1_NOC, "dout_clkcmu_dpuf1_noc",
823 "mout_clkcmu_dpuf1_noc", CLK_CON_DIV_CLKCMU_DPUF1_NOC, 0, 4),
824 DIV(DOUT_CLKCMU_DPUF2_NOC, "dout_clkcmu_dpuf2_noc",
825 "mout_clkcmu_dpuf2_noc", CLK_CON_DIV_CLKCMU_DPUF2_NOC, 0, 4),
826
827 /* DSP */
828 DIV(DOUT_CLKCMU_DSP_NOC, "dout_clkcmu_dsp_noc",
829 "mout_clkcmu_dsp_noc", CLK_CON_DIV_CLKCMU_DSP_NOC, 0, 4),
830
831 /* G3D */
832 DIV(DOUT_CLKCMU_G3D_SWITCH, "dout_clkcmu_g3d_switch",
833 "mout_clkcmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
834 DIV(DOUT_CLKCMU_G3D_NOCP, "dout_clkcmu_g3d_nocp",
835 "mout_clkcmu_g3d_nocp", CLK_CON_DIV_CLKCMU_G3D_NOCP, 0, 3),
836
837 /* GNPU */
838 DIV(DOUT_CLKCMU_GNPU_NOC, "dout_clkcmu_gnpu_noc",
839 "mout_clkcmu_gnpu_noc", CLK_CON_DIV_CLKCMU_GNPU_NOC, 0, 4),
840
841 /* HSI0 */
842 DIV(DOUT_CLKCMU_HSI0_NOC, "dout_clkcmu_hsi0_noc",
843 "mout_clkcmu_hsi0_noc", CLK_CON_DIV_CLKCMU_HSI0_NOC, 0, 4),
844
845 /* HSI1 */
846 DIV(DOUT_CLKCMU_HSI1_NOC, "dout_clkcmu_hsi1_noc",
847 "mout_clkcmu_hsi1_noc", CLK_CON_DIV_CLKCMU_HSI1_NOC, 0, 4),
848 DIV(DOUT_CLKCMU_HSI1_USBDRD, "dout_clkcmu_hsi1_usbdrd",
849 "mout_clkcmu_hsi1_usbdrd", CLK_CON_DIV_CLKCMU_HSI1_USBDRD, 0, 4),
850 DIV(DOUT_CLKCMU_HSI1_MMC_CARD, "dout_clkcmu_hsi1_mmc_card",
851 "mout_clkcmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 0, 9),
852
853 /* HSI2 */
854 DIV(DOUT_CLKCMU_HSI2_NOC, "dout_clkcmu_hsi2_noc",
855 "mout_clkcmu_hsi2_noc", CLK_CON_DIV_CLKCMU_HSI2_NOC, 0, 4),
856 DIV(DOUT_CLKCMU_HSI2_NOC_UFS, "dout_clkcmu_hsi2_noc_ufs",
857 "mout_clkcmu_hsi2_noc_ufs", CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS, 0, 4),
858 DIV(DOUT_CLKCMU_HSI2_UFS_EMBD, "dout_clkcmu_hsi2_ufs_embd",
859 "mout_clkcmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 3),
860 DIV(DOUT_CLKCMU_HSI2_ETHERNET, "dout_clkcmu_hsi2_ethernet",
861 "mout_clkcmu_hsi2_ethernet", CLK_CON_DIV_CLKCMU_HSI2_ETHERNET, 0, 3),
862
863 /* ISP */
864 DIV(DOUT_CLKCMU_ISP_NOC, "dout_clkcmu_isp_noc",
865 "mout_clkcmu_isp_noc", CLK_CON_DIV_CLKCMU_ISP_NOC, 0, 4),
866
867 /* M2M */
868 DIV(DOUT_CLKCMU_M2M_NOC, "dout_clkcmu_m2m_noc",
869 "mout_clkcmu_m2m_noc", CLK_CON_DIV_CLKCMU_M2M_NOC, 0, 4),
870 DIV(DOUT_CLKCMU_M2M_JPEG, "dout_clkcmu_m2m_jpeg",
871 "mout_clkcmu_m2m_jpeg", CLK_CON_DIV_CLKCMU_M2M_JPEG, 0, 4),
872
873 /* MFC */
874 DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc",
875 "mout_clkcmu_mfc_mfc", CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
876 DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd",
877 "mout_clkcmu_mfc_wfd", CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
878
879 /* MFD */
880 DIV(DOUT_CLKCMU_MFD_NOC, "dout_clkcmu_mfd_noc",
881 "mout_clkcmu_mfd_noc", CLK_CON_DIV_CLKCMU_MFD_NOC, 0, 4),
882
883 /* MIF */
884 DIV(DOUT_CLKCMU_MIF_NOCP, "dout_clkcmu_mif_nocp",
885 "mout_clkcmu_mif_nocp", CLK_CON_DIV_CLKCMU_MIF_NOCP, 0, 4),
886
887 /* MISC */
888 DIV(DOUT_CLKCMU_MISC_NOC, "dout_clkcmu_misc_noc",
889 "mout_clkcmu_misc_noc", CLK_CON_DIV_CLKCMU_MISC_NOC, 0, 4),
890
891 /* NOCL0 */
892 DIV(DOUT_CLKCMU_NOCL0_NOC, "dout_clkcmu_nocl0_noc",
893 "mout_clkcmu_nocl0_noc", CLK_CON_DIV_CLKCMU_NOCL0_NOC, 0, 4),
894
895 /* NOCL1 */
896 DIV(DOUT_CLKCMU_NOCL1_NOC, "dout_clkcmu_nocl1_noc",
897 "mout_clkcmu_nocl1_noc", CLK_CON_DIV_CLKCMU_NOCL1_NOC, 0, 4),
898
899 /* NOCL2 */
900 DIV(DOUT_CLKCMU_NOCL2_NOC, "dout_clkcmu_nocl2_noc",
901 "mout_clkcmu_nocl2_noc", CLK_CON_DIV_CLKCMU_NOCL2_NOC, 0, 4),
902
903 /* PERIC0 */
904 DIV(DOUT_CLKCMU_PERIC0_NOC, "dout_clkcmu_peric0_noc",
905 "mout_clkcmu_peric0_noc", CLK_CON_DIV_CLKCMU_PERIC0_NOC, 0, 4),
906 DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip",
907 "mout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
908
909 /* PERIC1 */
910 DIV(DOUT_CLKCMU_PERIC1_NOC, "dout_clkcmu_peric1_noc",
911 "mout_clkcmu_peric1_noc", CLK_CON_DIV_CLKCMU_PERIC1_NOC, 0, 4),
912 DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip",
913 "mout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
914
915 /* SDMA */
916 DIV(DOUT_CLKCMU_SDMA_NOC, "dout_clkcmu_sdma_noc",
917 "mout_clkcmu_sdma_noc", CLK_CON_DIV_CLKCMU_SDMA_NOC, 0, 4),
918
919 /* SNW */
920 DIV(DOUT_CLKCMU_SNW_NOC, "dout_clkcmu_snw_noc",
921 "mout_clkcmu_snw_noc", CLK_CON_DIV_CLKCMU_SNW_NOC, 0, 4),
922
923 /* SSP */
924 DIV(DOUT_CLKCMU_SSP_NOC, "dout_clkcmu_ssp_noc",
925 "mout_clkcmu_ssp_noc", CLK_CON_DIV_CLKCMU_SSP_NOC, 0, 4),
926
927 /* TAA */
928 DIV(DOUT_CLKCMU_TAA_NOC, "dout_clkcmu_taa_noc",
929 "mout_clkcmu_taa_noc", CLK_CON_DIV_CLKCMU_TAA_NOC, 0, 4),
930 };
931
932 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
933 FFACTOR(DOUT_SHARED0_DIV1, "dout_shared0_div1",
934 "mout_shared0_pll", 1, 1, 0),
935 FFACTOR(DOUT_SHARED0_DIV2, "dout_shared0_div2",
936 "mout_shared0_pll", 1, 2, 0),
937 FFACTOR(DOUT_SHARED0_DIV3, "dout_shared0_div3",
938 "mout_shared0_pll", 1, 3, 0),
939 FFACTOR(DOUT_SHARED0_DIV4, "dout_shared0_div4",
940 "mout_shared0_pll", 1, 4, 0),
941 FFACTOR(DOUT_SHARED1_DIV1, "dout_shared1_div1",
942 "mout_shared1_pll", 1, 1, 0),
943 FFACTOR(DOUT_SHARED1_DIV2, "dout_shared1_div2",
944 "mout_shared1_pll", 1, 2, 0),
945 FFACTOR(DOUT_SHARED1_DIV3, "dout_shared1_div3",
946 "mout_shared1_pll", 1, 3, 0),
947 FFACTOR(DOUT_SHARED1_DIV4, "dout_shared1_div4",
948 "mout_shared1_pll", 1, 4, 0),
949 FFACTOR(DOUT_SHARED2_DIV1, "dout_shared2_div1",
950 "mout_shared2_pll", 1, 1, 0),
951 FFACTOR(DOUT_SHARED2_DIV2, "dout_shared2_div2",
952 "mout_shared2_pll", 1, 2, 0),
953 FFACTOR(DOUT_SHARED2_DIV3, "dout_shared2_div3",
954 "mout_shared2_pll", 1, 3, 0),
955 FFACTOR(DOUT_SHARED2_DIV4, "dout_shared2_div4",
956 "mout_shared2_pll", 1, 4, 0),
957 FFACTOR(DOUT_SHARED3_DIV1, "dout_shared3_div1",
958 "mout_shared3_pll", 1, 1, 0),
959 FFACTOR(DOUT_SHARED3_DIV2, "dout_shared3_div2",
960 "mout_shared3_pll", 1, 2, 0),
961 FFACTOR(DOUT_SHARED3_DIV3, "dout_shared3_div3",
962 "mout_shared3_pll", 1, 3, 0),
963 FFACTOR(DOUT_SHARED3_DIV4, "dout_shared3_div4",
964 "mout_shared3_pll", 1, 4, 0),
965 FFACTOR(DOUT_SHARED4_DIV1, "dout_shared4_div1",
966 "mout_shared4_pll", 1, 1, 0),
967 FFACTOR(DOUT_SHARED4_DIV2, "dout_shared4_div2",
968 "mout_shared4_pll", 1, 2, 0),
969 FFACTOR(DOUT_SHARED4_DIV3, "dout_shared4_div3",
970 "mout_shared4_pll", 1, 3, 0),
971 FFACTOR(DOUT_SHARED4_DIV4, "dout_shared4_div4",
972 "mout_shared4_pll", 1, 4, 0),
973 FFACTOR(DOUT_SHARED5_DIV1, "dout_shared5_div1",
974 "mout_shared5_pll", 1, 1, 0),
975 FFACTOR(DOUT_SHARED5_DIV2, "dout_shared5_div2",
976 "mout_shared5_pll", 1, 2, 0),
977 FFACTOR(DOUT_SHARED5_DIV3, "dout_shared5_div3",
978 "mout_shared5_pll", 1, 3, 0),
979 FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4",
980 "mout_shared5_pll", 1, 4, 0),
981 FFACTOR(DOUT_TCXO_DIV2, "dout_tcxo_div2",
982 "oscclk", 1, 2, 0),
983 };
984
985 static const struct samsung_cmu_info top_cmu_info __initconst = {
986 .pll_clks = top_pll_clks,
987 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
988 .mux_clks = top_mux_clks,
989 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
990 .div_clks = top_div_clks,
991 .nr_div_clks = ARRAY_SIZE(top_div_clks),
992 .fixed_factor_clks = top_fixed_factor_clks,
993 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
994 .nr_clk_ids = CLKS_NR_TOP,
995 .clk_regs = top_clk_regs,
996 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
997 };
998
exynosautov920_cmu_top_init(struct device_node * np)999 static void __init exynosautov920_cmu_top_init(struct device_node *np)
1000 {
1001 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
1002 }
1003
1004 /* Register CMU_TOP early, as it's a dependency for other early domains */
1005 CLK_OF_DECLARE(exynosautov920_cmu_top, "samsung,exynosautov920-cmu-top",
1006 exynosautov920_cmu_top_init);
1007
1008 /* ---- CMU_PERIC0 --------------------------------------------------------- */
1009
1010 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */
1011 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0600
1012 #define PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER 0x0610
1013 #define CLK_CON_MUX_MUX_CLK_PERIC0_I3C 0x1000
1014 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1004
1015 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1008
1016 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x100c
1017 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x1010
1018 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1014
1019 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1018
1020 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI 0x101c
1021 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI 0x1020
1022 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI 0x1024
1023 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1028
1024 #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800
1025 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804
1026 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808
1027 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c
1028 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810
1029 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814
1030 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818
1031 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI 0x181c
1032 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI 0x1820
1033 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI 0x1824
1034 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828
1035
1036 static const unsigned long peric0_clk_regs[] __initconst = {
1037 PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,
1038 PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER,
1039 CLK_CON_MUX_MUX_CLK_PERIC0_I3C,
1040 CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,
1041 CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,
1042 CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,
1043 CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,
1044 CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,
1045 CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,
1046 CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI,
1047 CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI,
1048 CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI,
1049 CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,
1050 CLK_CON_DIV_DIV_CLK_PERIC0_I3C,
1051 CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1052 CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1053 CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1054 CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1055 CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1056 CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1057 CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI,
1058 CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI,
1059 CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI,
1060 CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1061 };
1062
1063 /* List of parent clocks for Muxes in CMU_PERIC0 */
1064 PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" };
1065 PNAME(mout_peric0_noc_user_p) = { "oscclk", "dout_clkcmu_peric0_noc" };
1066 PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" };
1067
1068 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
1069 MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user",
1070 mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1),
1071 MUX(CLK_MOUT_PERIC0_NOC_USER, "mout_peric0_noc_user",
1072 mout_peric0_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, 4, 1),
1073 /* USI00 ~ USI08 */
1074 MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi",
1075 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1076 MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi",
1077 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1078 MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi",
1079 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1080 MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi",
1081 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1082 MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi",
1083 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1084 MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi",
1085 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1086 MUX(CLK_MOUT_PERIC0_USI06_USI, "mout_peric0_usi06_usi",
1087 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI, 0, 1),
1088 MUX(CLK_MOUT_PERIC0_USI07_USI, "mout_peric0_usi07_usi",
1089 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI, 0, 1),
1090 MUX(CLK_MOUT_PERIC0_USI08_USI, "mout_peric0_usi08_usi",
1091 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI, 0, 1),
1092 /* USI_I2C */
1093 MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c",
1094 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1095 /* USI_I3C */
1096 MUX(CLK_MOUT_PERIC0_I3C, "mout_peric0_i3c",
1097 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_I3C, 0, 1),
1098 };
1099
1100 static const struct samsung_div_clock peric0_div_clks[] __initconst = {
1101 /* USI00 ~ USI08 */
1102 DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
1103 "mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1104 0, 4),
1105 DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
1106 "mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1107 0, 4),
1108 DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
1109 "mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1110 0, 4),
1111 DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
1112 "mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1113 0, 4),
1114 DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
1115 "mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1116 0, 4),
1117 DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
1118 "mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1119 0, 4),
1120 DIV(CLK_DOUT_PERIC0_USI06_USI, "dout_peric0_usi06_usi",
1121 "mout_peric0_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI,
1122 0, 4),
1123 DIV(CLK_DOUT_PERIC0_USI07_USI, "dout_peric0_usi07_usi",
1124 "mout_peric0_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI,
1125 0, 4),
1126 DIV(CLK_DOUT_PERIC0_USI08_USI, "dout_peric0_usi08_usi",
1127 "mout_peric0_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI,
1128 0, 4),
1129 /* USI_I2C */
1130 DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
1131 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1132 /* USI_I3C */
1133 DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c",
1134 "mout_peric0_i3c", CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4),
1135 };
1136
1137 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
1138 .mux_clks = peric0_mux_clks,
1139 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
1140 .div_clks = peric0_div_clks,
1141 .nr_div_clks = ARRAY_SIZE(peric0_div_clks),
1142 .nr_clk_ids = CLKS_NR_PERIC0,
1143 .clk_regs = peric0_clk_regs,
1144 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
1145 .clk_name = "noc",
1146 };
1147
1148 /* ---- CMU_PERIC1 --------------------------------------------------------- */
1149
1150 /* Register Offset definitions for CMU_PERIC1 (0x10C00000) */
1151 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x600
1152 #define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x610
1153 #define CLK_CON_MUX_MUX_CLK_PERIC1_I3C 0x1000
1154 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x1004
1155 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1008
1156 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x100c
1157 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI 0x1010
1158 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI 0x1014
1159 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI 0x1018
1160 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI 0x101c
1161 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI 0x1020
1162 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI 0x1024
1163 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1028
1164 #define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
1165 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1804
1166 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
1167 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
1168 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
1169 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
1170 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI 0x1818
1171 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI 0x181c
1172 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820
1173 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824
1174 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1828
1175
1176 static const unsigned long peric1_clk_regs[] __initconst = {
1177 PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
1178 PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER,
1179 CLK_CON_MUX_MUX_CLK_PERIC1_I3C,
1180 CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
1181 CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
1182 CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
1183 CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI,
1184 CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI,
1185 CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI,
1186 CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI,
1187 CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI,
1188 CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI,
1189 CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
1190 CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
1191 CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1192 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1193 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1194 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
1195 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
1196 CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
1197 CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
1198 CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
1199 CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
1200 CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
1201 };
1202
1203 /* List of parent clocks for Muxes in CMU_PERIC1 */
1204 PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
1205 PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_clkcmu_peric1_noc" };
1206 PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
1207
1208 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
1209 MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
1210 mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
1211 MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user",
1212 mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1),
1213 /* USI09 ~ USI17 */
1214 MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
1215 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
1216 MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
1217 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
1218 MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
1219 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
1220 MUX(CLK_MOUT_PERIC1_USI12_USI, "mout_peric1_usi12_usi",
1221 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1),
1222 MUX(CLK_MOUT_PERIC1_USI13_USI, "mout_peric1_usi13_usi",
1223 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1),
1224 MUX(CLK_MOUT_PERIC1_USI14_USI, "mout_peric1_usi14_usi",
1225 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1),
1226 MUX(CLK_MOUT_PERIC1_USI15_USI, "mout_peric1_usi15_usi",
1227 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1),
1228 MUX(CLK_MOUT_PERIC1_USI16_USI, "mout_peric1_usi16_usi",
1229 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1),
1230 MUX(CLK_MOUT_PERIC1_USI17_USI, "mout_peric1_usi17_usi",
1231 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1),
1232 /* USI_I2C */
1233 MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
1234 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
1235 /* USI_I3C */
1236 MUX(CLK_MOUT_PERIC1_I3C, "mout_peric1_i3c",
1237 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1),
1238 };
1239
1240 static const struct samsung_div_clock peric1_div_clks[] __initconst = {
1241 /* USI09 ~ USI17 */
1242 DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
1243 "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1244 0, 4),
1245 DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
1246 "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1247 0, 4),
1248 DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
1249 "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1250 0, 4),
1251 DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
1252 "mout_peric1_usi12_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
1253 0, 4),
1254 DIV(CLK_DOUT_PERIC1_USI13_USI, "dout_peric1_usi13_usi",
1255 "mout_peric1_usi13_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
1256 0, 4),
1257 DIV(CLK_DOUT_PERIC1_USI14_USI, "dout_peric1_usi14_usi",
1258 "mout_peric1_usi14_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
1259 0, 4),
1260 DIV(CLK_DOUT_PERIC1_USI15_USI, "dout_peric1_usi15_usi",
1261 "mout_peric1_usi15_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
1262 0, 4),
1263 DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
1264 "mout_peric1_usi16_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
1265 0, 4),
1266 DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
1267 "mout_peric1_usi17_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
1268 0, 4),
1269 /* USI_I2C */
1270 DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
1271 "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
1272 /* USI_I3C */
1273 DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c",
1274 "mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
1275 };
1276
1277 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
1278 .mux_clks = peric1_mux_clks,
1279 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
1280 .div_clks = peric1_div_clks,
1281 .nr_div_clks = ARRAY_SIZE(peric1_div_clks),
1282 .nr_clk_ids = CLKS_NR_PERIC1,
1283 .clk_regs = peric1_clk_regs,
1284 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
1285 .clk_name = "noc",
1286 };
1287
1288 /* ---- CMU_MISC --------------------------------------------------------- */
1289
1290 /* Register Offset definitions for CMU_MISC (0x10020000) */
1291 #define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER 0x600
1292 #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
1293 #define CLK_CON_DIV_CLKCMU_OTP 0x1800
1294 #define CLK_CON_DIV_DIV_CLK_MISC_NOCP 0x1804
1295 #define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2 0x1808
1296
1297 static const unsigned long misc_clk_regs[] __initconst = {
1298 PLL_CON0_MUX_CLKCMU_MISC_NOC_USER,
1299 CLK_CON_MUX_MUX_CLK_MISC_GIC,
1300 CLK_CON_DIV_CLKCMU_OTP,
1301 CLK_CON_DIV_DIV_CLK_MISC_NOCP,
1302 CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2,
1303 };
1304
1305 /* List of parent clocks for Muxes in CMU_MISC */
1306 PNAME(mout_misc_noc_user_p) = { "oscclk", "dout_clkcmu_misc_noc" };
1307 PNAME(mout_misc_gic_p) = { "dout_misc_nocp", "oscclk" };
1308
1309 static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
1310 MUX(CLK_MOUT_MISC_NOC_USER, "mout_misc_noc_user",
1311 mout_misc_noc_user_p, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 4, 1),
1312 MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic",
1313 mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1),
1314 };
1315
1316 static const struct samsung_div_clock misc_div_clks[] __initconst = {
1317 DIV(CLK_DOUT_MISC_NOCP, "dout_misc_nocp",
1318 "mout_misc_noc_user", CLK_CON_DIV_DIV_CLK_MISC_NOCP,
1319 0, 3),
1320 };
1321
1322 static const struct samsung_fixed_factor_clock misc_fixed_factor_clks[] __initconst = {
1323 FFACTOR(CLK_DOUT_MISC_OTP, "dout_misc_otp",
1324 "oscclk", 1, 10, 0),
1325 FFACTOR(CLK_DOUT_MISC_OSC_DIV2, "dout_misc_osc_div2",
1326 "oscclk", 1, 2, 0),
1327 };
1328
1329 static const struct samsung_cmu_info misc_cmu_info __initconst = {
1330 .mux_clks = misc_mux_clks,
1331 .nr_mux_clks = ARRAY_SIZE(misc_mux_clks),
1332 .div_clks = misc_div_clks,
1333 .nr_div_clks = ARRAY_SIZE(misc_div_clks),
1334 .fixed_factor_clks = misc_fixed_factor_clks,
1335 .nr_fixed_factor_clks = ARRAY_SIZE(misc_fixed_factor_clks),
1336 .nr_clk_ids = CLKS_NR_MISC,
1337 .clk_regs = misc_clk_regs,
1338 .nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
1339 .clk_name = "noc",
1340 };
1341
1342 /* ---- CMU_HSI0 --------------------------------------------------------- */
1343
1344 /* Register Offset definitions for CMU_HSI0 (0x16000000) */
1345 #define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x600
1346 #define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB 0x1800
1347
1348 static const unsigned long hsi0_clk_regs[] __initconst = {
1349 PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER,
1350 CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
1351 };
1352
1353 /* List of parent clocks for Muxes in CMU_HSI0 */
1354 PNAME(mout_hsi0_noc_user_p) = { "oscclk", "dout_clkcmu_hsi0_noc" };
1355
1356 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
1357 MUX(CLK_MOUT_HSI0_NOC_USER, "mout_hsi0_noc_user",
1358 mout_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 4, 1),
1359 };
1360
1361 static const struct samsung_div_clock hsi0_div_clks[] __initconst = {
1362 DIV(CLK_DOUT_HSI0_PCIE_APB, "dout_hsi0_pcie_apb",
1363 "mout_hsi0_noc_user", CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
1364 0, 4),
1365 };
1366
1367 static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
1368 .mux_clks = hsi0_mux_clks,
1369 .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
1370 .div_clks = hsi0_div_clks,
1371 .nr_div_clks = ARRAY_SIZE(hsi0_div_clks),
1372 .nr_clk_ids = CLKS_NR_HSI0,
1373 .clk_regs = hsi0_clk_regs,
1374 .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
1375 .clk_name = "noc",
1376 };
1377
1378 /* ---- CMU_HSI1 --------------------------------------------------------- */
1379
1380 /* Register Offset definitions for CMU_HSI1 (0x16400000) */
1381 #define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x600
1382 #define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER 0x610
1383 #define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER 0x620
1384 #define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD 0x1000
1385
1386 static const unsigned long hsi1_clk_regs[] __initconst = {
1387 PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER,
1388 PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER,
1389 PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER,
1390 CLK_CON_MUX_MUX_CLK_HSI1_USBDRD,
1391 };
1392
1393 /* List of parent clocks for Muxes in CMU_HSI1 */
1394 PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"};
1395 PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };
1396 PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" };
1397 PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" };
1398
1399 static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
1400 MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user",
1401 mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 4, 1),
1402 MUX(CLK_MOUT_HSI1_NOC_USER, "mout_hsi1_noc_user",
1403 mout_hsi1_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 4, 1),
1404 MUX(CLK_MOUT_HSI1_USBDRD_USER, "mout_hsi1_usbdrd_user",
1405 mout_hsi1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 4, 1),
1406 MUX(CLK_MOUT_HSI1_USBDRD, "mout_hsi1_usbdrd",
1407 mout_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 4, 1),
1408 };
1409
1410 static const struct samsung_cmu_info hsi1_cmu_info __initconst = {
1411 .mux_clks = hsi1_mux_clks,
1412 .nr_mux_clks = ARRAY_SIZE(hsi1_mux_clks),
1413 .nr_clk_ids = CLKS_NR_HSI1,
1414 .clk_regs = hsi1_clk_regs,
1415 .nr_clk_regs = ARRAY_SIZE(hsi1_clk_regs),
1416 .clk_name = "noc",
1417 };
1418
exynosautov920_cmu_probe(struct platform_device * pdev)1419 static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
1420 {
1421 const struct samsung_cmu_info *info;
1422 struct device *dev = &pdev->dev;
1423
1424 info = of_device_get_match_data(dev);
1425 exynos_arm64_register_cmu(dev, dev->of_node, info);
1426
1427 return 0;
1428 }
1429
1430 static const struct of_device_id exynosautov920_cmu_of_match[] = {
1431 {
1432 .compatible = "samsung,exynosautov920-cmu-peric0",
1433 .data = &peric0_cmu_info,
1434 }, {
1435 .compatible = "samsung,exynosautov920-cmu-peric1",
1436 .data = &peric1_cmu_info,
1437 }, {
1438 .compatible = "samsung,exynosautov920-cmu-misc",
1439 .data = &misc_cmu_info,
1440 }, {
1441 .compatible = "samsung,exynosautov920-cmu-hsi0",
1442 .data = &hsi0_cmu_info,
1443 }, {
1444 .compatible = "samsung,exynosautov920-cmu-hsi1",
1445 .data = &hsi1_cmu_info,
1446 },
1447 { }
1448 };
1449
1450 static struct platform_driver exynosautov920_cmu_driver __refdata = {
1451 .driver = {
1452 .name = "exynosautov920-cmu",
1453 .of_match_table = exynosautov920_cmu_of_match,
1454 .suppress_bind_attrs = true,
1455 },
1456 .probe = exynosautov920_cmu_probe,
1457 };
1458
exynosautov920_cmu_init(void)1459 static int __init exynosautov920_cmu_init(void)
1460 {
1461 return platform_driver_register(&exynosautov920_cmu_driver);
1462 }
1463 core_initcall(exynosautov920_cmu_init);
1464