Changes in Kbuild

202432ae8a6948ab6c88b56eaf2848a23637d9f0 - Merge branch 'for-7.1/cxl-region-refactor' into cxl-for-next

Fri, 03 Apr 2026 21:30:57 +0200

Merge branch 'for-7.1/cxl-region-refactor' into cxl-for-nextRefactor CXL core/region code to make region code more manageable bysplitting out DAX and PMEM code from RAM handling code.cxl/core: use cleanup.h for devm_cxl_add_dax_regioncxl/core/region: move dax region device logic into region_dax.ccxl/core/region: move pmem region driver logic into region_pmem.c List of files: /linux/tools/testing/cxl/Kbuild

549b5c12ef06441dbde4718f16e23c547f5592d7 - tools/testing/cxl: Test dax_hmem takeover of CXL regions

Fri, 27 Mar 2026 06:28:21 +0100

tools/testing/cxl: Test dax_hmem takeover of CXL regionsWhen platform firmware is committed to publishing EFI_CONVENTIONAL_MEMORYin the memory map, but CXL fails to assemble the region, dax_hmem canattempt to attach a dax device to the memory range.Take advantage of the new ability to support multiple "hmem_platform"devices, and to enable regression testing of several scenarios:* CXL correctly assembles a region, check dax_hmem fails to attach dax* CXL fails to assemble a region, check dax_hmem successfully attaches dax* Check that loading the dax_cxl driver loads the dax_hmem driver* Attempt to race cxl_mock_mem async probe vs dax_hmem probe flushing. Check that both positive and negative cases.Signed-off-by: Dan Williams Reviewed-by: Ira Weiny Reviewed-by: Dave Jiang Reviewed-by: Alison Schofield Tested-by: Alison Schofield Link: https://patch.msgid.link/20260327052821.440749-10-dan.j.williams@intel.comSigned-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

d747cf98f091e56beeed5233e8992fea59401011 - cxl/core/region: move dax region device logic into region_dax.c

Fri, 27 Mar 2026 03:02:02 +0100

cxl/core/region: move dax region device logic into region_dax.ccore/region.c is overloaded with per-region control logic (pmem, dax,sysram, etc). Move the CXL DAX region device infrastructure fromregion.c into a new region_dax.c file.This will also allow us to add additional dax-driver integration pathsthat don't further dirty the core region.c logic.No functional changes.Signed-off-by: Gregory Price Co-developed-by: Ira Weiny Signed-off-by: Ira Weiny Reviewed-by: Ira Weiny Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20260327020203.876122-3-gourry@gourry.netSigned-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

8a1ec5fb2360d6fc0183cbe7de68c7a4e611d120 - cxl/core/region: move pmem region driver logic into region_pmem.c

Fri, 27 Mar 2026 03:02:01 +0100

cxl/core/region: move pmem region driver logic into region_pmem.ccore/region.c is overloaded with per-region control logic (pmem, dax,sysram, etc). Move the pmem region driver logic from region.c intoregion_pmem.c make it clear that this code only applies to pmem regions.No functional changes.[ dj: Fixed up some tabbing issues, may be from original code. ]Signed-off-by: Gregory Price Co-developed-by: Ira Weiny Signed-off-by: Ira Weiny Reviewed-by: Ira Weiny Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20260327020203.876122-2-gourry@gourry.netSigned-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

63fbf275fa9f18f7020fb8acf54fa107e51d0f23 - Merge branch 'for-7.0/cxl-prm-translation' into cxl-for-next

Wed, 04 Feb 2026 18:53:33 +0100

Merge branch 'for-7.0/cxl-prm-translation' into cxl-for-nextAdd support for normalized CXL address translation through ACPI PRM methodto support AMD Zen5 platforms. Including a conventions doc that explainshow the translation is implemented and for future implementations thatneed such setup to comply with the current implementation method.cxl: Disable HPA/SPA translation handlers for Normalized Addressingcxl/region: Factor out code into cxl_region_setup_poison()cxl/atl: Lock decoders that need address translationcxl: Enable AMD Zen5 address translation using ACPI PRMTcxl/acpi: Prepare use of EFI runtime servicescxl: Introduce callback for HPA address ranges translationcxl/region: Use region data to get the root decodercxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos()cxl/region: Separate region parameter setup and region constructioncxl: Simplify cxl_root_ops allocation and handlingcxl/region: Store HPA range in struct cxl_regioncxl/region: Store root decoder in struct cxl_regioncxl/region: Rename misleading variable name @hpa to @hpa_rangeDocumentation/driver-api/cxl: ACPI PRM Address Translation Support and AMD Zen5 enablementcxl, doc: Moving conventions in separate filescxl, doc: Remove isonum.txt inclusion List of files: /linux/tools/testing/cxl/Kbuild

af74daf91652f15b82560bb93850d2ec8bbfa976 - cxl: Enable AMD Zen5 address translation using ACPI PRMT

Tue, 27 Jan 2026 19:12:31 +0100

cxl: Enable AMD Zen5 address translation using ACPI PRMTAdd AMD Zen5 support for address translation.Zen5 systems may be configured to use 'Normalized addresses'. Then,host physical addresses (HPA) are different from their system physicaladdresses (SPA). The endpoint has its own physical address space andan incoming HPA is already converted to the device's physical address(DPA). Thus it has interleaving disabled and CXL endpoints areprogrammed passthrough (DPA == HPA).Host Physical Addresses (HPAs) need to be translated from the endpointto its CXL host bridge, esp. to identify the endpoint's root decoderand region's address range. ACPI Platform Runtime Mechanism (PRM)provides a handler to translate the DPA to its SPA. This is documentedin: AMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh ACPI v6.5 Porting Guide, Publication # 58088 https://www.amd.com/en/search/documentation/hub.htmlWith Normalized Addressing this PRM handler must be used to translatean HPA of an endpoint to its SPA.Do the following to implement AMD Zen5 address translation:Introduce a new file core/atl.c to handle ACPI PRM specific addresstranslation code. Naming is loosely related to the kernel's AMDAddress Translation Library (CONFIG_AMD_ATL) but implementation doesnot depend on it, nor it is vendor specific. Use Kbuild and Kconfigoptions respectively to enable the code depending on architecture andplatform options.AMD Zen5 systems support the ACPI PRM CXL Address Translation firmwarecall (see ACPI v6.5 Porting Guide, Address Translation - CXL DPA toSystem Physical Address). Firmware enables the PRM handler if theplatform has address translation implemented. Check firmware andkernel support of ACPI PRM using the specific GUID. On success enableaddress translation by setting up the earlier introduced root portcallback, see function cxl_prm_setup_translation(). Setup is done incxl_setup_prm_address_translation(), it is the only function thatneeds to be exported. For low level PRM firmware calls, use the ACPIframework.Identify the region's interleaving ways by inspecting the addressranges. Also determine the interleaving granularity using the addresstranslation callback. Note that the position of the chunk from oneinterleaving block to the next may vary and thus cannot be consideredconstant. Address offsets larger than the interleaving block sizecannot be used to calculate the granularity. Thus, probe thegranularity using address translation for various HPAs in the sameinterleaving block.[ dj: Add atl.o build to cxl_test ]Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Gregory Price Signed-off-by: Robert Richter Link: https://patch.msgid.link/20260114164837.1076338-11-rrichter@amd.comSigned-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

7f5ff740ce0bcde242dafcc3f9bb3cbe6b5b8f3a - cxl/port: Move dport RAS setup to dport add time

Sat, 31 Jan 2026 01:04:00 +0100

cxl/port: Move dport RAS setup to dport add timeTowards the end goal of making all CXL RAS capability handling uniformacross host bridge ports, upstream switch ports, and endpoint ports, movedport RAS setup. Move it to cxl_switch_port_probe() context for switch / VHdports (via cxl_port_add_dport()) and cxl_endpoint_port_probe() context foran RCH dport. Rename the RAS setup helper to devm_cxl_dport_ras_setup() forsymmetry with devm_cxl_switch_port_decoders_setup().Only the RCH version needs to be exported and the cxl_test mocking can bedeleted with a dev_is_pci() check on the dport_dev.Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Terry Bowman Signed-off-by: Dan Williams Link: https://patch.msgid.link/20260131000403.2135324-7-dan.j.williams@intel.comSigned-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

3864cb60dad5a6c1bd9f444740cf541a1d8cda99 - cxl/port: Move dport probe operations to a driver event

Sat, 31 Jan 2026 01:03:59 +0100

cxl/port: Move dport probe operations to a driver eventIn preparation for adding more register setup to the cxl_port_add_dport()path (for RAS register mapping), move the dport creation event to a drivercallback. This achieves two goals, it puts driver operations logicallywhere they belong, in a driver, and it obviates the gymnastics ofDECLARE_TESTABLE() which just makes a mess of grepping for CXL symbols.In other words, a driver callback is less of an ongoing maintenance burdenthan this DECLARE_TESTABLE arrangement that does not scale and diminishesthe grep-ability of the codebase.cxl_port_add_dport() moves mostly unmodified from drivers/cxl/core/port.c.The only deliberate change is that it now assumes that the device_lock isheld on entry and the driver is attached (just like cxl_port_probe()).Reviewed-by: Terry Bowman Tested-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Signed-off-by: Dan Williams Link: https://patch.msgid.link/20260131000403.2135324-6-dan.j.williams@intel.comSigned-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

0ff60f2ec3e4043a442e805f80f8a2445113ec8f - cxl/pci: Move CXL driver's RCH error handling into core/ras_rch.c

Wed, 14 Jan 2026 19:20:29 +0100

cxl/pci: Move CXL driver's RCH error handling into core/ras_rch.cRestricted CXL Host (RCH) protocol error handling uses a procedure distinctfrom the CXL Virtual Hierarchy (VH) handling. This is because of thedifferences in the RCH and VH topologies. Improve the maintainability andadd ability to enable/disable RCH handling.Move and combine the RCH handling code into a single block conditionallycompiled with the CONFIG_CXL_RCH_RAS kernel config.Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Link: https://patch.msgid.link/20260114182055.46029-9-terry.bowman@amd.comSigned-off-by: Dan Williams Signed-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

7ff8b1d60881c5f97b5ae426e14d2822917d3b69 - cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c

Wed, 14 Jan 2026 19:20:28 +0100

cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.cCreate new config CONFIG_CXL_RAS and put all CXL RAS items behind theconfig. The config will depend on CPER and PCIE AER to build. Move therelated VH RAS code from core/pci.c to core/ras.c.Restricted CXL host (RCH) RAS functions will be moved in a future patch.Cc: Robert Richter Reviewed-by: Joshua Hahn Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang Reviewed-by: Alison Schofield Co-developed-by: Terry Bowman Signed-off-by: Terry Bowman Reviewed-by: Dan Williams Link: https://patch.msgid.link/20260114182055.46029-8-terry.bowman@amd.comSigned-off-by: Dan Williams Signed-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

b5bea8cee55c50117e08675a2c15f35a6bef2472 - Merge branch 'for-6.19/cxl-misc' into cxl-for-next

Tue, 18 Nov 2025 23:41:53 +0100

Merge branch 'for-6.19/cxl-misc' into cxl-for-next- remove unused mock function for cxl_rcd_component_reg_phys() List of files: /linux/tools/testing/cxl/Kbuild

26c5b0d9c080ff753c66de0b19d6e3e014a24877 - cxl/test: remove unused mock function for cxl_rcd_component_reg_phys()

Tue, 18 Nov 2025 19:22:02 +0100

cxl/test: remove unused mock function for cxl_rcd_component_reg_phys()Since commit 733b57f262b0 ("cxl/pci: Early setup RCH dport component registers from RCRB")is not necessary under mocking tests.[ dj: Fixup commit representation flagged by checkpatch. ][ dj: Ammend subject line to indicate which function. ]Signed-off-by: Alejandro Lucero Reviewed-by: Dave Jiang > ---Reviewed-by: Ira Weiny Link: https://patch.msgid.link/20251118182202.2083244-1-alejandro.lucero-palau@amd.comSigned-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

7ec9db66cc552f2f8a6779c16d01a2a01eccedde - Merge branch 'for-6.19/cxl-elc-test' into cxl-for-next

Mon, 17 Nov 2025 19:05:47 +0100

Merge branch 'for-6.19/cxl-elc-test' into cxl-for-nextExtended linear cache unit testing support - Standardize CXL auto region size - Add cxl_test CFMWS support for extended linear cache - Add support for acpi extended linear cache List of files: /linux/tools/testing/cxl/Kbuild

68f4a852e18329e84bb5d36168a45b0a52cdf236 - cxl/test: Add support for acpi extended linear cache

Mon, 17 Nov 2025 15:46:11 +0100

cxl/test: Add support for acpi extended linear cacheAdd the mock wrappers for hmat_get_extended_linear_cache_size() in orderto emulate the ACPI helper function for the regions that are mock'd bycxl_test.Reviewed-by: Jonathan Cameron Tested-by: Alison Schofield Reviewed-by: Alison Schofield Reviewed-by: Fabio M. De Francesco Link: https://patch.msgid.link/20251117144611.903692-4-dave.jiang@intel.comSigned-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

3f5b8f7f34f6d8e63c02d177341e43ebee4c2d36 - cxl/port: Remove devm_cxl_port_enumerate_dports()

Sat, 27 Sep 2025 12:07:09 +0200

cxl/port: Remove devm_cxl_port_enumerate_dports()devm_cxl_port_enumerate_dports() is not longer used after below commitcommit 4f06d81e7c6a ("cxl: Defer dport allocation for switch ports")Delete it and the relevant interface implemented in cxl_test.Signed-off-by: Li Ming Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

644685abc16b58b3afcc2feb0ac14e86476ca2ed - cxl/test: Adjust the mock version of devm_cxl_switch_port_decoders_setup()

Fri, 29 Aug 2025 20:09:26 +0200

cxl/test: Adjust the mock version of devm_cxl_switch_port_decoders_setup()With devm_cxl_switch_port_decoders_setup() being called within cxl_coreinstead of by the port driver probe, adjustments are needed to deal withcircular symbol dependency when this function is being mock'd. Add theappropriate changes to get around the circular dependency.Reviewed-by: Alison Schofield Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

d96eb90d9ca6e4652c8a23d48c94364aa061fdc4 - cxl/test: Add mock version of devm_cxl_add_dport_by_dev()

Fri, 29 Aug 2025 20:09:25 +0200

cxl/test: Add mock version of devm_cxl_add_dport_by_dev()devm_cxl_add_dport_by_dev() outside of cxl_test is done through PCIhierarchy. However with cxl_test, it needs to be done through theplatform device hierarchy. Add the mock function fordevm_cxl_add_dport_by_dev().When cxl_core calls a cxl_core exported function and that function ismocked by cxl_test, the call chain causes a circular dependency issue. Danprovided a workaround to avoid this issue. Apply the method to changes fromthe late dport allocation changes in order to enable cxl-test.In cxl_core they are defined with "__" added in front of the function. Amacro is used to define the original function names for when non-testversion of the kernel is built. A bit of macros and typedefs are used toallow mocking of those functions in cxl_test.Co-developed-by: Dan Williams Signed-off-by: Dan Williams Reviewed-by: Jonathan Cameron Reviewed-by: Li Ming Tested-by: Alison Schofield Tested-by: Robert Richter Signed-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

68d5d9734c12fce20ad493fe24738ab2019108c0 - cxl/test: Refactor decoder setup to reduce cxl_test burden

Fri, 29 Aug 2025 20:09:23 +0200

cxl/test: Refactor decoder setup to reduce cxl_test burdenGroup the decoder setup code in switch and endpoint port probe into asingle function for each to reduce the number of functions to be mockedin cxl_test. Introduce devm_cxl_switch_port_decoders_setup() anddevm_cxl_endpoint_decoders_setup(). These two functions will be mockedinstead with some functions optimized out since the mock version doesnot do anything. Remove devm_cxl_setup_hdm(),devm_cxl_add_passthrough_decoder(), and devm_cxl_enumerate_decoders() incxl_test mock code. In turn, mock_cxl_add_passthrough_decoder() can beremoved since cxl_test does not setup passthrough decoders.__wrap_cxl_hdm_decode_init() and __wrap_cxl_dvsec_rr_decode() can beremoved as well since they only return 0 when called.[dj: drop 'struct cxl_port' forward declaration (Robert)]Suggested-by: Robert Richter Reviewed-by: Alison Schofield Reviewed-by: Jonathan Cameron Reviewed-by: Robert Richter Signed-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

12b3d697c812aaf356e82d9e1f351fbb2ea97500 - cxl: Remove core/acpi.c and cxl core dependency on ACPI

Fri, 11 Jul 2025 17:15:27 +0200

cxl: Remove core/acpi.c and cxl core dependency on ACPIFrom Dave [1]:"""It was a mistake to introduce core/acpi.c and putting ACPI dependency oncxl_core when adding the extended linear cache support."""Current implementation calls hmat_get_extended_linear_cache_size() ofthe ACPI subsystem. That external reference causes issue runningcxl_test as there is no way to "mock" that function and ignore it whenusing cxl test.Instead of working around that using cxlrd ops and extensivelyexpanding cxl_test code [1], just move HMAT calls out of the coremodule to cxl_acpi. Implement this by adding a @cache_size member tostruct cxl_root_decoder. During initialization the cache size isdetermined and added to the root decoder object in cxl_acpi. Later onin cxl_core the cache_size parameter is used to setup extended linearcaching.[1] https://patch.msgid.link/20250610172938.139428-1-dave.jiang@intel.com[ dj: Remove core/acpi.o from tools/testing/cxl/Kbuild ][ dj: Add kdoc for cxlrd->cache_size ]Cc: Dave Jiang Signed-off-by: Robert Richter Reviewed-by: Alison Schofield Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Link: https://patch.msgid.link/20250711151529.787470-1-rrichter@amd.comSigned-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild

0c6e6f1357cbdc158d555346a728aa4aeb0d7011 - cxl/edac: Add CXL memory device patrol scrub control feature

Wed, 21 May 2025 14:47:41 +0200

cxl/edac: Add CXL memory device patrol scrub control featureCXL spec 3.2 section 8.2.10.9.11.1 describes the device patrol scrubcontrol feature. The device patrol scrub proactively locates and makescorrections to errors in regular cycle.Allow specifying the number of hours within which the patrol scrub must becompleted, subject to minimum and maximum limits reported by the device.Also allow disabling scrub allowing trade-off error rates againstperformance.Add support for patrol scrub control on CXL memory devices.Register with the EDAC device driver, which retrieves the scrub attributedescriptors from EDAC scrub and exposes the sysfs scrub control attributesto userspace. For example, scrub control for the CXL memory device"cxl_mem0" is exposed in /sys/bus/edac/devices/cxl_mem0/scrubX/.Additionally, add support for region-based CXL memory patrol scrub control.CXL memory regions may be interleaved across one or more CXL memorydevices. For example, region-based scrub control for "cxl_region1" isexposed in /sys/bus/edac/devices/cxl_region1/scrubX/.[dj: A few formatting fixes from Jonathan]Reviewed-by: Dave Jiang Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Signed-off-by: Shiju Jose Reviewed-by: Alison Schofield Acked-by: Dan Williams Link: https://patch.msgid.link/20250521124749.817-4-shiju.jose@huawei.comSigned-off-by: Dave Jiang List of files: /linux/tools/testing/cxl/Kbuild