Changes in glymur.dtsi

aab799b1bdd1ff3e6912f96e66c910b8a5d011bb - Merge tag 'soc-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Wed, 17 Jun 2026 20:16:56 +0200

Merge tag 'soc-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socPull SoC devicetree updates from Arnd Bergmann: "There are fewer devicetree updates this time that the last few ones, with five SoC types getting added: - Qualcomm Dragonwing IPQ9650 is a new wireless networking SoC using four Cortex-A55 and one Cortex-A78 core, which is a significant upgrade from older generations - ZTE zx297520v3 is an older low-end wireless SoC using a single Cortex-A53 core, which so far can only run 32-bit kernels. This brings back the ZX family of chips that was removed in 2021 after support for the original zx296702 and zx296718 chips was never completed. - Renesas R-Car M3Le (R8A779MD) is a variant of the R-Car M3-N (R8A77965) automotive SoC. - Apple t8122 (M3) is the 2023 generation of their laptop SoCs, which has now been reverse-engineered to the point of having initial kernel support for five laptop models. - ASPEED AST27xx is their first baseboard managment controller using a 64-bit core, the Cortex-A35, following earlier generations using ARMv5/v6/v7 CPUs. These all come with one or more initial boards, and in total there are 39 new boards getting added across SoC families, including: - Two NAS boxes using the old Cortina Systems Gemini SoC based on an ARMv4 FA526 CPU core - 18 industrial embedded boards using NXP i.MX6/8/9 and LX2160A SoCs from Variscite, Toradex and SolidRun, plus a number of overlays for combinations with additional boards - One new carrier board and SoM using TI K3 AM62x, in addition to new overlays for older SoMs - Two new boards using Spacemit K3 (no relation with TI) RISC-V SoCs. - Three phones from Google, Nothing and Motorola, all using Qualcomm Snapdragon SoCs - AST26xx BMC support for two server boards While there is still a significant number of patches improving hardware support for the existing boards across vendors (NXP, Qualcomm, Renesas, Rockchips, Mediatek, ...), a much smaller number of cleanups and warning fixes have made it in this time"* tag 'soc-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (665 commits) arm64: dts: aspeed: Fix duplicate pinctrl labels and address scheme arm64: dts: bst: enable eMMC controller in C1200 dt-bindings: display/lvds-codec: add ti,sn65lvds93 arm64: dts: allwinner: a523: Add missing GPIO interrupt arm64: dts: lx2160a-rev2: avoid 32-bit pcie window system ram overlap arm64: dts: aspeed: Add initial AST27xx SoC device tree arm64: Kconfig: Add ASPEED SoC family Kconfig support dt-bindings: arm: aspeed: Add AST2700 board compatible arm64: dts: allwinner: a523: add gpadc node arm64: dts: allwinner: Add EL2 virtual timer interrupt ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node dt-bindings: media: sun6i-a31-isp: Add optional interconnect properties dt-bindings: media: sun6i-a31-csi: Add optional interconnect properties arm64: dts: imx{91,93}-phyboard-segin: Add peb-av-18 overlays arm64: dts: imx93-var-som-symphony: enable ADC arm64: dts: imx93-var-som-symphony: enable TPM3 PWM arm64: dts: imx93-var-som-symphony: keep RGB_SEL low arm64: dts: imx93-var-som-symphony: enable UART7 arm64: dts: imx93-var-som-symphony: add TPM support arm64: dts: imx91-var-som-symphony: fix RGB_SEL handling ... List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

db9900e518b2992cbbcbfb7572c2d436ec0feb6d - arm64: dts: qcom: glymur: Add qfprom efuse node

Tue, 31 Mar 2026 15:54:21 +0200

arm64: dts: qcom: glymur: Add qfprom efuse nodeAdd the qfprom (Qualcomm Fuse ROM) efuse node and gpu speed bin childnode for Glymur SoCSigned-off-by: Pankaj Patil Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260331-glymur-qfprom-v1-2-5b4284d23c80@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

1f7d0c42a08d157294b8dce4ac162c2853f287d0 - arm64: dts: qcom: glymur: add coresight nodes

Wed, 20 May 2026 03:42:45 +0200

arm64: dts: qcom: glymur: add coresight nodesAdd CoreSight nodes to enable trace paths like TPDM->ETF/STM->ETF.These devices are part of the AOSS, CDSP, QDSS, PCIe5, TraceNoc andsome small subsystems, such as GCC, IPCC, PMU and so on.Delete cti_wpss DT node on Mahua since this device will cause NoC issueon Mahua device.Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20260520-add-coresight-nodes-for-glymur-v6-1-0bfdcdfce3ec@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

ecabfe832b817bd1c1fdb8841d7bc706bf621ef1 - arm64: dts: qcom: glymur: Fix wrong interrupt number for i2c19

Mon, 18 May 2026 11:52:53 +0200

arm64: dts: qcom: glymur: Fix wrong interrupt number for i2c19The i2c19 node at 0x88c000 uses GIC SPI 584, but that interruptbelongs to the neighboring i2c18/spi18 node at 0x888000. The correctinterrupt for i2c19 is GIC SPI 585, as used by its sibling nodesspi19 and uart19 which share the same register base and clock.Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi")Signed-off-by: Gopikrishna Garmidi Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260518-glymur-fix-i2c19-irq-v1-1-7d5968bd9b2b@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

cd1d174c75f70fb0d7204802551aeaeb84689b59 - arm64: dts: qcom: glymur: Add ADSP and CDSP for Glymur SoC

Fri, 13 Mar 2026 13:08:13 +0100

arm64: dts: qcom: glymur: Add ADSP and CDSP for Glymur SoCAdd remoteproc PAS loader for ADSP and CDSP with its fastrpc nodes.Signed-off-by: Sibi Sankar Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260313120814.1312410-5-sibi.sankar@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

675fec65df73b525c12cb7a1c1ef54fcc3296d7c - arm64: dts: qcom: Add support for MM clock controllers for Glymur

Fri, 10 Apr 2026 05:49:04 +0200

arm64: dts: qcom: Add support for MM clock controllers for GlymurAdd the device nodes for the multimedia clock controllers videocc, gpuccand gxclkctl.Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260410-glymur_mmcc_dt_config_v2-v3-1-acce9d106e72@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

12c97d1c15f926cd430bf5cdf8ffe878cb478165 - arm64: dts: qcom: glymur: Drop RPMh CXO clocks from QMP PHYs

Tue, 14 Apr 2026 19:05:51 +0200

arm64: dts: qcom: glymur: Drop RPMh CXO clocks from QMP PHYsOn Glymur, all QMP PHYs except the one used by USB SS0 take theirreference clock from the TCSR clock controller. Since these TCSR clocksalready derive from RPMH_CXO_CLK as their sole parent, there is no needto provide an extra `clkref` clock to the PHY nodes.Drop the extra RPMh CXO clock inputs and use the TCSR clocks as the PHYreference clocks instead.This also fixes the devicetree schema validation, as the bindings do notallow a separate `clkref` clock.Fixes: 4eee57dd4df9 ("arm64: dts: qcom: glymur: Add USB related nodes")Reported-by: Krzysztof Kozlowski Reported-by: Rob Herring Closes: https://lore.kernel.org/r/20260410145205.GA554754-robh@kernel.org/Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260414-dts-glymur-drop-rpmh-cxo-clk-from-qmpphys-v1-1-ab12d77c4aec@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

347fa2fa64e1cef0c7897522896c0c66e734c82b - arm64: dts: qcom: glymur: Mark USB SS1 and SS2 as role-switch capable

Wed, 15 Apr 2026 09:52:56 +0200

arm64: dts: qcom: glymur: Mark USB SS1 and SS2 as role-switch capableLike USB SS0, the USB SS1 and SS2 controllers on Glymur also supportUSB role switching.Describe this by adding the 'usb-role-switch' property to both controllers.Fixes: 4eee57dd4df9 ("arm64: dts: qcom: glymur: Add USB related nodes")Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260415-dts-qcom-glymur-usb-role-switch-fix-v1-1-409e1a257f1f@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

f5fb358c7d9161a6abfd2c619b2999c7e51cd2fe - arm64: dts: qcom: glymur: Enable cpufreq cooling devices

Thu, 07 May 2026 08:29:50 +0200

arm64: dts: qcom: glymur: Enable cpufreq cooling devicesAdd cooling-cells property to the CPU nodes to support cpufreqcooling devices.Signed-off-by: Haritha S K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260507-glymur_cpu_freq-v1-1-d566cc1d32c3@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

08569936a11b8ed20f95783d80d1ba2f4e93fa93 - arm64: dts: qcom: Use GIC_SPI macro for interrupt-map

Tue, 07 Apr 2026 22:18:40 +0200

arm64: dts: qcom: Use GIC_SPI macro for interrupt-mapMake the complicated interrupt-map property (with multiple '0' entries)a bit more readable by using known define for GIC_SPI.Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260407201839.25759-2-krzysztof.kozlowski@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

93e08fdc55f227847dc9b249fd5eb43403e7e8b9 - arm64: dts: qcom: glymur: Add crypto engine and BAM

Tue, 05 May 2026 09:40:04 +0200

arm64: dts: qcom: glymur: Add crypto engine and BAMOn almost all Qualcomm platforms, including Glymur, there is a Cryptoengine IP block to which the CPU can off-load cryptographic computationsfor achieving acceleration.The engine is also DMA capable due to the presence of an associated BusAccess Manager (BAM) module.Describe the Crypto engine and its BAM.Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260505-glymur_crypto_enablement-v2-2-bf115aeb1459@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

46eccc1034c3740b07b58c125190bbb99247c9de - arm64: dts: qcom: glymur: Fix cache and SRAM simple_bus_reg warnings

Sun, 05 Apr 2026 15:39:29 +0200

arm64: dts: qcom: glymur: Fix cache and SRAM simple_bus_reg warningsCorrect the unit address of cache controller and SRAM nodes in QualcommGlymur SoC DTSI to fix W=1 DTC warnings: glymur.dtsi:5876.36-5908.5: Warning (simple_bus_reg): /soc@0/system-cache-controller@20400000: simple-bus unit address format error, expected "21800000" glymur.dtsi:5917.23-5934.5: Warning (simple_bus_reg): /soc@0/sram@81e08000: simple-bus unit address format error, expected "81e08600"Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi")Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-2-1f2c7b74a93f@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

cd66b6d256f94e40922941e14d7f9390d35d072b - arm64: dts: qcom: glymur: Fix USB simple_bus_reg warning

Sun, 05 Apr 2026 15:39:28 +0200

arm64: dts: qcom: glymur: Fix USB simple_bus_reg warningCorrect the unit address of USB node in Qualcomm Glymur SoC DTSI to fixW=1 DTC warning: glymur.dtsi:4027.23-4093.5: Warning (simple_bus_reg): /soc@0/usb@a2f8800: simple-bus unit address format error, expected "a200000"Fixes: 4eee57dd4df9 ("arm64: dts: qcom: glymur: Add USB related nodes")Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-1-1f2c7b74a93f@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

fee828abbd9dd4af41a7aa2b9671e5c23cfc3635 - arm64: dts: qcom: patch mahua thermal zones by label

Fri, 20 Mar 2026 03:51:00 +0100

arm64: dts: qcom: patch mahua thermal zones by labelUpdating DT nodes by the full path is fragile and frowned upon, it'seasy to miss the rename of the node in the main tree. Add necessarylabels and patch thermal zones for Mahua using those labels.Signed-off-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260320-mahua-fix-thermals-v1-1-8957bf976c90@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

bf2a06f36e32a3802842ebc7e1fc87e8e7ce2e72 - arm64: dts: qcom: glymur: Add missing opp entry

Wed, 25 Mar 2026 17:21:50 +0100

arm64: dts: qcom: glymur: Add missing opp entryAdd missing opp entry that corresponds to highest ddr frequencyfor Glymur/Mahua SoCs.Fixes: e4945894c1cb ("arm64: dts: qcom: glymur: Add glymur BWMONs")Signed-off-by: Pragnesh Papaniya Link: https://lore.kernel.org/r/20260325-bwmon_fixes-v1-1-9433f9d4c276@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

652b7210b8b92eaf121d4ed12f99e81cedbacb0a - arm64: dts: qcom: glymur: Describe display-related nodes

Fri, 20 Mar 2026 12:16:43 +0100

arm64: dts: qcom: glymur: Describe display-related nodesThe MDSS (Mobile Display SubSystem) on Glymur provides four DisplayPortcontrollers. Describe them together with the display controller and eDPPHY. Also add the combo PHY link and vco_div clocks to the display clockcontroller, and connect the PHYs and DP endpoints in the graph.Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260320-dts-qcom-glymur-crd-add-edp-v7-1-ca415560447e@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

4eee57dd4df9f388cb2d7369205e1d51b83c341b - arm64: dts: qcom: glymur: Add USB related nodes

Fri, 20 Mar 2026 11:56:52 +0100

arm64: dts: qcom: glymur: Add USB related nodesThe Glymur USB subsystem contains three USB 3.2 Gen 2 controllers,one USB 3.2 multi-port controller, and one USB 2.0-only controller.This includes five SS USB QMP PHYs (three combo and two UNI) and six M31eUSB2 PHYs.All controllers are based on SNPS DWC3, so describe them as Qualcommflattened DWC3 nodes.Signed-off-by: Wesley Cheng Co-developed-by: Abel Vesa Reviewed-by: Konrad Dybcio Tested-by: Pankaj Patil Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260320-dts-qcom-glymur-add-usb-support-v7-1-ba367eda6010@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

73b24193e71a7bb934c21e660e8f331960e2cfd0 - arm64: dts: qcom: glymur: Add glymur BWMONs

Mon, 02 Mar 2026 12:46:56 +0100

arm64: dts: qcom: glymur: Add glymur BWMONsAdd the CPU BWMON nodes for glymur SoCs.Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya Link: https://lore.kernel.org/r/20260302-glymur_bwmon_dt-v1-1-f4939d75bd47@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

c1014a629d0181ce7739caf1448fb8e22d4cba9c - arm64: dts: qcom: Add Mahua SoC and CRD

Wed, 18 Mar 2026 13:41:00 +0100

arm64: dts: qcom: Add Mahua SoC and CRDIntroduce support for the Mahua SoC and the CRD based on it. Some ofthe notable differences are the absent CPU cluster, interconnect, TLMM,thermal zones and adjusted PCIe west clocks. Everything else shouldwork as-is.Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Gopikrishna Garmidi Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260318124100.212992-4-gopikrishna.garmidi@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi

5044a0b0307a3377dabbb0a2a653a30e388d16cc - arm64: dts: qcom: glymur: Fix deprecated cpu compatibles

Fri, 13 Mar 2026 11:34:39 +0100

arm64: dts: qcom: glymur: Fix deprecated cpu compatiblesThe generic Qualcomm Oryon CPU compatible used by the GlymurSoC is deprecated and incorrect since it uses a single compatibleto describe two different core variants. It is now replaced withtwo different core-specific compatibles based on MIDR part andvariant number.CPUS 0-5:MIDR_EL1[PART_NUM] - 0x2MIDR_EL1[VARIANT] - 0x2CPUS 6-17:MIDR_EL1[PART_NUM] - 0x2MIDR_EL1[VARIANT] - 0x1Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi")Signed-off-by: Sibi Sankar Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260313103439.1255247-3-sibi.sankar@oss.qualcomm.comSigned-off-by: Bjorn Andersson List of files: /linux/scripts/dtc/include-prefixes/arm64/qcom/glymur.dtsi