Changes in Makefile

70cb95c736807da2c4952423c9f9afe470341996 - Merge tag 'soc-drivers-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Wed, 17 Jun 2026 20:21:40 +0200

Merge tag 'soc-drivers-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socPull SoC driver updates from Arnd Bergmann: "There are a few added drivers, but mostly the normal maintenance to drivers for firmware, memory controller and other soc specific hardware: - The NXP QuickEngine gets modern MSI support, which allows some cleanups to the GICv3 irqchip chip driver - A new SoC specific driver for the Renesas R-Car MFIS unit is added, encapsulating support for the on-chip mailbox and hwspinlock implementations that are not easily separated into individual drivers - The Qualcomm SoC drivers add support for additional SoC implementations, and flexibility around power management for the serial-engine driver as well as probing the LLCC driver using custom hardware descriptions inside of the device itself. - Added support for the Samsung thermal management unit - A cleanup to the Tegra 'PMC' driver interfaces to remove legacy APIs and allow multiple PMC instances everywhere. - Updates to the TI SCI and KNAS drivers to improve suspend/resume support. - Minor driver changes for mediatek, xilinx, allwinner, aspeed, tegra, broadcom, amd, microchip and starfive specific drivers - Memory controller updates for Tegra and Renesas for additional SoC types and other improvements. - Firmware driver updates for Arm FF-A, SMCCC and SCMI interfaces, to update driver probing, object lifetimes and address minor bugs"* tag 'soc-drivers-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (189 commits) Revert "firmware: zynqmp: Add dynamic CSU register discovery and sysfs interface" Revert "Documentation: ABI: add sysfs interface for ZynqMP CSU registers" memory: tegra234: drop dead NULL check in tegra234_mc_icc_aggregate() memory: tegra264: drop redundant tegra264_mc_icc_aggregate() memory: tegra186-emc: stop borrowing MC aggregate hook for EMC soc: aspeed: cleanup dead default for ASPEED_SOCINFO firmware: tegra: bpmp: Add support for multi-socket platforms firmware: tegra: bpmp: Propagate debugfs errors soc/tegra: pmc: Add Tegra238 support soc/tegra: pmc: Restrict power-off handler to Nexus 7 soc/tegra: pmc: Populate powergate debugfs only when needed soc/tegra: pmc: Move legacy code behind CONFIG_ARM guard soc/tegra: pmc: Remove unused legacy functions soc/tegra: pmc: Create PMC context dynamically firmware: samsung: acpm: remove compile-testing stubs firmware: samsung: acpm: Add devm_acpm_get_by_phandle helper firmware: samsung: acpm: Add TMU protocol support firmware: samsung: acpm: Make acpm_ops const and access via pointer firmware: samsung: acpm: Drop redundant _ops suffix in acpm_ops members firmware: samsung: acpm: Annotate rx_data->cmd with __counted_by_ptr ... List of files: /linux/drivers/irqchip/Makefile

71619266e0a272ef5ef137a661e8e3f1711c2aba - irqchip/loongarch-ir: Add IR (interrupt redirection) irqchip support

Wed, 13 May 2026 03:28:35 +0200

irqchip/loongarch-ir: Add IR (interrupt redirection) irqchip supportThe main function of the redirect interrupt controller is to managethe redirected-interrupt table, which consists of many redirected entries.When MSI interrupts are requested, the driver creates a correspondingredirected entry that describes the target CPU/vector number and theoperating mode of the interrupt. The redirected interrupt module has anindependent cache, and during the interrupt routing process, it willprioritize the redirected entries that hit the cache. The irqchip drivercan invalidate certain entry caches via a command queue.Co-developed-by: Liupu Wang Signed-off-by: Liupu Wang Signed-off-by: Tianyang Zhang Signed-off-by: Thomas Gleixner Acked-by: Huacai Chen Link: https://patch.msgid.link/20260513012839.2856463-5-zhangtianyang@loongson.cn List of files: /linux/drivers/irqchip/Makefile

ac2005bba8d938c03c3856a96f20afaa42002635 - irqchip/starfive: Rename jh8100 to jhb100

Thu, 16 Apr 2026 08:47:48 +0200

irqchip/starfive: Rename jh8100 to jhb100The StarFive JH8100 SoC was discontinued before production. The newlytaped-out JHB100 SoC uses the same interrupt controller IP. Rename thedriver file, Kconfig symbol, and internal references from "jh8100" to"jhb100" to accurately reflect the supported hardware.Signed-off-by: Changhuang Liang Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260416064751.632138-3-changhuang.liang@starfivetech.com List of files: /linux/drivers/irqchip/Makefile

d3587cc4a5e691539c46f327f8d510c1bc482b7e - irqchip/aspeed-intc: Remove AST2700-A0 support

Tue, 07 Apr 2026 05:08:07 +0200

irqchip/aspeed-intc: Remove AST2700-A0 supportThe existing AST2700 interrupt controller driver ("aspeed,ast2700-intc-ic")was written against the A0 pre-production design.From A1 onwards (retained in the A2 production silicon), the interruptfabric was re-architected: interrupt routing is programmable and interruptoutputs can be directed to multiple upstream controllers (PSP GIC,Secondary Service Processor (SSP) NVIC, Tertiary Service Processor (TSP)NVIC, and Boot MCU interrupt controller). This design requires routeresolution and a controller hierarchy model which the A0 driver cannotrepresent.Remove driver support for A0 in favour of the driver for the A2 productiondesign.Signed-off-by: Ryan Chen Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260407-irqchip-v5-4-c0b0a300a057@aspeedtech.com List of files: /linux/drivers/irqchip/Makefile

46e39ee92d14bf2248d6404119b816047144de4e - irqchip/ast2700-intc: Add KUnit tests for route resolution

Tue, 07 Apr 2026 05:08:06 +0200

irqchip/ast2700-intc: Add KUnit tests for route resolutionAdd a KUnit suite for aspeed_intc0_resolve_route().Cover invalid arguments, invalid domain/range data, connected anddisconnected mappings, and malformed upstream range cases.Signed-off-by: Ryan Chen Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260407-irqchip-v5-3-c0b0a300a057@aspeedtech.com List of files: /linux/drivers/irqchip/Makefile

07825e41519abb8ac13d6d1c553af47f57775f6b - irqchip/ast2700-intc: Add AST2700-A2 support

Tue, 07 Apr 2026 05:08:05 +0200

irqchip/ast2700-intc: Add AST2700-A2 supportThe AST2700 interrupt fabric is shared by multiple integrated processors(PSP/SSP/TSP/BootMCU), each with its own interrupt controller and its owndevicetree view of the system. As a result, interrupt routing cannot betreated as fixed: the valid route for a peripheral interrupt depends onwhich processor is consuming it.The INTC0 driver models this by creating a hierarchical irqdomain underthe upstream interrupt controller selected by the interrupt-parentproperty in the devicetree. Information derived from this relationshipis incorporated into the route resolution logic for the controller.The INTC1 driver implements the banked INTM-fed controller and forwardsinterrupts toward INTC0, without embedding assumptions about the finaldestination processor.Signed-off-by: Ryan Chen Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20260407-irqchip-v5-2-c0b0a300a057@aspeedtech.com List of files: /linux/drivers/irqchip/Makefile

14b1cbcc6cec0b02298f4adf717646cd943b7ef6 - fsl-mc: Remove legacy MSI implementation

Tue, 24 Feb 2026 11:09:35 +0100

fsl-mc: Remove legacy MSI implementationGet rid of most of the fsl_mc MSI infrastructure, which is now replacedby common code.Reviewed-by: Ioana Ciornei Tested-by: Ioana Ciornei # LX2160ARDB, LS2088ARDBTested-by: Sascha Bischoff Signed-off-by: Marc Zyngier Acked-by: Thomas Gleixner Link: https://lore.kernel.org/r/20260224100936.3752303-6-maz@kernel.orgSigned-off-by: Christophe Leroy (CS GROUP) List of files: /linux/drivers/irqchip/Makefile

13e7b3305b647cf58c47c979fe8a04e08caa6098 - irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver

Mon, 01 Dec 2025 12:29:31 +0100

irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driverThe Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have anInterrupt Controller (ICU) that supports interrupts from external pins IRQ0to IRQ15, and SEI, and software-triggered interrupts INTCPU0 to INTCPU15.INTCPU0 to INTCPU13, IRQ0 to IRQ13 are non-safety interrupts, whileINTCPU14, INTCPU15, IRQ14, IRQ15 and SEI are safety interrupts, and areexposed via a separate register space.Signed-off-by: Cosmin Tanislav Signed-off-by: Thomas Gleixner Link: https://patch.msgid.link/20251201112933.488801-3-cosmin-gabriel.tanislav.xa@renesas.com List of files: /linux/drivers/irqchip/Makefile

c620438ef2ac80b09269a9ae3c0b4fe5add19bfe - irqchip: Kill irq-partition-percpu

Mon, 20 Oct 2025 14:29:40 +0200

irqchip: Kill irq-partition-percpuThis code is now completely unused, and nobody will ever miss it.Signed-off-by: Marc Zyngier Signed-off-by: Thomas Gleixner Tested-by: Will Deacon Link: https://patch.msgid.link/20251020122944.3074811-24-maz@kernel.org List of files: /linux/drivers/irqchip/Makefile

aa43953e862c031ff66e44353c88beb7a449e80d - irqchip: Add driver for the RPMI system MSI service group

Mon, 18 Aug 2025 06:09:09 +0200

irqchip: Add driver for the RPMI system MSI service groupThe RPMI specification defines a system MSI service group whichallows application processors to receive MSIs upon system eventssuch as graceful shutdown/reboot request, CPU hotplug event, memoryhotplug event, etc.Add an irqchip driver for the RISC-V RPMI system MSI service groupto directly receive system MSIs in Linux kernel.Reviewed-by: Thomas Gleixner Signed-off-by: Anup Patel Link: https://lore.kernel.org/r/20250818040920.272664-14-apatel@ventanamicro.comSigned-off-by: Paul Walmsley List of files: /linux/drivers/irqchip/Makefile

63eb28bb1402891b1ad2be02a530f29a9dd7f1cd - Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Thu, 31 Jul 2025 02:14:01 +0200

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmPull kvm updates from Paolo Bonzini: "ARM: - Host driver for GICv5, the next generation interrupt controller for arm64, including support for interrupt routing, MSIs, interrupt translation and wired interrupts - Use FEAT_GCIE_LEGACY on GICv5 systems to virtualize GICv3 VMs on GICv5 hardware, leveraging the legacy VGIC interface - Userspace control of the 'nASSGIcap' GICv3 feature, allowing userspace to disable support for SGIs w/o an active state on hardware that previously advertised it unconditionally - Map supporting endpoints with cacheable memory attributes on systems with FEAT_S2FWB and DIC where KVM no longer needs to perform cache maintenance on the address range - Nested support for FEAT_RAS and FEAT_DoubleFault2, allowing the guest hypervisor to inject external aborts into an L2 VM and take traps of masked external aborts to the hypervisor - Convert more system register sanitization to the config-driven implementation - Fixes to the visibility of EL2 registers, namely making VGICv3 system registers accessible through the VGIC device instead of the ONE_REG vCPU ioctls - Various cleanups and minor fixes LoongArch: - Add stat information for in-kernel irqchip - Add tracepoints for CPUCFG and CSR emulation exits - Enhance in-kernel irqchip emulation - Various cleanups RISC-V: - Enable ring-based dirty memory tracking - Improve perf kvm stat to report interrupt events - Delegate illegal instruction trap to VS-mode - MMU improvements related to upcoming nested virtualization s390x - Fixes x86: - Add CONFIG_KVM_IOAPIC for x86 to allow disabling support for I/O APIC, PIC, and PIT emulation at compile time - Share device posted IRQ code between SVM and VMX and harden it against bugs and runtime errors - Use vcpu_idx, not vcpu_id, for GA log tag/metadata, to make lookups O(1) instead of O(n) - For MMIO stale data mitigation, track whether or not a vCPU has access to (host) MMIO based on whether the page tables have MMIO pfns mapped; using VFIO is prone to false negatives - Rework the MSR interception code so that the SVM and VMX APIs are more or less identical - Recalculate all MSR intercepts from scratch on MSR filter changes, instead of maintaining shadow bitmaps - Advertise support for LKGS (Load Kernel GS base), a new instruction that's loosely related to FRED, but is supported and enumerated independently - Fix a user-triggerable WARN that syzkaller found by setting the vCPU in INIT_RECEIVED state (aka wait-for-SIPI), and then putting the vCPU into VMX Root Mode (post-VMXON). Trying to detect every possible path leading to architecturally forbidden states is hard and even risks breaking userspace (if it goes from valid to valid state but passes through invalid states), so just wait until KVM_RUN to detect that the vCPU state isn't allowed - Add KVM_X86_DISABLE_EXITS_APERFMPERF to allow disabling interception of APERF/MPERF reads, so that a "properly" configured VM can access APERF/MPERF. This has many caveats (APERF/MPERF cannot be zeroed on vCPU creation or saved/restored on suspend and resume, or preserved over thread migration let alone VM migration) but can be useful whenever you're interested in letting Linux guests see the effective physical CPU frequency in /proc/cpuinfo - Reject KVM_SET_TSC_KHZ for vm file descriptors if vCPUs have been created, as there's no known use case for changing the default frequency for other VM types and it goes counter to the very reason why the ioctl was added to the vm file descriptor. And also, there would be no way to make it work for confidential VMs with a "secure" TSC, so kill two birds with one stone - Dynamically allocation the shadow MMU's hashed page list, and defer allocating the hashed list until it's actually needed (the TDP MMU doesn't use the list) - Extract many of KVM's helpers for accessing architectural local APIC state to common x86 so that they can be shared by guest-side code for Secure AVIC - Various cleanups and fixes x86 (Intel): - Preserve the host's DEBUGCTL.FREEZE_IN_SMM when running the guest. Failure to honor FREEZE_IN_SMM can leak host state into guests - Explicitly check vmcs12.GUEST_DEBUGCTL on nested VM-Enter to prevent L1 from running L2 with features that KVM doesn't support, e.g. BTF x86 (AMD): - WARN and reject loading kvm-amd.ko instead of panicking the kernel if the nested SVM MSRPM offsets tracker can't handle an MSR (which is pretty much a static condition and therefore should never happen, but still) - Fix a variety of flaws and bugs in the AVIC device posted IRQ code - Inhibit AVIC if a vCPU's ID is too big (relative to what hardware supports) instead of rejecting vCPU creation - Extend enable_ipiv module param support to SVM, by simply leaving IsRunning clear in the vCPU's physical ID table entry - Disable IPI virtualization, via enable_ipiv, if the CPU is affected by erratum #1235, to allow (safely) enabling AVIC on such CPUs - Request GA Log interrupts if and only if the target vCPU is blocking, i.e. only if KVM needs a notification in order to wake the vCPU - Intercept SPEC_CTRL on AMD if the MSR shouldn't exist according to the vCPU's CPUID model - Accept any SNP policy that is accepted by the firmware with respect to SMT and single-socket restrictions. An incompatible policy doesn't put the kernel at risk in any way, so there's no reason for KVM to care - Drop a superfluous WBINVD (on all CPUs!) when destroying a VM and use WBNOINVD instead of WBINVD when possible for SEV cache maintenance - When reclaiming memory from an SEV guest, only do cache flushes on CPUs that have ever run a vCPU for the guest, i.e. don't flush the caches for CPUs that can't possibly have cache lines with dirty, encrypted data Generic: - Rework irqbypass to track/match producers and consumers via an xarray instead of a linked list. Using a linked list leads to O(n^2) insertion times, which is hugely problematic for use cases that create large numbers of VMs. Such use cases typically don't actually use irqbypass, but eliminating the pointless registration is a future problem to solve as it likely requires new uAPI - Track irqbypass's "token" as "struct eventfd_ctx *" instead of a "void *", to avoid making a simple concept unnecessarily difficult to understand - Decouple device posted IRQs from VFIO device assignment, as binding a VM to a VFIO group is not a requirement for enabling device posted IRQs - Clean up and document/comment the irqfd assignment code - Disallow binding multiple irqfds to an eventfd with a priority waiter, i.e. ensure an eventfd is bound to at most one irqfd through the entire host, and add a selftest to verify eventfd:irqfd bindings are globally unique - Add a tracepoint for KVM_SET_MEMORY_ATTRIBUTES to help debug issues related to private <=> shared memory conversions - Drop guest_memfd's .getattr() implementation as the VFS layer will call generic_fillattr() if inode_operations.getattr is NULL - Fix issues with dirty ring harvesting where KVM doesn't bound the processing of entries in any way, which allows userspace to keep KVM in a tight loop indefinitely - Kill off kvm_arch_{start,end}_assignment() and x86's associated tracking, now that KVM no longer uses assigned_device_count as a heuristic for either irqbypass usage or MDS mitigation Selftests: - Fix a comment typo - Verify KVM is loaded when getting any KVM module param so that attempting to run a selftest without kvm.ko loaded results in a SKIP message about KVM not being loaded/enabled (versus some random parameter not existing) - Skip tests that hit EACCES when attempting to access a file, and print a "Root required?" help message. In most cases, the test just needs to be run with elevated permissions"* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (340 commits) Documentation: KVM: Use unordered list for pre-init VGIC registers RISC-V: KVM: Avoid re-acquiring memslot in kvm_riscv_gstage_map() RISC-V: KVM: Use find_vma_intersection() to search for intersecting VMAs RISC-V: perf/kvm: Add reporting of interrupt events RISC-V: KVM: Enable ring-based dirty memory tracking RISC-V: KVM: Fix inclusion of Smnpm in the guest ISA bitmap RISC-V: KVM: Delegate illegal instruction fault to VS mode RISC-V: KVM: Pass VMID as parameter to kvm_riscv_hfence_xyz() APIs RISC-V: KVM: Factor-out g-stage page table management RISC-V: KVM: Add vmid field to struct kvm_riscv_hfence RISC-V: KVM: Introduce struct kvm_gstage_mapping RISC-V: KVM: Factor-out MMU related declarations into separate headers RISC-V: KVM: Use ncsr_xyz() in kvm_riscv_vcpu_trap_redirect() RISC-V: KVM: Implement kvm_arch_flush_remote_tlbs_range() RISC-V: KVM: Don't flush TLB when PTE is unchanged RISC-V: KVM: Replace KVM_REQ_HFENCE_GVMA_VMID_ALL with KVM_REQ_TLB_FLUSH RISC-V: KVM: Rename and move kvm_riscv_local_tlb_sanitize() RISC-V: KVM: Drop the return value of kvm_riscv_vcpu_aia_init() RISC-V: KVM: Check kvm_riscv_vcpu_alloc_vector_context() return value KVM: arm64: selftests: Add FEAT_RAS EL2 registers to get-reg-list ... List of files: /linux/drivers/irqchip/Makefile

695949d8b16f11f2f172d8d0c7ccc1ae09ed6cb7 - irqchip/gic-v5: Add GICv5 IWB support

Thu, 03 Jul 2025 12:25:19 +0200

irqchip/gic-v5: Add GICv5 IWB supportThe GICv5 architecture implements the Interrupt Wire Bridge (IWB) inorder to support wired interrupts that cannot be connected directlyto an IRS and instead uses the ITS to translate a wire event intoan IRQ signal.Add the wired-to-MSI IWB driver to manage IWB wired interrupts.An IWB is connected to an ITS and it has its own deviceID for allinterrupt wires that it manages; the IWB input wire number must beexposed to the ITS as an eventID with a 1:1 mapping.This eventID is not programmable and therefore requires a newmsi_alloc_info_t flag to make sure the ITS driver does not allocatean eventid for the wire but rather it uses the msi_alloc_info_t.hwirqnumber to gather the ITS eventID.Co-developed-by: Sascha Bischoff Signed-off-by: Sascha Bischoff Co-developed-by: Timothy Hayes Signed-off-by: Timothy Hayes Signed-off-by: Lorenzo Pieralisi Reviewed-by: Marc Zyngier Cc: Thomas Gleixner Cc: Marc Zyngier Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-29-12e71f1b3528@kernel.orgSigned-off-by: Marc Zyngier List of files: /linux/drivers/irqchip/Makefile

57d72196dfc8502b7e376ecdffb11c4f8766f26d - irqchip/gic-v5: Add GICv5 ITS support

Thu, 03 Jul 2025 12:25:18 +0200

irqchip/gic-v5: Add GICv5 ITS supportThe GICv5 architecture implements Interrupt Translation Service(ITS) components in order to translate events coming from peripheralsinto interrupt events delivered to the connected IRSes.Events (ie MSI memory writes to ITS translate frame), are translatedby the ITS using tables kept in memory.ITS translation tables for peripherals is kept in memory storage(device table [DT] and Interrupt Translation Table [ITT]) thatis allocated by the driver on boot.Both tables can be 1- or 2-level; the structure is chosen by thedriver after probing the ITS HW parameters and checking theallowed table splits and supported {device/event}_IDbits.DT table entries are allocated on demand (ie when a device isprobed); the DT table is sized using the number of supporteddeviceID bits in that that's a system design decision (ie thenumber of deviceID bits implemented should reflect the numberof devices expected in a system) therefore it makes sense toallocate a DT table that can cater for the maximum number ofdevices.DT and ITT tables are allocated using the kmalloc interface;the allocation size may be smaller than a page or larger,and must provide contiguous memory pages.LPIs INTIDs backing the device events are allocated one-by-oneand only upon Linux IRQ allocation; this to avoid preallocatinga large number of LPIs to cover the HW device MSI vectorsize whereas few MSI entries are actually enabled by a device.ITS cacheability/shareability attributes are programmedaccording to the provided firmware ITS description.The GICv5 partially reuses the GICv3 ITS MSI parent infrastructureand adds functions required to retrieve the ITS translate frameaddresses out of msi-map and msi-parent properties to implementthe GICv5 ITS MSI parent callbacks.Co-developed-by: Sascha Bischoff Signed-off-by: Sascha Bischoff Co-developed-by: Timothy Hayes Signed-off-by: Timothy Hayes Signed-off-by: Lorenzo Pieralisi Reviewed-by: Marc Zyngier Cc: Thomas Gleixner Cc: Marc Zyngier Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-28-12e71f1b3528@kernel.orgSigned-off-by: Marc Zyngier List of files: /linux/drivers/irqchip/Makefile

b4ead12d95002b9c65e3c646cf73e0a91c608024 - irqchip/gic-v3: Rename GICv3 ITS MSI parent

Thu, 03 Jul 2025 12:25:16 +0200

irqchip/gic-v3: Rename GICv3 ITS MSI parentThe GICv5 ITS will reuse some GICv3 ITS MSI parent functions thereforeit makes sense to keep the code functionality in a compilation unitshared by the two drivers.Rename the GICv3 ITS MSI parent file and update the relatedKconfig/Makefile entries to pave the way for code sharing.Signed-off-by: Lorenzo Pieralisi Reviewed-by: Marc Zyngier Cc: Thomas Gleixner Cc: Marc Zyngier Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-26-12e71f1b3528@kernel.orgSigned-off-by: Marc Zyngier List of files: /linux/drivers/irqchip/Makefile

5cb1b6dab2def316671ea2565291a86ad58b884c - irqchip/gic-v5: Add GICv5 IRS/SPI support

Thu, 03 Jul 2025 12:25:11 +0200

irqchip/gic-v5: Add GICv5 IRS/SPI supportThe GICv5 Interrupt Routing Service (IRS) component implementsinterrupt management and routing in the GICv5 architecture.A GICv5 system comprises one or more IRSes, that togetherhandle the interrupt routing and state for the system.An IRS supports Shared Peripheral Interrupts (SPIs), that areinterrupt sources directly connected to the IRS; they do notrely on memory for storage. The number of supported SPIs isfixed for a given implementation and can be probed through IRSIDR registers.SPI interrupt state and routing are managed through GICv5instructions.Each core (PE in GICv5 terms) in a GICv5 system is identified withan Interrupt AFFinity ID (IAFFID).An IRS manages a set of cores that are connected to it.Firmware provides a topology description that the driver usesto detect to which IRS a CPU (ie an IAFFID) is associated with.Use probeable information and firmware description to initializethe IRSes and implement GICv5 IRS SPIs support through anSPI-specific IRQ domain.The GICv5 IRS driver:- Probes IRSes in the system to detect SPI ranges- Associates an IRS with a set of cores connected to it- Adds an IRQchip structure for SPI handlingSPIs priority is set to a value corresponding to the lowestpermissible priority in the system (taking into account theimplemented priority bits of the IRS and CPU interface).Since all IRQs are set to the same priority value, the valueitself does not matter as long as it is a valid one.Co-developed-by: Sascha Bischoff Signed-off-by: Sascha Bischoff Co-developed-by: Timothy Hayes Signed-off-by: Timothy Hayes Signed-off-by: Lorenzo Pieralisi Reviewed-by: Marc Zyngier Cc: Will Deacon Cc: Thomas Gleixner Cc: Catalin Marinas Cc: Marc Zyngier Acked-by: Catalin Marinas Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-21-12e71f1b3528@kernel.orgSigned-off-by: Marc Zyngier List of files: /linux/drivers/irqchip/Makefile

7ec80fb3f025825e860b433685fb801d6de34bf3 - irqchip/gic-v5: Add GICv5 PPI support

Thu, 03 Jul 2025 12:25:10 +0200

irqchip/gic-v5: Add GICv5 PPI supportThe GICv5 CPU interface implements support for PE-Private PeripheralInterrupts (PPI), that are handled (enabled/prioritized/delivered)entirely within the CPU interface hardware.To enable PPI interrupts, implement the baseline GICv5 host kerneldriver infrastructure required to handle interrupts on a GICv5 system.Add the exception handling code path and definitions for GICv5instructions.Add GICv5 PPI handling code as a specific IRQ domain to:- Set-up PPI priority- Manage PPI configuration and state- Manage IRQ flow handler- IRQs allocation/free- Hook-up a PPI specific IRQchip to provide the relevant methodsPPI IRQ priority is chosen as the minimum allowed priority by thesystem design (after probing the number of priority bits implementedby the CPU interface).Co-developed-by: Sascha Bischoff Signed-off-by: Sascha Bischoff Co-developed-by: Timothy Hayes Signed-off-by: Timothy Hayes Signed-off-by: Lorenzo Pieralisi Reviewed-by: Marc Zyngier Cc: Will Deacon Cc: Thomas Gleixner Cc: Catalin Marinas Cc: Marc Zyngier Acked-by: Catalin Marinas Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-20-12e71f1b3528@kernel.orgSigned-off-by: Marc Zyngier List of files: /linux/drivers/irqchip/Makefile

df0f030ee7e444c55341f4210124115878284125 - irqchip/thead-c900-aclint-sswi: Generalize aclint-sswi driver and add MIPS P800 support

Thu, 12 Jun 2025 16:39:08 +0200

irqchip/thead-c900-aclint-sswi: Generalize aclint-sswi driver and add MIPS P800 supportRefactor the Thead specific implementation of the ACLINT-SSWI irqchip: - Rename the source file and related details to reflect the generic nature of the driver - Factor out the generic code that serves both Thead and MIPS variants. This generic part is compliant with the RISC-V draft spec [1] - Provide generic and Thead specific initialization functionsSigned-off-by: Vladimir Kondratiev Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20250612143911.3224046-5-vladimir.kondratiev@mobileye.comLink: https://github.com/riscvarchive/riscv-aclint [1] List of files: /linux/drivers/irqchip/Makefile

1902a59cf5f9d8b99ecf0cb8f122cb00ef7a3f13 - irqchip: Add EcoNet EN751221 INTC

Sun, 30 Mar 2025 19:02:59 +0200

irqchip: Add EcoNet EN751221 INTCAdd a driver for the interrupt controller in the EcoNet EN751221 MIPS SoC.Signed-off-by: Caleb James DeLisle Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20250330170306.2584136-4-cjd@cjdns.fr List of files: /linux/drivers/irqchip/Makefile

7d06015d936c861160803e020f68f413b5c3cd9d - Merge tag 'pci-v6.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Sat, 29 Mar 2025 03:36:53 +0100

Merge tag 'pci-v6.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pciPull pci updates from Bjorn Helgaas: "Enumeration: - Enable Configuration RRS SV, which makes device readiness visible, early instead of during child bus scanning (Bjorn Helgaas) - Log debug messages about reset methods being used (Bjorn Helgaas) - Avoid reset when it has been disabled via sysfs (Nishanth Aravamudan) - Add common pci-ep-bus.yaml schema for exporting several peripherals of a single PCI function via devicetree (Andrea della Porta) - Create DT nodes for PCI host bridges to enable loading device tree overlays to create platform devices for PCI devices that have several features that require multiple drivers (Herve Codina) Resource management: - Enlarge devres table[] to accommodate bridge windows, ROM, IOV BARs, etc., and validate BAR index in devres interfaces (Philipp Stanner) - Fix typo that repeatedly distributed resources to a bridge instead of iterating over subordinate bridges, which resulted in too little space to assign some BARs (Kai-Heng Feng) - Relax bridge window tail sizing for optional resources, e.g., IOV BARs, to avoid failures when removing and re-adding devices (Ilpo Järvinen) - Allow drivers to enable devices even if we haven't assigned optional IOV resources to them (Ilpo Järvinen) - Rework handling of optional resources (IOV BARs, ROMs) to reduce failures if we can't allocate them (Ilpo Järvinen) - Fix a NULL dereference in the SR-IOV VF creation error path (Shay Drory) - Fix s390 mmio_read/write syscalls, which didn't cause page faults in some cases, which broke vfio-pci lazy mapping on first access (Niklas Schnelle) - Add pdev->non_mappable_bars to replace CONFIG_VFIO_PCI_MMAP, which was disabled only for s390 (Niklas Schnelle) - Support mmap of PCI resources on s390 except for ISM devices (Niklas Schnelle) ASPM: - Delay pcie_link_state deallocation to avoid dangling pointers that cause invalid references during hot-unplug (Daniel Stodden) Power management: - Allow PCI bridges to go to D3Hot when suspending on all non-x86 systems (Manivannan Sadhasivam) Power control: - Create pwrctrl devices in pci_scan_device() to make it more symmetric with pci_pwrctrl_unregister() and make pwrctrl devices for PCI bridges possible (Manivannan Sadhasivam) - Unregister pwrctrl devices in pci_destroy_dev() so DOE, ASPM, etc. can still access devices after pci_stop_dev() (Manivannan Sadhasivam) - If there's a pwrctrl device for a PCI device, skip scanning it because the pwrctrl core will rescan the bus after the device is powered on (Manivannan Sadhasivam) - Add a pwrctrl driver for PCI slots based on voltage regulators described via devicetree (Manivannan Sadhasivam) Bandwidth control: - Add set_pcie_speed.sh to TEST_PROGS to fix issue when executing the set_pcie_cooling_state.sh test case (Yi Lai) - Avoid a NULL pointer dereference when we run out of bus numbers to assign for a bridge secondary bus (Lukas Wunner) Hotplug: - Drop superfluous pci_hotplug_slot_list, try_module_get() calls, and NULL pointer checks (Lukas Wunner) - Drop shpchp module init/exit logging, replace shpchp dbg() with ctrl_dbg(), and remove unused dbg(), err(), info(), warn() wrappers (Ilpo Järvinen) - Drop 'shpchp_debug' module parameter in favor of standard dynamic debugging (Ilpo Järvinen) - Drop unused cpcihp .get_power(), .set_power() function pointers (Guilherme Giacomo Simoes) - Disable hotplug interrupts in portdrv only when pciehp is not enabled to avoid issuing two hotplug commands too close together (Feng Tang) - Skip pciehp 'device replaced' check if the device has been removed to address a deadlock when resuming after a device was removed during system sleep (Lukas Wunner) - Don't enable pciehp hotplug interupt when resuming in poll mode (Ilpo Järvinen) Virtualization: - Fix bugs in 'pci=config_acs=' kernel command line parameter (Tushar Dave) DOE: - Expose supported DOE features via sysfs (Alistair Francis) - Allow DOE support to be enabled even if CXL isn't enabled (Alistair Francis) Endpoint framework: - Convert PCI device data so pci-epf-test works correctly on big-endian endpoint systems (Niklas Cassel) - Add BAR_RESIZABLE type to endpoint framework and add DWC core support for EPF drivers to set BAR_RESIZABLE type and size (Niklas Cassel) - Fix pci-epf-test double free that causes an oops if the host reboots and PERST# deassertion restarts endpoint BAR allocation (Christian Bruel) - Fix endpoint BAR testing so tests can skip disabled BARs instead of reporting them as failures (Niklas Cassel) - Widen endpoint test BAR size variable to accommodate BARs larger than INT_MAX (Niklas Cassel) - Remove unused tools 'pci' build target left over after moving tests to tools/testing/selftests/pci_endpoint (Jianfeng Liu) Altera PCIe controller driver: - Add DT binding and driver support for Agilex family (P-Tile, F-Tile, R-Tile) (Matthew Gerlach and D M, Sharath Kumar) AMD MDB PCIe controller driver: - Add DT binding and driver for AMD MDB (Multimedia DMA Bridge) (Thippeswamy Havalige) Broadcom STB PCIe controller driver: - Add BCM2712 MSI-X DT binding and interrupt controller drivers and add softdep on irq_bcm2712_mip driver to ensure that it is loaded first (Stanimir Varbanov) - Expand inbound window map to 64GB so it can accommodate BCM2712 (Stanimir Varbanov) - Add BCM2712 support and DT updates (Stanimir Varbanov) - Apply link speed restriction before bringing link up, not after (Jim Quinlan) - Update Max Link Speed in Link Capabilities via the internal writable register, not the read-only config register (Jim Quinlan) - Handle regulator_bulk_get() error to avoid panic when we call regulator_bulk_free() later (Jim Quinlan) - Disable regulators only when removing the bus immediately below a Root Port because we don't support regulators deeper in the hierarchy (Jim Quinlan) - Make const read-only arrays static (Colin Ian King) Cadence PCIe endpoint driver: - Correct MSG TLP generation so endpoints can generate INTx messages (Hans Zhang) Freescale i.MX6 PCIe controller driver: - Identify the second controller on i.MX8MQ based on devicetree 'linux,pci-domain' instead of DBI 'reg' address (Richard Zhu) - Remove imx_pcie_cpu_addr_fixup() since dwc core can now derive the ATU input address (using parent_bus_offset) from devicetree (Frank Li) Freescale Layerscape PCIe controller driver: - Drop deprecated 'num-ib-windows' and 'num-ob-windows' and unnecessary 'status' from example (Krzysztof Kozlowski) - Correct the syscon_regmap_lookup_by_phandle_args("fsl,pcie-scfg") arg_count to fix probe failure on LS1043A (Ioana Ciornei) HiSilicon STB PCIe controller driver: - Call phy_exit() to clean up if histb_pcie_probe() fails (Christophe JAILLET) Intel Gateway PCIe controller driver: - Remove intel_pcie_cpu_addr() since dwc core can now derive the ATU input address (using parent_bus_offset) from devicetree (Frank Li) Intel VMD host bridge driver: - Convert vmd_dev.cfg_lock from spinlock_t to raw_spinlock_t so pci_ops.read() will never sleep, even on PREEMPT_RT where spinlock_t becomes a sleepable lock, to avoid calling a sleeping function from invalid context (Ryo Takakura) MediaTek PCIe Gen3 controller driver: - Remove leftover mac_reset assert for Airoha EN7581 SoC (Lorenzo Bianconi) - Add EN7581 PBUS controller 'mediatek,pbus-csr' DT property and program host bridge memory aperture to this syscon node (Lorenzo Bianconi) Qualcomm PCIe controller driver: - Add qcom,pcie-ipq5332 binding (Varadarajan Narayanan) - Add qcom i.MX8QM and i.MX8QXP/DXP optional DMA interrupt (Alexander Stein) - Add optional dma-coherent DT property for Qualcomm SA8775P (Dmitry Baryshkov) - Make DT iommu property required for SA8775P and prohibited for SDX55 (Dmitry Baryshkov) - Add DT IOMMU and DMA-related properties for Qualcomm SM8450 (Dmitry Baryshkov) - Add endpoint DT properties for SAR2130P and enable endpoint mode in driver (Dmitry Baryshkov) - Describe endpoint BAR0 and BAR2 as 64-bit only and BAR1 and BAR3 as RESERVED (Manivannan Sadhasivam) Rockchip DesignWare PCIe controller driver: - Describe rk3568 and rk3588 BARs as Resizable, not Fixed (Niklas Cassel) Synopsys DesignWare PCIe controller driver: - Add debugfs-based Silicon Debug, Error Injection, Statistical Counter support for DWC (Shradha Todi) - Add debugfs property to expose LTSSM status of DWC PCIe link (Hans Zhang) - Add Rockchip support for DWC debugfs features (Niklas Cassel) - Add dw_pcie_parent_bus_offset() to look up the parent bus address of a specified 'reg' property and return the offset from the CPU physical address (Frank Li) - Use dw_pcie_parent_bus_offset() to derive CPU -> ATU addr offset via 'reg[config]' for host controllers and 'reg[addr_space]' for endpoint controllers (Frank Li) - Apply struct dw_pcie.parent_bus_offset in ATU users to remove use of .cpu_addr_fixup() when programming ATU (Frank Li) TI J721E PCIe driver: - Correct the 'link down' interrupt bit for J784S4 (Siddharth Vadapalli) TI Keystone PCIe controller driver: - Describe AM65x BARs 2 and 5 as Resizable (not Fixed) and reduce alignment requirement from 1MB to 64KB (Niklas Cassel) Xilinx Versal CPM PCIe controller driver: - Free IRQ domain in probe error path to avoid leaking it (Thippeswamy Havalige) - Add DT .compatible "xlnx,versal-cpm5nc-host" and driver support for Versal Net CPM5NC Root Port controller (Thippeswamy Havalige) - Add driver support for CPM5_HOST1 (Thippeswamy Havalige) Miscellaneous: - Convert fsl,mpc83xx-pcie binding to YAML (J. Neuschäfer) - Use for_each_available_child_of_node_scoped() to simplify apple, kirin, mediatek, mt7621, tegra drivers (Zhang Zekun)"* tag 'pci-v6.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (197 commits) PCI: layerscape: Fix arg_count to syscon_regmap_lookup_by_phandle_args() PCI: j721e: Fix the value of .linkdown_irq_regfield for J784S4 misc: pci_endpoint_test: Add support for PCITEST_IRQ_TYPE_AUTO PCI: endpoint: pci-epf-test: Expose supported IRQ types in CAPS register PCI: dw-rockchip: Endpoint mode cannot raise INTx interrupts PCI: endpoint: Add intx_capable to epc_features struct dt-bindings: PCI: Add common schema for devices accessible through PCI BARs PCI: intel-gw: Remove intel_pcie_cpu_addr() PCI: imx6: Remove imx_pcie_cpu_addr_fixup() PCI: dwc: Use parent_bus_offset to remove need for .cpu_addr_fixup() PCI: dwc: ep: Ensure proper iteration over outbound map windows PCI: dwc: ep: Use devicetree 'reg[addr_space]' to derive CPU -> ATU addr offset PCI: dwc: ep: Consolidate devicetree handling in dw_pcie_ep_get_resources() PCI: dwc: ep: Call epc_create() early in dw_pcie_ep_init() PCI: dwc: Use devicetree 'reg[config]' to derive CPU -> ATU addr offset PCI: dwc: Add dw_pcie_parent_bus_offset() checking and debug PCI: dwc: Add dw_pcie_parent_bus_offset() PCI/bwctrl: Fix NULL pointer dereference on bus number exhaustion PCI: xilinx-cpm: Add cpm_csr register mapping for CPM5_HOST1 variant PCI: brcmstb: Make const read-only arrays static ... List of files: /linux/drivers/irqchip/Makefile

c66741549424ca67453885f8b3a5aa81d9abfb34 - irqchip: Add the Sophgo SG2042 MSI interrupt controller

Wed, 26 Feb 2025 03:15:19 +0100

irqchip: Add the Sophgo SG2042 MSI interrupt controllerAdd driver for Sophgo SG2042 MSI interrupt controller.Signed-off-by: Chen Wang Signed-off-by: Thomas Gleixner Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/all/3104216ca90a5f532bafb676c1c5b1efb19e94d1.1740535748.git.unicorn_wang@outlook.com List of files: /linux/drivers/irqchip/Makefile