Changes in Makefile

c17ee635fd3a482b2ad2bf5e269755c2eae5f25e - Merge drm/drm-fixes into drm-misc-fixes

Mon, 23 Feb 2026 10:09:45 +0100

Merge drm/drm-fixes into drm-misc-fixes7.0-rc1 was just released, let's merge it to kick the new release cycle.Signed-off-by: Maxime Ripard List of files: /linux/drivers/cxl/core/Makefile

e812928be2ee1c2744adf20ed04e0ce1e2fc5c13 - Merge tag 'cxl-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl

Fri, 13 Feb 2026 01:33:05 +0100

Merge tag 'cxl-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlPull CXL updates from Dave Jiang: - Introduce cxl_memdev_attach and pave way for soft reserved handling, type2 accelerator enabling, and LSA 2.0 enabling. All these series require the endpoint driver to settle before continuing the memdev driver probe. - Address CXL port error protocol handling and reporting. The large patch series was split into three parts. The first two parts are included here with the final part coming later. The first part consists of a series of code refactoring to PCI AER sub-system that addresses CXL and also CXL RAS code to prepare for port error handling. The second part refactors the CXL code to move management of component registers to cxl_port objects to allow all CXL AER errors to be handled through the cxl_port hierarchy. - Provide AMD Zen5 platform address translation for CXL using ACPI PRMT. This includes a conventions document to explain why this is needed and how it's implemented. - Misc CXL patches of fixes, cleanups, and updates. Including CXL address translation for unaligned MOD3 regions.[ TLA service: CXL is "Compute Express Link" ]* tag 'cxl-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (59 commits) cxl: Disable HPA/SPA translation handlers for Normalized Addressing cxl/region: Factor out code into cxl_region_setup_poison() cxl/atl: Lock decoders that need address translation cxl: Enable AMD Zen5 address translation using ACPI PRMT cxl/acpi: Prepare use of EFI runtime services cxl: Introduce callback for HPA address ranges translation cxl/region: Use region data to get the root decoder cxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos() cxl/region: Separate region parameter setup and region construction cxl: Simplify cxl_root_ops allocation and handling cxl/region: Store HPA range in struct cxl_region cxl/region: Store root decoder in struct cxl_region cxl/region: Rename misleading variable name @hpa to @hpa_range Documentation/driver-api/cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement cxl, doc: Moving conventions in separate files cxl, doc: Remove isonum.txt inclusion cxl/port: Unify endpoint and switch port lookup cxl/port: Move endpoint component register management to cxl_port cxl/port: Map Port RAS registers cxl/port: Move dport RAS setup to dport add time ... List of files: /linux/drivers/cxl/core/Makefile

63fbf275fa9f18f7020fb8acf54fa107e51d0f23 - Merge branch 'for-7.0/cxl-prm-translation' into cxl-for-next

Wed, 04 Feb 2026 18:53:33 +0100

Merge branch 'for-7.0/cxl-prm-translation' into cxl-for-nextAdd support for normalized CXL address translation through ACPI PRM methodto support AMD Zen5 platforms. Including a conventions doc that explainshow the translation is implemented and for future implementations thatneed such setup to comply with the current implementation method.cxl: Disable HPA/SPA translation handlers for Normalized Addressingcxl/region: Factor out code into cxl_region_setup_poison()cxl/atl: Lock decoders that need address translationcxl: Enable AMD Zen5 address translation using ACPI PRMTcxl/acpi: Prepare use of EFI runtime servicescxl: Introduce callback for HPA address ranges translationcxl/region: Use region data to get the root decodercxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos()cxl/region: Separate region parameter setup and region constructioncxl: Simplify cxl_root_ops allocation and handlingcxl/region: Store HPA range in struct cxl_regioncxl/region: Store root decoder in struct cxl_regioncxl/region: Rename misleading variable name @hpa to @hpa_rangeDocumentation/driver-api/cxl: ACPI PRM Address Translation Support and AMD Zen5 enablementcxl, doc: Moving conventions in separate filescxl, doc: Remove isonum.txt inclusion List of files: /linux/drivers/cxl/core/Makefile

af74daf91652f15b82560bb93850d2ec8bbfa976 - cxl: Enable AMD Zen5 address translation using ACPI PRMT

Tue, 27 Jan 2026 19:12:31 +0100

cxl: Enable AMD Zen5 address translation using ACPI PRMTAdd AMD Zen5 support for address translation.Zen5 systems may be configured to use 'Normalized addresses'. Then,host physical addresses (HPA) are different from their system physicaladdresses (SPA). The endpoint has its own physical address space andan incoming HPA is already converted to the device's physical address(DPA). Thus it has interleaving disabled and CXL endpoints areprogrammed passthrough (DPA == HPA).Host Physical Addresses (HPAs) need to be translated from the endpointto its CXL host bridge, esp. to identify the endpoint's root decoderand region's address range. ACPI Platform Runtime Mechanism (PRM)provides a handler to translate the DPA to its SPA. This is documentedin: AMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh ACPI v6.5 Porting Guide, Publication # 58088 https://www.amd.com/en/search/documentation/hub.htmlWith Normalized Addressing this PRM handler must be used to translatean HPA of an endpoint to its SPA.Do the following to implement AMD Zen5 address translation:Introduce a new file core/atl.c to handle ACPI PRM specific addresstranslation code. Naming is loosely related to the kernel's AMDAddress Translation Library (CONFIG_AMD_ATL) but implementation doesnot depend on it, nor it is vendor specific. Use Kbuild and Kconfigoptions respectively to enable the code depending on architecture andplatform options.AMD Zen5 systems support the ACPI PRM CXL Address Translation firmwarecall (see ACPI v6.5 Porting Guide, Address Translation - CXL DPA toSystem Physical Address). Firmware enables the PRM handler if theplatform has address translation implemented. Check firmware andkernel support of ACPI PRM using the specific GUID. On success enableaddress translation by setting up the earlier introduced root portcallback, see function cxl_prm_setup_translation(). Setup is done incxl_setup_prm_address_translation(), it is the only function thatneeds to be exported. For low level PRM firmware calls, use the ACPIframework.Identify the region's interleaving ways by inspecting the addressranges. Also determine the interleaving granularity using the addresstranslation callback. Note that the position of the chunk from oneinterleaving block to the next may vary and thus cannot be consideredconstant. Address offsets larger than the interleaving block sizecannot be used to calculate the granularity. Thus, probe thegranularity using address translation for various HPAs in the sameinterleaving block.[ dj: Add atl.o build to cxl_test ]Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Tested-by: Gregory Price Signed-off-by: Robert Richter Link: https://patch.msgid.link/20260114164837.1076338-11-rrichter@amd.comSigned-off-by: Dave Jiang List of files: /linux/drivers/cxl/core/Makefile

914c743509d56067eeeb2b5e341a44a68ef8377d - Merge branch 'for-7.0/cxl-aer-prep' into cxl-for-next

Fri, 23 Jan 2026 00:59:43 +0100

Merge branch 'for-7.0/cxl-aer-prep' into cxl-for-nextPreparation for CXL port error protocol handling. First part containsall the changes centered around setting up the PCI side of errorhandling.cxl: Update RAS handler interfaces to also support CXL Portscxl/mem: Clarify @host for devm_cxl_add_nvdimm()PCI/AER: Update struct aer_err_info with kernel-doc formattingPCI/AER: Report CXL or PCIe bus type in AER trace loggingPCI/AER: Use guard() in cxl_rch_handle_error_iter()PCI/AER: Move CXL RCH error handling to aer_cxl_rch.cPCI/AER: Update is_internal_error() to be non-static is_aer_internal_error()PCI/AER: Export pci_aer_unmask_internal_errors()cxl/pci: Move CXL driver's RCH error handling into core/ras_rch.cPCI/AER: Replace PCIEAER_CXL symbol with CXL_RAScxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.cPCI: Replace cxl_error_is_native() with pcie_aer_is_native()cxl/pci: Remove unnecessary CXL RCH handling helper functionscxl/pci: Remove unnecessary CXL Endpoint handling helper functionsPCI: Introduce pcie_is_cxl()PCI: Update CXL DVSEC definitionsPCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h List of files: /linux/drivers/cxl/core/Makefile

0ff60f2ec3e4043a442e805f80f8a2445113ec8f - cxl/pci: Move CXL driver's RCH error handling into core/ras_rch.c

Wed, 14 Jan 2026 19:20:29 +0100

cxl/pci: Move CXL driver's RCH error handling into core/ras_rch.cRestricted CXL Host (RCH) protocol error handling uses a procedure distinctfrom the CXL Virtual Hierarchy (VH) handling. This is because of thedifferences in the RCH and VH topologies. Improve the maintainability andadd ability to enable/disable RCH handling.Move and combine the RCH handling code into a single block conditionallycompiled with the CONFIG_CXL_RCH_RAS kernel config.Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Link: https://patch.msgid.link/20260114182055.46029-9-terry.bowman@amd.comSigned-off-by: Dan Williams Signed-off-by: Dave Jiang List of files: /linux/drivers/cxl/core/Makefile

7ff8b1d60881c5f97b5ae426e14d2822917d3b69 - cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c

Wed, 14 Jan 2026 19:20:28 +0100

cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.cCreate new config CONFIG_CXL_RAS and put all CXL RAS items behind theconfig. The config will depend on CPER and PCIE AER to build. Move therelated VH RAS code from core/pci.c to core/ras.c.Restricted CXL host (RCH) RAS functions will be moved in a future patch.Cc: Robert Richter Reviewed-by: Joshua Hahn Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang Reviewed-by: Alison Schofield Co-developed-by: Terry Bowman Signed-off-by: Terry Bowman Reviewed-by: Dan Williams Link: https://patch.msgid.link/20260114182055.46029-8-terry.bowman@amd.comSigned-off-by: Dan Williams Signed-off-by: Dave Jiang List of files: /linux/drivers/cxl/core/Makefile

cb9f145f638d7afa633632a9290d6ad06caeb8ee - Merge remote-tracking branch 'drm/drm-next' into msm-next-robclark

Sat, 01 Nov 2025 13:47:30 +0100

Merge remote-tracking branch 'drm/drm-next' into msm-next-robclarkBack-merge drm-next to get caught up.Signed-off-by: Rob Clark List of files: /linux/drivers/cxl/core/Makefile

f088104d837a991c65e51fa30bb4196169b3244d - Merge drm/drm-next into drm-intel-gt-next

Tue, 16 Sep 2025 12:53:20 +0200

Merge drm/drm-next into drm-intel-gt-nextBackmerge in order to get the commit: 048832a3f400 ("drm/i915: Refactor shmem_pwrite() to use kiocb and write_iter")To drm-intel-gt-next as there are followup fixes to be applied.Signed-off-by: Joonas Lahtinen List of files: /linux/drivers/cxl/core/Makefile

a53d0cf7f1cb3182ad533ff5cacfa5fd29c419ad - Merge commit 'linus' into core/bugs, to resolve conflicts

Tue, 05 Aug 2025 11:15:34 +0200

Merge commit 'linus' into core/bugs, to resolve conflictsResolve conflicts with this commit that was developed in parallelduring the merge window: 8c8efa93db68 ("x86/bug: Add ARCH_WARN_ASM macro for BUG/WARN asm code sharing with Rust") Conflicts: arch/riscv/include/asm/bug.h arch/x86/include/asm/bug.hSigned-off-by: Ingo Molnar List of files: /linux/drivers/cxl/core/Makefile

8b87f67b4c87452e21721887fa8dec1f4c6b2b7c - Merge branch 'next' into for-linus

Wed, 08 Oct 2025 06:53:13 +0200

Merge branch 'next' into for-linusPrepare input updates for 6.18 merge window. List of files: /linux/drivers/cxl/core/Makefile

4b051897df2375414587a245ecb9bb1a4d26b3b8 - Merge tag 'v6.17-rc2' into HEAD

Thu, 21 Aug 2025 20:46:49 +0200

Merge tag 'v6.17-rc2' into HEADSync up with mainline to bring in changes to include/linux/sprintf.h List of files: /linux/drivers/cxl/core/Makefile

d325efac5938efa3c2a25df72a1bd1af16cd0ed8 - Merge branch 'for-6.18/core' into for-linus

Tue, 30 Sep 2025 16:31:10 +0200

Merge branch 'for-6.18/core' into for-linus- allow HID-BPF to rebind a driver to hid-multitouch (Benjamin Tissoires)- Change hid_driver to use a const char* for .name (Rahul Rameshbabu) List of files: /linux/drivers/cxl/core/Makefile

71b28769d708f20046fc6f853cf93fb88a8b6e11 - Merge remote-tracking branch 'origin' into for-6.18/intel-thc-hid

Fri, 19 Sep 2025 17:08:20 +0200

Merge remote-tracking branch 'origin' into for-6.18/intel-thc-hidNeeded as a basisi for followup support for quicki2c advanced BIOS features.Signed-off-by: Jiri Kosina List of files: /linux/drivers/cxl/core/Makefile

b4d90dbc4c1bc4bd3eb2d2989330af0eb95c98e8 - Merge drm/drm-next into drm-misc-next-fixes

Mon, 15 Sep 2025 10:23:28 +0200

Merge drm/drm-next into drm-misc-next-fixesBackmerging to drm-misc-next-fixes to get features and fixes fromv6.17-rc6.Signed-off-by: Thomas Zimmermann List of files: /linux/drivers/cxl/core/Makefile

702fdf3513b045f596f836d9a4b8672c76f11834 - Merge drm/drm-next into drm-intel-next

Wed, 10 Sep 2025 14:01:42 +0200

Merge drm/drm-next into drm-intel-nextCatching up with some display dependencies.Signed-off-by: Rodrigo Vivi List of files: /linux/drivers/cxl/core/Makefile

ca994e8922f25f7fed2075098f185cf198109eaa - Merge drm/drm-next into drm-xe-next

Tue, 12 Aug 2025 14:58:37 +0200

Merge drm/drm-next into drm-xe-nextBring v6.17-rc1 to propagate commits from other subsystems, particularlyPCI, which has some new functions needed for SR-IOV integration.Signed-off-by: Lucas De Marchi List of files: /linux/drivers/cxl/core/Makefile

08c51f5bddc81c8c97c1eb11861b0dc009e5ccd8 - Merge drm/drm-next into drm-misc-n

Mon, 11 Aug 2025 14:37:45 +0200

Merge drm/drm-next into drm-misc-nUpdating drm-misc-next to the state of v6.17-rc1. Begins a new releasecycle.Signed-off-by: Thomas Zimmermann List of files: /linux/drivers/cxl/core/Makefile

8d2b0853add1d7534dc0794e3c8e0b9e8c4ec640 - Merge drm/drm-fixes into drm-misc-fixes

Mon, 11 Aug 2025 16:49:06 +0200

Merge drm/drm-fixes into drm-misc-fixesUpdating drm-misc-fixes to the state of v6.17-rc1. Begins a new releasecycle.Signed-off-by: Thomas Zimmermann List of files: /linux/drivers/cxl/core/Makefile

ab93e0dd72c37d378dd936f031ffb83ff2bd87ce - Merge branch 'next' into for-linus

Wed, 06 Aug 2025 19:08:54 +0200

Merge branch 'next' into for-linusPrepare input updates for 6.17 merge window. List of files: /linux/drivers/cxl/core/Makefile