Changes in Makefile

502d45774af09f1c681c754c4b7cdfb5d7f72fd9 - Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Wed, 26 Aug 2026 20:14:30 +0200

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxPull clk updates from Stephen Boyd: "Mostly the usual clk driver updates and new SoC additions plus non-critical data fixes for things that weren't used yet. One thing that's new here in the core is SSC spread spectrum support (SSC) in the clk provider API. The idea is that DT authors will configure SSC for certain clks and they'll be configured at clk provider registration time or when a consumer device is probed, similar to how we handle assigned clk rates or parents. On the clk driver side we have Qualcomm adding almost half the diff because they add support for 4 different SoCs and then a long tail of other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more SoC support this time around. Luckily it's mostly clk data for these new SoCs because the actual clk_ops are already there. Beyond the new drivers we get all the little fixups for more compilation coverage or usage of more modern APIs. That all looks normal. Finally, I kinda buried the lede, I'm bringing on Brian and Jerome to help out with maintaining the clk subsystem. The current working model is already semi-distributed in that silicon vendors typically take care of their drivers and send me pull requests but I'm becoming a bottleneck for new drivers and core framework review because this has become a 100% volunteer effort on my part. Mike is stepping down after all these years (thanks Mike!) and that jump started the conversation around finding co-maintainers. Brian and Jerome have graciously offered to help me with the work load, meaning in the future they'll be sending pull requests and committing directly to the clk.git tree. They've both been around on the list for a while, I've met them both in person, and they've been making changes to the core clk framework along with helping review patches so I'm pretty confident this will work well. Core: - devm_clk_bulk_get_enable() consumer API - devm_clk_hw_register_composite_pdata() provider API - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs - Divider clk rounding improved (and tested) New Drivers: - Cix Sky1 audio subsystem (AUDSS) - UltraRISC DP1000 - MediaTek MT8173 MFG_TOP - Si549 - Aspeed AST2700 PECI - Airoha EN7523 PCIe - Rockchip RV1106 - Mobileye EyeQ7H - Qualcomm Maili GCC, TCSR, RPMh, and video clks - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks - Qualcomm Nord display and graphics clks - Qualcomm Glymur camera and EVA clks - Qualcomm Hawi video clks - Amlogic A9 AO and peripheral clks - Renesas R-Car X5H (R8A78000) CPG"* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (269 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: samsung: Don't include clk: at91: Read "reg" with helper clk: renesas: Add R-Car X5H CPG driver clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator ... List of files: /linux/drivers/clk/mediatek/Makefile

dd8eb789f18c4c600f28e61176a02bcf3b790117 - Merge branches 'clk-pile' and 'clk-microchip' into clk-next

Fri, 21 Aug 2026 01:51:47 +0200

Merge branches 'clk-pile' and 'clk-microchip' into clk-next* clk-pile: (111 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 ...* clk-microchip: clk: at91: Read "reg" with helper List of files: /linux/drivers/clk/mediatek/Makefile

df822f2e36cf2c2864d166d90cf002df4d8689e5 - Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile

Fri, 14 Aug 2026 02:42:25 +0200

Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pilePull clk patches from Brian Masney: - New clock controller drivers for the Cix Sky1 audio subsystem (AUDSS), UltraRISC DP1000, and MediaTek MT8173 MFG_TOP, along with their devicetree bindings. Si549 support was added to the existing si544 driver. - New clock and reset support for the Aspeed AST2700 PECI controller and Airoha EN7523 PCIe PERSTOUT reset lines. - The clk core gains devm_clk_bulk_get_enable() as the mandatory counterpart to the existing optional variant, and exports devm_clk_hw_register_composite_pdata() for modular drivers. - Tegra gets a proper EMC clock implementation for Tegra114, 48MHz pll_p_out1 support needed for UEFI on Surface2, and the Xilinx clocking-wizard gains PLL charge pump/lock parameter programming during dynamic reconfiguration. - Bug fixes for a NULL pointer dereference from uninitialized clk_init_data in the eswin driver, an IO remap leak in the MediaTek pllfh error path, inverted gate control for MT8135 devapc_ck, a missing OF node put in tegra124-emc on registration failure, a prepare reference leak in the palmas driver, unregistered PLLs on MT6735 probe failure, a missing kasprintf NULL check in pmc_atom, PCIe warm boot instability in the Airoha EN7523 driver, and a clocking-wizard clock difference detection bug. - Various cleanups across tegra, st, and mvebu providers to stop misusing the consumer clock API, along with other minor fixes and improvements.Signed-off-by: Brian Masney * tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux: (45 commits) clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 clk: aspeed: add AST2700 PECI clock dt-bindings: clock: ast2700: add PECI clock clk: mediatek: Add mt8173-mfgtop driver dt-bindings: clock: mediatek: Add mt8173 mfgtop clk: tegra: clean-up simple provider misuse of the consumer API clk: st: clean-up simple provider misuse of the consumer API clk: mvebu: clean-up simple provider misuse of the consumer API clk: remove conditional return with no effect clk: Add devm_clk_bulk_get_enable() clk: en7523: add support for dedicated PCIe PERSTOUT reset dt-bindings: clock: airoha: Add additional reset for PCIe PERSTOUT arm64: dts: cix: sky1: add audss cru reset: cix: add sky1 audss auxiliary reset driver ... List of files: /linux/drivers/clk/mediatek/Makefile

ebd0b73d2137c2277440da04124a0ce7011b2d1a - clk: mediatek: Add mt8173-mfgtop driver

Tue, 28 Jul 2026 11:18:00 +0200

clk: mediatek: Add mt8173-mfgtop driverThe MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOPin the datasheet, that contains clock gates, some power sequence signaldelays, and other unknown registers that get toggled when the GPU ispowered on.The clock gates are exposed as clocks provided by a clock controller,while the power sequencing bits are exposed as one singular power domain.Tested-by: Icenowy Zheng Reviewed-by: Brian Masney Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Chen-Yu Tsai Signed-off-by: Brian Masney List of files: /linux/drivers/clk/mediatek/Makefile

8edf8b09fc44990977b3fbcb708035b1740d0b7e - Merge drm/drm-next into drm-intel-gt-next

Tue, 12 May 2026 10:16:35 +0200

Merge drm/drm-next into drm-intel-gt-nextBackmerging to pull in commit 5401b9adebc9 ("i915: don't usea vma that didn't match the context VM") to revert it.Signed-off-by: Joonas Lahtinen List of files: /linux/drivers/clk/mediatek/Makefile

a4a508df2aa34f8650afde54ea804321c618f45f - Merge tag 'v6.18' into next

Sat, 13 Dec 2025 10:18:20 +0100

Merge tag 'v6.18' into nextSync up with the mainline to bring in the latest APIs. List of files: /linux/drivers/clk/mediatek/Makefile

7362b5b493102c6b71827c2da22117b475528f6d - Merge branch 'for-6.19/nintendo' into for-linus

Tue, 02 Dec 2025 14:46:11 +0100

Merge branch 'for-6.19/nintendo' into for-linus- switch to WQ_PERCPU workaueues (Marco Crivellari)- reduce potential initialization blocking time of hid-nintendo (Willy Huang) List of files: /linux/drivers/clk/mediatek/Makefile

cb9f145f638d7afa633632a9290d6ad06caeb8ee - Merge remote-tracking branch 'drm/drm-next' into msm-next-robclark

Sat, 01 Nov 2025 13:47:30 +0100

Merge remote-tracking branch 'drm/drm-next' into msm-next-robclarkBack-merge drm-next to get caught up.Signed-off-by: Rob Clark List of files: /linux/drivers/clk/mediatek/Makefile

82ee50252dc891e3f3b32d923bb4f656d300b772 - Merge drm/drm-next into drm-xe-next

Tue, 14 Oct 2025 11:31:49 +0200

Merge drm/drm-next into drm-xe-nextBackmerging to bring in 6.18-rc1.Signed-off-by: Thomas Hellström List of files: /linux/drivers/clk/mediatek/Makefile

2acee98fcc61052d63fab4539fcb6ee677555645 - Merge drm/drm-next into drm-intel-next

Tue, 14 Oct 2025 09:37:11 +0200

Merge drm/drm-next into drm-intel-nextSync to v6.18-rc1.Signed-off-by: Jani Nikula List of files: /linux/drivers/clk/mediatek/Makefile

9b966ae42235a88eaea714be09ff3d698535bdfe - Merge drm/drm-next into drm-misc-next

Mon, 13 Oct 2025 09:19:19 +0200

Merge drm/drm-next into drm-misc-nextUpdating drm-misc-next to the state of v6.18-rc1.Signed-off-by: Thomas Zimmermann List of files: /linux/drivers/clk/mediatek/Makefile

39e9d5f63075f4d54e3b59b8238478c32af92755 - Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf before 6.18-rc1

Sun, 12 Oct 2025 03:27:47 +0200

Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf before 6.18-rc1Cross-merge BPF and other fixes after downstream PR.No conflicts.Signed-off-by: Alexei Starovoitov List of files: /linux/drivers/clk/mediatek/Makefile

2ace52718376fdb56aca863da2eebe70d7e2ddb1 - Merge branch 'objtool/core'

Fri, 21 Nov 2025 11:21:20 +0100

Merge branch 'objtool/core'Bring in the UDB and objtool data annotations to avoid conflicts while further extending the bug exceptions.Signed-off-by: Peter Zijlstra List of files: /linux/drivers/clk/mediatek/Makefile

f39b6c468c52745dbca9a842d91c8373fda208ab - Merge tag 'v6.18-rc6' into for-linus

Tue, 18 Nov 2025 08:16:55 +0100

Merge tag 'v6.18-rc6' into for-linusSync up with the mainline to bring in definition ofINPUT_PROP_HAPTIC_TOUCHPAD. List of files: /linux/drivers/clk/mediatek/Makefile

4f38da1f027ea2c9f01bb71daa7a299c191b6940 - spi: Merge up v6.18-rc1

Mon, 13 Oct 2025 14:32:13 +0200

spi: Merge up v6.18-rc1Ensure my CI has a sensible baseline. List of files: /linux/drivers/clk/mediatek/Makefile

ec2e0fb07d789976c601bec19ecced7a501c3705 - Merge tag 'asoc-fix-v6.18-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus

Thu, 16 Oct 2025 20:14:24 +0200

Merge tag 'asoc-fix-v6.18-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linusASoC: Fixes for v6.18A moderately large collection of driver specific fixes, plus a few newquirks and device IDs. The NAU8821 changes are a little large but morein mechanical ways than in ways that are complex. List of files: /linux/drivers/clk/mediatek/Makefile

48a710760e10a4f36e11233a21860796ba204b1e - Merge drm/drm-fixes into drm-misc-fixes

Tue, 14 Oct 2025 10:59:58 +0200

Merge drm/drm-fixes into drm-misc-fixesUpdating drm-misc-fixes to the state of v6.18-rc1.Signed-off-by: Thomas Zimmermann List of files: /linux/drivers/clk/mediatek/Makefile

522ba450b56fff29f868b1552bdc2965f55de7ed - Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Tue, 07 Oct 2025 18:28:37 +0200

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxPull clk updates from Stephen Boyd: "There's a bunch of patches here across drivers/clk/ to migrate drivers to use struct clk_ops::determine_rate() instead of the round_rate() one so that we can remove the round_rate clk_op entirely. Brian has taken up that task which nobody else has wanted to do for close to a decade. Thanks Brian! This is all prerequisite work to get to the real task of improving the clk rate setting process. Once we have determine_rate() used everywhere, we'll be able to do things like chain the rate request structs in linked lists to order the rate setting operations or add more parameters without having to change every clk driver in existence. It's also nice to not have multiple ways to do something which just causes confusion for clk driver authors. Overall I'm glad this is getting done. Beyond this change we also have a tweak to the clk_lookup() function in the core framework to use hashing on the clk name instead of a clk tree walk with string comparisons. We _still_ rely on the clk name to be unique, because historically we've used globally unique strings to describe the clk tree topology. This tree walk becomes increasingly slow as more clks are added to the system. Searching from the roots for a duplicate is simple but pretty dumb and it wastes boot time so we're using a hash table as an improvement. Ideally we wouldn't rely on the strings to be unique at all, relegating them to simply debug information, but that is future work that will likely require some sort of Kconfig knob indicating strings aren't used for topology description. Outside of the core framework changes we have the usual new SoC support and fixes to clk drivers for things that were discovered once the clks were used by consumer drivers. Nothing in particular is jumping out at me in the "misc" pile, except maybe the Amlogic driver that has gone through a refactoring. That series got a fix from testing in -next though so it seems likely that things have been getting good test coverage for a couple weeks already"* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (299 commits) clk: microchip: core: remove duplicate roclk_determine_rate() reset: aspeed: register AST2700 reset auxiliary bus device dt-bindings: clock: ast2700: modify soc0/1 clock define clk: tegra: do not overallocate memory for bpmp clocks clk: ep93xx: Use int type to store negative error codes clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver clk: loongson2: Add clock definitions for Loongson-2K0300 SoC clk: loongson2: Avoid hardcoding firmware name of the reference clock clk: loongson2: Allow zero divisors for dividers clk: loongson2: Support scale clocks with an alternative mode clk: loongson2: Allow specifying clock flags for gate clock dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible clk: clocking-wizard: Fix output clock register offset for Versal platforms clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver() clk: mmp: pxa1908: Instantiate power driver through auxiliary bus clk: s2mps11: add support for S2MPG10 PMIC clock dt-bindings: clock: samsung,s2mps11: add s2mpg10 dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings clk: stm32: introduce clocks for STM32MP21 platform dt-bindings: stm32: add STM32MP21 clocks and reset bindings ... List of files: /linux/drivers/clk/mediatek/Makefile

8397c58ea73ebd1236820093b57ea4664f4d21b4 - Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next

Mon, 06 Oct 2025 20:00:22 +0200

Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next - Add Mediatek MT8196 clk drivers* clk-marvell: clk: mmp: pxa1908: Instantiate power driver through auxiliary bus* clk-xilinx: clk: clocking-wizard: Fix output clock register offset for Versal platforms clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()* clk-mediatek: (31 commits) clk: mediatek: Add MT8196 vencsys clock support clk: mediatek: Add MT8196 vdecsys clock support clk: mediatek: Add MT8196 ovl1 clock support clk: mediatek: Add MT8196 ovl0 clock support clk: mediatek: Add MT8196 disp-ao clock support clk: mediatek: Add MT8196 disp1 clock support clk: mediatek: Add MT8196 disp0 clock support clk: mediatek: Add MT8196 mfg clock support clk: mediatek: Add MT8196 mdpsys clock support clk: mediatek: Add MT8196 mcu clock support clk: mediatek: Add MT8196 I2C clock support clk: mediatek: Add MT8196 pextpsys clock support clk: mediatek: Add MT8196 ufssys clock support clk: mediatek: Add MT8196 peripheral clock support clk: mediatek: Add MT8196 vlpckgen clock support clk: mediatek: Add MT8196 topckgen2 clock support clk: mediatek: Add MT8196 topckgen clock support clk: mediatek: Add MT8196 apmixedsys clock support dt-bindings: clock: mediatek: Describe MT8196 clock controllers clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro ...* clk-loongson: clk: loongson2: Add clock definitions for Loongson-2K0300 SoC clk: loongson2: Avoid hardcoding firmware name of the reference clock clk: loongson2: Allow zero divisors for dividers clk: loongson2: Support scale clocks with an alternative mode clk: loongson2: Allow specifying clock flags for gate clock dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible List of files: /linux/drivers/clk/mediatek/Makefile

2f66f069999dda4a44c5586805d468b8ac93ac1a - clk: mediatek: Add MT8196 vencsys clock support

Mon, 15 Sep 2025 17:19:47 +0200

clk: mediatek: Add MT8196 vencsys clock supportAdd support for the MT8196 vencsys clock controller, which providesclock gate control for the video encoder.Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao Signed-off-by: Stephen Boyd List of files: /linux/drivers/clk/mediatek/Makefile