Changes in Makefile

67f8bc848ee31831336bd478e57d2f993551902e - Merge drm/drm-fixes into drm-misc-fixes

Tue, 01 Sep 2026 09:38:51 +0200

Merge drm/drm-fixes into drm-misc-fixesLet's start the 7.3 drm-misc-fixes cycle.Signed-off-by: Maxime Ripard List of files: /linux/drivers/clk/Makefile

b2128290c29902315e632ea59e0504d6bc9e9b42 - Merge remote-tracking branch 'drm/drm-next' into msm-next-backmerge

Sat, 18 Jul 2026 17:06:55 +0200

Merge remote-tracking branch 'drm/drm-next' into msm-next-backmergeBackmerge of drm-next, mainly to pick up dt bindings docs updates toavoid conflicts.Signed-off-by: Rob Clark List of files: /linux/drivers/clk/Makefile

502d45774af09f1c681c754c4b7cdfb5d7f72fd9 - Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Wed, 26 Aug 2026 20:14:30 +0200

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxPull clk updates from Stephen Boyd: "Mostly the usual clk driver updates and new SoC additions plus non-critical data fixes for things that weren't used yet. One thing that's new here in the core is SSC spread spectrum support (SSC) in the clk provider API. The idea is that DT authors will configure SSC for certain clks and they'll be configured at clk provider registration time or when a consumer device is probed, similar to how we handle assigned clk rates or parents. On the clk driver side we have Qualcomm adding almost half the diff because they add support for 4 different SoCs and then a long tail of other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more SoC support this time around. Luckily it's mostly clk data for these new SoCs because the actual clk_ops are already there. Beyond the new drivers we get all the little fixups for more compilation coverage or usage of more modern APIs. That all looks normal. Finally, I kinda buried the lede, I'm bringing on Brian and Jerome to help out with maintaining the clk subsystem. The current working model is already semi-distributed in that silicon vendors typically take care of their drivers and send me pull requests but I'm becoming a bottleneck for new drivers and core framework review because this has become a 100% volunteer effort on my part. Mike is stepping down after all these years (thanks Mike!) and that jump started the conversation around finding co-maintainers. Brian and Jerome have graciously offered to help me with the work load, meaning in the future they'll be sending pull requests and committing directly to the clk.git tree. They've both been around on the list for a while, I've met them both in person, and they've been making changes to the core clk framework along with helping review patches so I'm pretty confident this will work well. Core: - devm_clk_bulk_get_enable() consumer API - devm_clk_hw_register_composite_pdata() provider API - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs - Divider clk rounding improved (and tested) New Drivers: - Cix Sky1 audio subsystem (AUDSS) - UltraRISC DP1000 - MediaTek MT8173 MFG_TOP - Si549 - Aspeed AST2700 PECI - Airoha EN7523 PCIe - Rockchip RV1106 - Mobileye EyeQ7H - Qualcomm Maili GCC, TCSR, RPMh, and video clks - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks - Qualcomm Nord display and graphics clks - Qualcomm Glymur camera and EVA clks - Qualcomm Hawi video clks - Amlogic A9 AO and peripheral clks - Renesas R-Car X5H (R8A78000) CPG"* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (269 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: samsung: Don't include clk: at91: Read "reg" with helper clk: renesas: Add R-Car X5H CPG driver clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator ... List of files: /linux/drivers/clk/Makefile

dd8eb789f18c4c600f28e61176a02bcf3b790117 - Merge branches 'clk-pile' and 'clk-microchip' into clk-next

Fri, 21 Aug 2026 01:51:47 +0200

Merge branches 'clk-pile' and 'clk-microchip' into clk-next* clk-pile: (111 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 ...* clk-microchip: clk: at91: Read "reg" with helper List of files: /linux/drivers/clk/Makefile

a1476addb4631cc7d393adc057a20129b264520f - Merge branches 'clk-renesas', 'clk-thead', 'clk-mobileye', 'clk-amlogic' and 'clk-spacemit' into clk-next

Fri, 21 Aug 2026 01:51:21 +0200

Merge branches 'clk-renesas', 'clk-thead', 'clk-mobileye', 'clk-amlogic' and 'clk-spacemit' into clk-next* clk-renesas: clk: renesas: Add R-Car X5H CPG driver dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator clk: r9a08g045: Add clocks and resets for CAN-FD dt-bindings: clock: renesas,versaclock7: Update maintainer clk: renesas: r9a09g047: Add LVDS clocks and resets clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations clk: renesas: r9a08g046: Add USB2.0 clock and reset entries clk: renesas: r9a09g077: Add RTC clocks clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC and RTC clk: renesas: r9a08g046: Add clock and reset entries for GE3D clk: renesas: r9a08g046: Add clock and reset entries for SDHI clk: renesas: r9a09g047: Add audio clock and reset support dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family dt-bindings: clock: renesas,r9a09g077/87: Add PCLKRTC clock ID dt-bindings: clock: renesas,r9a09g077/87: Add LCDC_CLKD clock ID* clk-thead: clk: thead: allow COMPILE_TEST builds* clk-mobileye: clk: eyeq: Add EyeQ7H compatibles clk: eyeq: Drop PLL, dividers, and fixed factors structs clk: eyeq: Convert clocks declaration to eqc_clock clk: eyeq: Introduce a generic clock type clk: eyeq: Prefix the PLL registers with the PLL type clk: fixed-factor: Export __clk_hw_register_fixed_factor() clk: fixed-factor: Rework initialization with parent clocks reset: eyeq: Add EyeQ7H compatibles dt-bindings: soc: mobileye: Add EyeQ7H OLB* clk-amlogic: clk: amlogic: Add A9 peripherals clock controller driver dt-bindings: clock: Add Amlogic A9 peripherals clock controller clk: amlogic: Add A9 AO clock controller driver dt-bindings: clock: Add Amlogic A9 AO clock controller clk: meson: align gxbb_32k_clk_sel number of parents with actual count* clk-spacemit: clk: spacemit: k3: fix missing /2 factor in i2s sysclk dividers clk: spacemit: k3: fix i2s clock topology dt-bindings: soc: spacemit: k3: add i2s_sysclk, i2s_bclk_factor and i2s1_sysclk_src IDs clk: spacemit: k3: Add UFS refclk clock dt-bindings: soc: spacemit: k3: Add clock ID for UFS refclk clk: spacemit: k3: fix parent clock of UFS aclk List of files: /linux/drivers/clk/Makefile

df822f2e36cf2c2864d166d90cf002df4d8689e5 - Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile

Fri, 14 Aug 2026 02:42:25 +0200

Merge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux into clk-pilePull clk patches from Brian Masney: - New clock controller drivers for the Cix Sky1 audio subsystem (AUDSS), UltraRISC DP1000, and MediaTek MT8173 MFG_TOP, along with their devicetree bindings. Si549 support was added to the existing si544 driver. - New clock and reset support for the Aspeed AST2700 PECI controller and Airoha EN7523 PCIe PERSTOUT reset lines. - The clk core gains devm_clk_bulk_get_enable() as the mandatory counterpart to the existing optional variant, and exports devm_clk_hw_register_composite_pdata() for modular drivers. - Tegra gets a proper EMC clock implementation for Tegra114, 48MHz pll_p_out1 support needed for UEFI on Surface2, and the Xilinx clocking-wizard gains PLL charge pump/lock parameter programming during dynamic reconfiguration. - Bug fixes for a NULL pointer dereference from uninitialized clk_init_data in the eswin driver, an IO remap leak in the MediaTek pllfh error path, inverted gate control for MT8135 devapc_ck, a missing OF node put in tegra124-emc on registration failure, a prepare reference leak in the palmas driver, unregistered PLLs on MT6735 probe failure, a missing kasprintf NULL check in pmc_atom, PCIe warm boot instability in the Airoha EN7523 driver, and a clocking-wizard clock difference detection bug. - Various cleanups across tegra, st, and mvebu providers to stop misusing the consumer clock API, along with other minor fixes and improvements.Signed-off-by: Brian Masney * tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux: (45 commits) clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 clk: aspeed: add AST2700 PECI clock dt-bindings: clock: ast2700: add PECI clock clk: mediatek: Add mt8173-mfgtop driver dt-bindings: clock: mediatek: Add mt8173 mfgtop clk: tegra: clean-up simple provider misuse of the consumer API clk: st: clean-up simple provider misuse of the consumer API clk: mvebu: clean-up simple provider misuse of the consumer API clk: remove conditional return with no effect clk: Add devm_clk_bulk_get_enable() clk: en7523: add support for dedicated PCIe PERSTOUT reset dt-bindings: clock: airoha: Add additional reset for PCIe PERSTOUT arm64: dts: cix: sky1: add audss cru reset: cix: add sky1 audss auxiliary reset driver ... List of files: /linux/drivers/clk/Makefile

804b10deb0e8872716416b38af0e4e60a038f0fd - Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pile

Fri, 14 Aug 2026 02:17:13 +0200

Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pilePull clk patches picked up by Brian Masney:Here's various improvements and fixes for the clk subsystem that was posted priorto the opening of the last merge window.- Add spread spectrum clock (SSC) support to the clk framework, including a new assigned-clock-sscs devicetree property and clk_hw_set_spread_spectrum() API with KUnit tests (Peng Fan)- Add SCMI clock OEM extensions for the i.MX95 clock driver and introduce a common SCMI clock header (Peng Fan)- Add clock, reset, and devicetree bindings for the ESWIN EIC7700 HSP clock and reset generator (Xuyang Dong)- Add clk_determine_rate_noop() helper for clock drivers that can do any rate, and convert existing open-coded implementations across hisilicon, imx, qcom, renesas, rp1, samsung, scpi, sprd, mediatek phy, and mediatek pmdomain drivers (Brian Masney)- Add kernel-doc documentation for struct clk_core and the core clock flags, and wire up clk identifiers into the documentation build (Brian Masney)- Fix clk_divider_bestdiv() returning the minimum rate instead of the maximum rate for large rate requests, with KUnit tests (Lad Prabhakar)- Fix Nuvoton MA35D1 PLL frequency calculation including ignored div_u64 return values, incorrect PLL_CTL1_FRAC bit field width, and broken determine_rate logic (Joey Lu)- Support unique clock names for multi-socket Tegra platforms (Jon Hunter)- Allow COMPILE_TEST builds for HiSilicon clock drivers (Rosen Penev)- Various fixes and cleanups from Akari Tsuyukusa, Alexander A. Klimov, Brian Masney, David Carlier, David Laight, Min zhang, Myeonghun Pak, Pavel Löbl, Randy Dunlap, Rob Herring, Rosen Penev, Uwe Kleine-König, William Theesfeld, Xuyang Dong, and Yu-Chun LinSigned-off-by: Brian Masney [sboyd@kernel.org: Fix allmodconfig modpost failure in scmi]* tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux: (53 commits) pmdomain: mediatek: mtk-mfg: use clk_determine_rate_noop() pmdomain: mediatek: airoha: use clk_determine_rate_noop() phy: mediatek: phy-mtk-hdmi-mt2701: use clk_determine_rate_noop() clk: sprd: use clk_determine_rate_noop() clk: scpi: use clk_determine_rate_noop() clk: samsung: acpm: use clk_determine_rate_noop() clk: rp1: use clk_determine_rate_noop() clk: renesas: rzg2l-cpg: use clk_determine_rate_noop() clk: qcom: smd-rpm: use clk_determine_rate_noop() clk: qcom: rpmh: use clk_determine_rate_noop() clk: qcom: rpm: use clk_determine_rate_noop() clk: imx: scu: use clk_determine_rate_noop() clk: hisilicon: hi3660-stub: use clk_determine_rate_noop() clk: add clk_determine_rate_noop() clk: imx: scu: drop redundant init.ops variable assignment clk: test: convert constants to use HZ_PER_MHZ docs: clk: include some identifiers to keep documentation up to date clk: add kernel docs for struct clk_core clk: add kernel docs for the core flags clk: hisilicon: allow COMPILE_TEST builds ... List of files: /linux/drivers/clk/Makefile

aa7ebeb0358cf639caeb60dcbbed9a2510ebbd45 - Merge tag 'thead-clk-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into clk-thead

Wed, 12 Aug 2026 06:13:23 +0200

Merge tag 'thead-clk-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into clk-theadPull one T-HEAD clk driver update from Drew Fustini:There is just one change for this cycle. It allows COMPILE_TEST toselect the th1520 clk driver without having CONFIG_ARCH_THEAD enabled.* tag 'thead-clk-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux: clk: thead: allow COMPILE_TEST builds List of files: /linux/drivers/clk/Makefile

3730fe6032d9a5e1140994693feefe0efa927acb - clk: cix: add sky1 audss clock controller

Thu, 23 Jul 2026 11:08:06 +0200

clk: cix: add sky1 audss clock controllerAdd a platform driver for the Cix Sky1 AUDSS CRU. The driver mapsthe CRU registers and registers mux, divider and gate clocks forDSP, SRAM, HDA, DMAC, I2S, mailbox, watchdog and timer blocks.Four SoC-level audio reference clocks are enabled as inputs to theinternal clock tree. The driver releases the AUDSS NOC reset, enablesruntime PM and instantiates the auxiliary reset device.Signed-off-by: Joakim Zhang Reviewed-by: Brian Masney Signed-off-by: Brian Masney List of files: /linux/drivers/clk/Makefile

3948a36be42b67f43f1d3f113dad4c8b347efb9b - clk: ultrarisc: Add DP1000 clock driver

Mon, 20 Jul 2026 02:38:06 +0200

clk: ultrarisc: Add DP1000 clock driverAdd a clock driver for the UltraRISC DP1000 SoC.The clock tree is driven by a SYSPLL and provides fixed-factor clocks forthe subsystem and PCIe, divider-based root clocks for GMAC and the UART,I2C, and SPI blocks, and per-instance gate clocks for UART0-3, I2C0-3,and SPI0-1.Signed-off-by: Jia Wang Reviewed-by: Brian Masney Signed-off-by: Brian Masney List of files: /linux/drivers/clk/Makefile

745dfe874d5b9136090af69eba3f61170ceaa168 - clk: stm32: allow STM32MP COMPILE_TEST builds

Sun, 19 Jul 2026 23:50:40 +0200

clk: stm32: allow STM32MP COMPILE_TEST buildsCOMMON_CLK_STM32MP already allows COMPILE_TEST, but the parent clockMakefile only descends into drivers/clk/stm32 for ARCH_STM32. Use theSTM32MP clock symbol for that directory gate instead.Tested with:make LLVM=1 ARCH=loongarch drivers/clk/stm32/Assisted-by: Codex:GPT-5.5Signed-off-by: Rosen Penev Reviewed-by: Brian Masney Signed-off-by: Brian Masney List of files: /linux/drivers/clk/Makefile

b2ee00d0bf4cca5dd02702fc339d2b523191966f - clk: thead: allow COMPILE_TEST builds

Tue, 07 Jul 2026 02:56:19 +0200

clk: thead: allow COMPILE_TEST buildsFollow the pattern of many other directories in this Makefile (sunxi-ng,tenstorrent, ti, etc.) by using obj-y. This allows COMPILE_TEST toselect the driver without having CONFIG_ARCH_THEAD enabledTested with:make LLVM=1 ARCH=loongarch drivers/clk/thead/Assisted-by: Codex:GPT-5.5Acked-by: Drew Fustini Reviewed-by: Brian Masney Signed-off-by: Rosen Penev Signed-off-by: Drew Fustini List of files: /linux/drivers/clk/Makefile

48d5f26f1d5c14e2edf21c843e815a105badd1ba - clk: hisilicon: allow COMPILE_TEST builds

Sat, 09 May 2026 07:11:10 +0200

clk: hisilicon: allow COMPILE_TEST buildsThe HiSilicon clock symbols already depend on ARCH_HISI or COMPILE_TEST,but the parent clock Makefile only descends into the hisilicon directorywhen ARCH_HISI is enabled.Add a hidden family gate selected by the HiSilicon clock and reset symbols,default it for ARCH_HISI, and use it for the parent Makefile descent. Thiskeeps existing platform builds unchanged while allowing compile-testcoverage.Tested with:make LLVM=1 ARCH=loongarch drivers/clk/hisilicon/Assisted-by: Codex:GPT-5.5Signed-off-by: Rosen Penev Reviewed-by: Brian Masney Signed-off-by: Brian Masney List of files: /linux/drivers/clk/Makefile

50ca555d6ae8205374e406b411ae0e8e9447568d - clk: divider: Add KUnit tests for clk_divider_bestdiv() ULONG_MAX handling

Tue, 02 Jun 2026 22:02:42 +0200

clk: divider: Add KUnit tests for clk_divider_bestdiv() ULONG_MAX handlingAdd KUnit tests to verify the behaviour of clk_divider_bestdiv() whenclk_round_rate() is called with ULONG_MAX, which is the canonical wayto probe the maximum rate a clock can produce.Two test cases are introduced:- clk_divider_bestdiv_ulong_max_returns_max_rate: registers a 1 GHz fixed-rate parent driving a table-based divider whose smallest entry is div=2 (entries: 2, 4, 8). Calls clk_hw_round_rate(div_hw, ULONG_MAX) and checks the result.- clk_divider_bestdiv_mux_ulong_max_returns_max_rate: places a two-input mux (4 GHz and 2 GHz fixed-rate parents, CLK_SET_RATE_PARENT) ahead of the same table-based divider to verify correct parent selection under ULONG_MAX.Both tests use an explicit clk_div_table with a minimum divider of 2 sothat the pre-loop maxdiv clamping in clk_divider_bestdiv(): maxdiv = min(ULONG_MAX / rate, maxdiv);clamps maxdiv to 1, causing _next_div() to return 2 on the firstiteration and skip the loop body entirely. This makes bestdiv fall backto the maximum divider, returning the minimum rate rather than themaximum.The expected values intentionally reflect the buggy output: - test 1: PARENT_RATE_1GHZ / 8 (minimum rate, not maximum) - test 2: 0 (invalid, loop never populated bestdiv)These will be corrected to PARENT_RATE_1GHZ / 2 and PARENT_RATE_4GHZ / 2respectively once the fix to clk_divider_bestdiv() is applied.Signed-off-by: Lad Prabhakar Reviewed-by: Brian Masney Signed-off-by: Brian Masney List of files: /linux/drivers/clk/Makefile

77369b1e6a37134f4c7bf9c175c7c4ec36c3ee11 - clk: scmi: Add i.MX95 OEM extension support for SCMI clock driver

Fri, 12 Jun 2026 10:46:28 +0200

clk: scmi: Add i.MX95 OEM extension support for SCMI clock driver - Introduce 'clk-scmi-oem.c' to support vendor-specific OEM extensions for the SCMI clock driver, allows clean integration of vendor-specific features without impacting the core SCMI clock driver logic. - Extend 'clk-scmi.h' with 'scmi_clk_oem' structure and related declarations. - Initialize OEM extensions via 'scmi_clk_oem_init()'. - Support querying OEM-specific features and setting spread spectrum. - Pass 'scmi_device' to 'scmi_clk_ops_select()' for OEM data access.Reviewed-by: Sebin Francis Reviewed-by: Cristian Marussi Signed-off-by: Peng Fan Signed-off-by: Brian Masney List of files: /linux/drivers/clk/Makefile

7d98de6ffdab5bf65854f2464be362f33a606238 - clk: Add KUnit tests for assigned-clock-sscs

Fri, 12 Jun 2026 10:46:26 +0200

clk: Add KUnit tests for assigned-clock-sscsAdd KUnit test coverage for the assigned-clock-sscs DT property thatconfigures spread spectrum on clocks before they are used.Extend the existing test infrastructure to support spread spectrum:- Add struct clk_spread_spectrum field to clk_dummy_context and a clk_dummy_set_spread_spectrum callback- Wire set_spread_spectrum into all dummy clock ops- Extend clk_assigned_rates_register_clk and test parameter struct to propagate initial SSCS valuesAdd a new separate test suite clk_assigned_sscs with three categories: 1. clk_assigned_sscs_assigns_one — verifies that a single assigned-clock-sscs entry correctly configures spread spectrum on one clock, testing both provider and consumer paths 2. clk_assigned_sscs_assigns_multiple — verifies that multiple assigned-clock-sscs entries configure spread spectrum on two clocks, testing both provider and consumer paths 3. clk_assigned_sscs_skips — verifies that malformed DT properties are correctly skipped without error: missing assigned-clocks, zero-valued SSCS, and null phandles, tested for both provider and consumer scenariosNew DT overlays are added for all test scenarios: - kunit_clk_assigned_sscs_one{,consumer} — single valid entry - kunit_clk_assigned_sscs_multiple{,consumer} — two valid entries - kunit_clk_assigned_sscs_without{,consumer} — missing assigned-clocks - kunit_clk_assigned_sscs_zero{,consumer} — all-zero SSCS values - kunit_clk_assigned_sscs_null{,consumer} — null phandleCo-developed-by: Brian Masney Signed-off-by: Peng Fan Signed-off-by: Brian Masney List of files: /linux/drivers/clk/Makefile

637315cb400eed1dbe721954fea437a61a2d65b2 - Merge tag 'kvm-riscv-7.3-1' of https://github.com/kvm-riscv/linux into HEAD

Tue, 18 Aug 2026 13:07:31 +0200

Merge tag 'kvm-riscv-7.3-1' of https://github.com/kvm-riscv/linux into HEADKVM/riscv changes for 7.3- Svadu/Zicfiss/Zicfilp FWFT support for Guest- Use try_cmpxchg for IMSIC MRIF RMW- More arch-specific tracepoints in KVM RISC-V- Eager Page Splitting for KVM RISC-V- Optimize hfence request handling for SMP Guests- Improve dirty log clearing by skipping zero bits in mask- Guard HFENCE range loops against overflow- CPU PM notifiers in KVM RISC-V for non-retentive idle states- Fix kernel-mode vector context save/restore for Guest List of files: /linux/drivers/clk/Makefile

efe86f088f48f18c27b648e5724048947f3b7fb4 - Merge drm/drm-next into drm-xe-next

Tue, 14 Jul 2026 15:40:31 +0200

Merge drm/drm-next into drm-xe-nextSync some i915/display changesSigned-off-by: Rodrigo Vivi List of files: /linux/drivers/clk/Makefile

6d177908bad5992e17669030db41caab88041d5e - Merge drm/drm-next into drm-intel-next

Tue, 30 Jun 2026 14:55:43 +0200

Merge drm/drm-next into drm-intel-nextSync with v7.2-rc1.Signed-off-by: Jani Nikula List of files: /linux/drivers/clk/Makefile

827b9aabd3ea3e96d5e48abed9f44dbd1e550d4e - Merge drm/drm-next into drm-misc-next

Tue, 30 Jun 2026 10:16:00 +0200

Merge drm/drm-next into drm-misc-nextBackmerging to get drm-misc-next to v7.2-rc1.Signed-off-by: Thomas Zimmermann List of files: /linux/drivers/clk/Makefile