Changes in Makefile

db810874e581db749c8c6ed9820a97fe63ea6e42 - Merge branches 'clk-ti', 'clk-samsung', 'clk-rockchip' and 'clk-spacemit' into clk-next

Thu, 25 Jun 2026 16:55:38 +0200

Merge branches 'clk-ti', 'clk-samsung', 'clk-rockchip' and 'clk-spacemit' into clk-next* clk-ti: clk: keystone: sci-clk: fix application of sizeof to pointer clk: keystone: don't cache clock rate* clk-samsung: clk: samsung: exynos990: Fix PERIC0/1 USI clock types clk: samsung: exynos850: mark APM I3C clocks as critical* clk-rockchip: clk: rockchip: allow COMPILE_TEST builds clk: rockchip: rk3588: add GATE_GRF clocks for I2S MCLK output to IO soc: rockchip: rk3588: add SYS_GRF SOC_CON6 register offset clk: rockchip: add helper to register auxiliary GRFs clk: rockchip: allow grf_type_sys lookup in aux_grf_table dt-bindings: clock: rockchip,rk3588-cru: add I2S MCLK output to IO clock IDs* clk-spacemit: clk: spacemit: k3: Add PCIe DBI clock dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs clk: spacemit: k3: Fix PCIe clock register offset clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock List of files: /linux/drivers/clk/Makefile

a7b7c7c6c01679efef0fd2f2ca1c5114f303e4f5 - clk: canaan: Add clock driver for Canaan K230

Sat, 25 Apr 2026 11:29:32 +0200

clk: canaan: Add clock driver for Canaan K230This patch provides basic support for the K230 clock, which coversall clocks in K230 SoC.The clock tree of the K230 SoC consists of a 24MHZ external crystaloscillator, PLLs and an external pulse input for timerX, and theirderived clocks.Co-developed-by: Troy Mitchell Signed-off-by: Troy Mitchell Signed-off-by: Xukai Wang Signed-off-by: Conor Dooley List of files: /linux/drivers/clk/Makefile

7edfb7fb58ee058298e18fde76a6077ef17d19d8 - clk: rockchip: allow COMPILE_TEST builds

Sat, 09 May 2026 02:36:02 +0200

clk: rockchip: allow COMPILE_TEST buildsCOMMON_CLK_ROCKCHIP already gates the Rockchip clock objects inside theRockchip clock Makefile. Allow selecting it for COMPILE_TEST and use itfor the parent Makefile descent instead of ARCH_ROCKCHIP.The per-SoC Rockchip clock symbols already have COMPILE_TEST dependencies,so this exposes the existing build coverage to other architectures withoutselecting the Rockchip platform.Tested with:make LLVM=1 ARCH=loongarch drivers/clk/rockchip/Assisted-by: Codex:GPT-5.5Signed-off-by: Rosen Penev Reviewed-by: Brian Masney Link: https://patch.msgid.link/20260509003602.956186-1-rosenp@gmail.comSigned-off-by: Heiko Stuebner List of files: /linux/drivers/clk/Makefile

6b701fde9b31f085f39fc2a371cb33212fab6f68 - Merge branches 'clk-samsung', 'clk-qcom', 'clk-round', 'clk-sai' and 'clk-cleanup' into clk-next

Thu, 16 Apr 2026 19:12:43 +0200

Merge branches 'clk-samsung', 'clk-qcom', 'clk-round', 'clk-sai' and 'clk-cleanup' into clk-next* clk-samsung: clk: samsung: exynos850: Add APM-to-AP mailbox clock dt-bindings: clock: exynos850: Add APM_AP MAILBOX clock clk: samsung: Use %pe format to simplify clk: samsung: pll: Fix possible truncation in a9fraco recalc rate clk: samsung: exynosautov920: add block G3D clock support dt-bindings: clock: exynosautov920: add G3D clock definitions clk: samsung: gs101: harmonise symbol names (clock arrays) clk: samsung: artpec-9: Add initial clock support for ARTPEC-9 SoC clk: samsung: Add clock PLL support for ARTPEC-9 SoC dt-bindings: clock: Add ARTPEC-9 clock controller* clk-qcom: (67 commits) clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC clk: qcom: rpmh: Add support for Nord rpmh clocks clk: qcom: Add TCSR clock driver for Nord SoC dt-bindings: clock: qcom: Add Nord Global Clock Controller dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON clk: qcom: Constify list of critical CBCR registers clk: qcom: Constify qcom_cc_driver_data clk: qcom: videocc-glymur: Constify qcom_cc_desc clk: qcom: Add a driver for SM8750 GPU clocks dt-bindings: clock: qcom: Add SM8750 GPU clocks clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074 clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018 clk: qcom: gdsc: Fix error path on registration of multiple pm subdomains dt-bindings: clock: qcom: Add missing power-domains property clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock clk: qcom: dispcc-sc7180: Add missing MDSS resets ...* clk-round: clk: divider: remove divider_round_rate() and divider_round_rate_parent() clk: divider: remove divider_ro_round_rate_parent() clk: remove round_rate() clk ops clk: composite: convert from round_rate() to determine_rate() clk: test: remove references to clk_ops.round_rate* clk-sai: clk: fsl-sai: Add MCLK generation support clk: fsl-sai: Extract clock setup into fsl_sai_clk_register() dt-bindings: clock: fsl-sai: Document clock-cells = <1> support clk: fsl-sai: Add i.MX8M support with 8 byte register offset clk: fsl-sai: Sort the headers dt-bindings: clock: fsl-sai: Document i.MX8M support* clk-cleanup: clk: visconti: pll: initialize clk_init_data to zero clk: xgene: Fix mapping leak in xgene_pllclk_init() clk: Simplify clk_is_match() clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoC clk: mvebu: armada-37xx-periph: fix __iomem casts in structure init clk: qoriq: avoid format string warning List of files: /linux/drivers/clk/Makefile

522a83abc36eb374d532a3db326ee1d3aab1d367 - Merge branches 'clk-tenstorrent', 'clk-rockchip', 'clk-imx' and 'clk-allwinner' into clk-next

Thu, 16 Apr 2026 19:12:33 +0200

Merge branches 'clk-tenstorrent', 'clk-rockchip', 'clk-imx' and 'clk-allwinner' into clk-next* clk-tenstorrent: clk: tenstorrent: Add Atlantis clock controller driver reset: tenstorrent: Add reset controller for Atlantis dt-bindings: clk: tenstorrent: Add tenstorrent,atlantis-prcm-rcpu* clk-rockchip: clk: rockchip: rk3568: Add PCIe pipe clock gates clk: rockchip: Add clock controller for the RV1103B dt-bindings: clock: rockchip: Add RV1103B CRU support* clk-imx: clk: imx8mq: Correct the CSI PHY sels clk: vf610: Add support for the Ethernet switch clocks dt-bindings: clock: vf610: Add definitions for MTIP L2 switch dt-bindings: clock: vf610: Drop VF610_CLK_END define clk: vf610: Move VF610_CLK_END define to clk-vf610 driver clk: imx: imx8-acm: fix flags for acm clocks clk: imx: imx6q: Fix device node reference leak in of_assigned_ldb_sels() clk: imx: imx6q: Fix device node reference leak in pll6_bypassed() clk: imx: fracn-gppll: Add 477.4MHz support clk: imx: fracn-gppll: Add 333.333333 MHz support clk: imx: pll14xx: Use unsigned format specifier dt-bindings: clock: imx6q[ul]-clock: add optional clock enet[1]_ref_pad* clk-allwinner: clk: sunxi-ng: sun55i-a523-r: Add missing r-spi module clock List of files: /linux/drivers/clk/Makefile

cd44f127c1d42833a32ba0a0965255ee6184f8c1 - clk: eswin: Add eic7700 clock driver

Tue, 03 Mar 2026 09:07:12 +0100

clk: eswin: Add eic7700 clock driverAdd clock drivers for the EIC7700 SoC. The clock controller on the ESWINEIC7700 provides various clocks to different IP blocks within the SoC.Signed-off-by: Yifeng Huang Tested-by: Marcel Ziswiler # ebc77Reviewed-by: Brian Masney Signed-off-by: Xuyang Dong Tested-by: Bo Gan # hfp550Signed-off-by: Stephen Boyd List of files: /linux/drivers/clk/Makefile

5d6c477687aeb158df9ec95580270146778f6af1 - clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoC

Tue, 24 Feb 2026 12:17:18 +0100

clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoCAs noticed in the discussion [1] the Baikal SoC and platformsare not going to be finalized, hence remove stale code.Reviewed-by: Brian Masney Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1]Signed-off-by: Andy Shevchenko Acked-by: Rob Herring (Arm) Reviewed-by: Randy Dunlap Signed-off-by: Stephen Boyd List of files: /linux/drivers/clk/Makefile

23c8ebc952849b3ba47d04d0ec95daf5cc136061 - clk: tenstorrent: Add Atlantis clock controller driver

Fri, 06 Mar 2026 18:12:19 +0100

clk: tenstorrent: Add Atlantis clock controller driverAdd driver for clock controller in Tenstorrent Atlantis SoC. This versionof the driver covers clocks from RCPU subsystem.5 types of clocks generated by this controller: PLLs (PLLswith bypass functionality and an additional Gate clk at output), SharedGates (Multiple Gate clks that share an enable bit), standard Muxes,Dividers and Gates. All clocks are implemented using custom clk ops anduse the regmap interface associated with the syscon. All clocks are derivedfrom a 24 Mhz oscillator.The reset controller is also setup as an auxiliary device of the clockcontroller.Signed-off-by: Anirudh Srinivasan Reviewed-by: Brian Masney Reviewed-by: Drew Fustini Signed-off-by: Drew Fustini List of files: /linux/drivers/clk/Makefile

03b3faa12c25140d00f9dca4ed44a6184600d9d8 - clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory.

Wed, 24 Dec 2025 06:37:22 +0100

clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory.Prepare for long-term maintenance and future additions by introducing adedicated drivers/clk/aspeed/ subdirectory for ASPEED clock drivers.Move the existing ASPEED clock drivers into the newdrivers/clk/aspeed/ subdirectory.No functional change, file move only.Signed-off-by: Ryan Chen Reviewed-by: Brian Masney Signed-off-by: Stephen Boyd List of files: /linux/drivers/clk/Makefile

b276445e98fe28609688fb85b89a81b803910e63 - clk: keystone: fix compile testing

Thu, 27 Nov 2025 14:53:25 +0100

clk: keystone: fix compile testingSome keystone clock drivers can be selected when COMPILE_TEST isenabled but since commit b745c0794e2f ("clk: keystone: Add sci-clkdriver support") they are never actually built.Enable compile testing by allowing the build system to process thekeystone drivers.Fixes: b745c0794e2f ("clk: keystone: Add sci-clk driver support")Signed-off-by: Johan Hovold Signed-off-by: Stephen Boyd List of files: /linux/drivers/clk/Makefile

5ba9f520f41a33c99fd5d1eb81b5650ed3517b88 - clk: Add clock driver for the RISC-V RPMI clock service group

Mon, 18 Aug 2025 06:09:06 +0200

clk: Add clock driver for the RISC-V RPMI clock service groupThe RPMI specification defines a clock service group which can beaccessed via SBI MPXY extension or dedicated S-mode RPMI transport.Add mailbox client based clock driver for the RISC-V RPMI clockservice group.Reviewed-by: Stephen Boyd Reviewed-by: Andy Shevchenko Co-developed-by: Anup Patel Signed-off-by: Anup Patel Signed-off-by: Rahul Pathak Link: https://lore.kernel.org/r/20250818040920.272664-11-apatel@ventanamicro.com[pjw@kernel.org: converted rpmi_clkrate_u64 macro to a function; replaced bare constant with a macro]Signed-off-by: Paul Walmsley List of files: /linux/drivers/clk/Makefile

2d945dde7fa3f17f46349360a9f97614de9f47da - Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Thu, 31 Jul 2025 22:36:27 +0200

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxPull clk updates from Stephen Boyd: "This is the usual collection of primarily clk driver updates. The big part of the diff is all the new Qualcomm clk drivers added for a few SoCs they're working on. The other two vendors with significant work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks to existing drivers and supports some new SoCs while Amlogic is starting a significant refactoring to simplify their code. The core framework gained a pair of helpers to get the 'struct device' or 'struct device_node' associated with a 'struct clk_hw'. Some associated KUnit tests were added for these simple helpers as well. Beyond that core change there are lots of little fixes throughout the clk drivers for the stuff we see every day, wrong clk driver data that affects tree topology or supported frequencies, etc. They're not found until the clks are actually used by some consumer device driver. New Drivers: - Global, display, gpu, video, camera, tcsr, and rpmh clock controller for the Qualcomm Milos SoC - Camera, display, GPU, and video clock controllers for Qualcomm QCS615 - Video clock controller driver for Qualcomm SM6350 - Camera clock controller driver for Qualcomm SC8180X - I3C clocks and resets on Renesas RZ/G3E - Expanded Serial Peripheral Interface (xSPI) clocks and resets on Renesas RZ/V2H(P) and RZ/V2N - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P) - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H - Ethernet clocks and resets on Renesas RZ/G3E - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas RZ/V2N Updates: - Support atomic PWMs in the PWM clk driver - clk_hw_get_dev() and clk_hw_get_of_node() helpers - Replace round_rate() with determine_rate() in various clk drivers - Convert clk DT bindings to DT schema format for DT validation - Various clk driver cleanups and refactorings from static analysis tools and possibly real humans - A lot of little fixes here and there to things like clk tree topology, missing frequencies, flagging clks as critical, etc"* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (216 commits) clk: clocking-wizard: Fix the round rate handling for versal clk: Fix typos clk: spacemit: ccu_pll: fix error return value in recalc_rate callback clk: tegra: periph: Make tegra_clk_periph_ops static clk: tegra: periph: Fix error handling and resolve unsigned compare warning clk: imx: scu: convert from round_rate() to determine_rate() clk: imx: pllv4: convert from round_rate() to determine_rate() clk: imx: pllv3: convert from round_rate() to determine_rate() clk: imx: pllv2: convert from round_rate() to determine_rate() clk: imx: pll14xx: convert from round_rate() to determine_rate() clk: imx: pfd: convert from round_rate() to determine_rate() clk: imx: frac-pll: convert from round_rate() to determine_rate() clk: imx: fracn-gppll: convert from round_rate() to determine_rate() clk: imx: fixup-div: convert from round_rate() to determine_rate() clk: imx: cpu: convert from round_rate() to determine_rate() clk: imx: busy: convert from round_rate() to determine_rate() clk: imx: composite-93: remove round_rate() in favor of determine_rate() clk: imx: composite-8m: remove round_rate() in favor of determine_rate() clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls clk: imx: Remove redundant pm_runtime_mark_last_busy() calls ... List of files: /linux/drivers/clk/Makefile

ac32d031f508e46c19ab38d6ba8b53fc28df9945 - clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests

Thu, 17 Apr 2025 15:44:23 +0200

clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() testsAdd kunit test suites clk_hw_get_dev() and clk_hw_get_of_node()for clocks registered with clk_hw_register() and of_clk_hw_register()Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20250417-clk-hw-get-helpers-v1-2-7743e509612a@baylibre.comReviewed-by: Brian Masney [sboyd@kernel.org: Drop genparams, rename tests, drop inits,combine suites, add test for non-DT platform device]Signed-off-by: Stephen Boyd List of files: /linux/drivers/clk/Makefile

6486341721a2cd1cbc9c08a9bc90235c0b42f25b - clk: rp1: Add support for clocks provided by RP1

Thu, 29 May 2025 15:50:41 +0200

clk: rp1: Add support for clocks provided by RP1RaspberryPi RP1 is an MFD providing, among other peripherals, severalclock generators and PLLs that drives the sub-peripherals.Add the driver to support the clock providers.Signed-off-by: Andrea della Porta Tested-by: Randy Dunlap # build-testedLink: https://lore.kernel.org/r/20250529135052.28398-4-andrea.porta@suse.comSigned-off-by: Florian Fainelli List of files: /linux/drivers/clk/Makefile

1b72c59db0add8e47fa116b21f78ed0b09a264f3 - clk: spacemit: Add clock support for SpacemiT K1 SoC

Wed, 16 Apr 2025 15:54:03 +0200

clk: spacemit: Add clock support for SpacemiT K1 SoCThe clock tree of K1 SoC contains three main types of clock hardware(PLL/DDN/MIX) and has control registers split into several multifunctiondevices: APBS (PLLs), MPMU, APBC and APMU.All register operations are done through regmap to ensure atomicitybetween concurrent operations of clock driver and reset,power-domain driver that will be introduced in the future.Signed-off-by: Haylen Chu Reviewed-by: Alex Elder Reviewed-by: Inochi Amaoto Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20250416135406.16284-4-heylenay@4d2.orgSigned-off-by: Yixun Lan List of files: /linux/drivers/clk/Makefile

b2f8240153fb762e23dfc3dd1b042c299b3e265b - Merge branches 'clk-mobileye', 'clk-twl', 'clk-nuvoton', 'clk-renesas' and 'clk-bindings' into clk-next

Tue, 19 Nov 2024 05:00:28 +0100

Merge branches 'clk-mobileye', 'clk-twl', 'clk-nuvoton', 'clk-renesas' and 'clk-bindings' into clk-next - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver - TWL6030 clk driver - Nuvoton Arbel BMC NPCM8XX SoC clks - Convert more clk bindings to YAML* clk-mobileye: clk: eyeq: add EyeQ6H west fixed factor clocks clk: eyeq: add EyeQ6H central fixed factor clocks clk: eyeq: add EyeQ5 fixed factor clocks clk: eyeq: add fixed factor clocks infrastructure clk: eyeq: require clock index with phandle in all cases clk: fixed-factor: add clk_hw_register_fixed_factor_index() function dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles clk: eyeq: add driver clk: divider: Introduce CLK_DIVIDER_EVEN_INTEGERS flag dt-bindings: clock: add Mobileye EyeQ6L/EyeQ6H clock indexes Revert "dt-bindings: clock: mobileye,eyeq5-clk: add bindings"* clk-twl: clk: twl: add TWL6030 support clk: twl: remove is_prepared* clk-nuvoton: clk: npcm8xx: add clock controller reset: npcm: register npcm8xx clock auxiliary bus device dt-bindings: reset: npcm: add clock properties* clk-renesas: clk: renesas: vbattb: Add VBATTB clock driver clk: Add devm_clk_hw_register_gate_parent_hw() clk: renesas: rzg2l: Fix FOUTPOSTDIV clk dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB clk: renesas: r9a08g045: Add power domain for RTC clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safe clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local ones clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup() dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks clk: renesas: r9a09g057: Add clock and reset entries for ICU clk: renesas: r9a09g057: Add CA55 core clocks clk: renesas: Remove duplicate and trailing empty lines* clk-bindings: dt-bindings: clock: actions,owl-cmu: convert to YAML dt-bindings: clock: ti: Convert mux.txt to json-schema dt-bindings: clock: ti: Convert divider.txt to json-schema dt-bindings: clock: ti: Convert interface.txt to json-schema dt-bindings: clock: convert rockchip,rk3328-cru.txt to YAML List of files: /linux/drivers/clk/Makefile

25d904946a0baf08b16204d95dc3624096d99c38 - clk: eyeq: add driver

Wed, 23 Oct 2024 12:58:40 +0200

clk: eyeq: add driverAdd Mobileye EyeQ5, EyeQ6L and EyeQ6H clock controller driver. It isboth a platform driver and a hook onto of_clk_init() used for clocksrequired early (GIC timer, UARTs).For some compatible, it is both at the same time. eqc_early_init()initialises early PLLs and exposes its own clock provider. It marksother clocks as deferred. eqc_probe() adds all remaining clocks usinganother clock provider.It exposes read-only PLLs derived from the main crystal on board.It also exposes another type of clocks: divider clocks.They always have even divisors and have one PLL as parent.This driver also bears the responsability for optional reset and pinctrlauxiliary devices. The match data attached to the devicetree nodecompatible indicate if such devices should be created. They all getpassed a pointer to the start of the OLB region.Signed-off-by: Théo Lebrun Link: https://lore.kernel.org/r/20241023-mbly-clk-v6-1-ca83e43daf93@bootlin.comSigned-off-by: Stephen Boyd List of files: /linux/drivers/clk/Makefile

e0b255df027e9745ec4c21dd08e333e46c03556c - clk: npcm8xx: add clock controller

Thu, 12 Sep 2024 21:10:38 +0200

clk: npcm8xx: add clock controllerAdd auxiliary driver to support Nuvoton Arbel BMC NPCM8XX contains anintegrated clock controller which generates and supplies clocks to allmodules within the BMC.The NPCM8xx clock controller is created using the auxiliary deviceframework and set up in the npcm reset driver since the NPCM8xx clock isusing the same register region.Signed-off-by: Tomer Maimon Tested-by: Benjamin Fair Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20240912191038.981105-4-tmaimon77@gmail.comSigned-off-by: Stephen Boyd List of files: /linux/drivers/clk/Makefile

e978201bc530b5566dff5c531dc17a20e0158803 - clk: test: Add KUnit tests for clock-assigned-rates{-u64} DT properties

Thu, 22 Aug 2024 02:24:30 +0200

clk: test: Add KUnit tests for clock-assigned-rates{-u64} DT propertiesAdd unit tests for the two types of assigned rate properties. Testdifferent combinations of assigned clocks and make sure that ratesaren't assigned when the DT properties are malformed or are zero.Cc: Peng Fan Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20240822002433.1163814-4-sboyd@kernel.org List of files: /linux/drivers/clk/Makefile

075dbe9f6e3c21596c5245826a4ee1f1c1676eb8 - Merge tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Thu, 26 Sep 2024 21:00:25 +0200

Merge tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socPull SoC update from Arnd Bergmann: "Convert ep93xx to devicetree This concludes a long journey towards replacing the old board files with devictree description on the Cirrus Logic EP93xx platform. Nikita Shubin has been working on this for a long time, for details see the last post on https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/"* tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits) dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config net: cirrus: use u8 for addr to calm down sparse dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0 dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe() pinctrl: ep93xx: Fix raster pins typo spi: ep93xx: update kerneldoc comments for ep93xx_spi clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate() clk: ep93xx: add module license dmaengine: cirrus: remove platform code ASoC: cirrus: edb93xx: Delete driver ARM: ep93xx: soc: drop defines ARM: ep93xx: delete all boardfiles ata: pata_ep93xx: remove legacy pinctrl use pwm: ep93xx: drop legacy pinctrl ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms ARM: dts: ep93xx: Add EDB9302 DT ARM: dts: ep93xx: add ts7250 board ARM: dts: add Cirrus EP93XX SoC .dtsi ... List of files: /linux/drivers/clk/Makefile