en Copyright 2015 Java http://kernelsources.org:8080/source/history/linux/arch/arm64/boot/dts/aspeed/Makefile#e77bb5dc57593a4698aaacd57a776728cf552e73 arm64: dts: aspeed: Add initial AST27xx SoC device treeAdd initial device tree support for the ASPEED AST27xx family, the8th-generation Baseboard Management Controller (BMC) SoCs.AST27xx SOC Family - https://www.aspeedtech.com/server_ast2700/ - https://www.aspeedtech.com/server_ast2720/ - https://www.aspeedtech.com/server_ast2750/The AST27xx features a dual-SoC architecture consisting of two dies,referred to as SoC0 and SoC1 - interconnected through an internalproprietary bus. Both SoCs share the same address decoding scheme,while each maintains independent clock and reset domains.- SoC0 (CPU die): contains a quad-core Cortex-A35 cluster and two Cortex-M4 cores, along with high-speed peripherals.- SoC1 (I/O die): includes the BootMCU (responsible for system boot) and its own clock/reset domains low-speed peripherals.The device tree describes the SoC0 and SoC1 domains and their peripherallayouts.Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>Link: https://lore.kernel.org/r/20260609-upstream_ast2700-v9-3-f631752f0cb1@aspeedtech.comSigned-off-by: Arnd Bergmann <arnd@arndb.de> List of files: /linux/arch/arm64/boot/dts/aspeed/Makefile Tue, 09 Jun 2026 04:47:20 +0200 Ryan Chen <ryan_chen@aspeedtech.com>