/* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright 2008 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ #pragma ident "%Z%%M% %I% %E% SMI" #pragma dictionary "SUN4U" #define AGENT_ID_MASK 0x1f #define AGENT_ID_SHIFT 24 #define HB_FIT 1000 #define HBUS_FIT 1000 #define PCI_BUS_FIT 500 #define PCI_DEV_FIT 1000 #define CPU_FIT 500 #define PCI_HB_DEV_PATH hostbridge/pcibus/pcidev[32]/pcifn[0] fru hostbridge; asru hostbridge; event fault.io.xmits@hostbridge, FITrate=HB_FIT, FRU=hostbridge, ASRU=hostbridge; event error.io.xmits.saf.dstat@hostbridge; event error.io.xmits.saf.to@hostbridge; event error.io.xmits.saf.bus@hostbridge; event error.io.xmits.ecc.thresh@hostbridge; event error.io.pci.device-ta@hostbridge/pcibus/pcidev/pcifn; event ereport.io.xmits.saf.ape@hostbridge{within(5s)}; event ereport.io.xmits.saf.to@hostbridge{within(5s)}; event ereport.io.xmits.saf.bus@hostbridge{within(5s)}; event ereport.io.xmits.saf.bca@hostbridge{within(5s)}; event ereport.io.xmits.saf.bcb@hostbridge{within(5s)}; event ereport.io.xmits.saf.ciq-to@hostbridge{within(5s)}; event ereport.io.xmits.saf.lpq-to@hostbridge{within(5s)}; event ereport.io.xmits.saf.sfpq-to@hostbridge{within(5s)}; event ereport.io.xmits.ecc.pce@hostbridge{within(5s)}; event ereport.io.xmits.ecc.pue@hostbridge{within(5s)}; event ereport.io.xmits.ecc.s-pce@hostbridge{within(5s)}; event ereport.io.xmits.ecc.s-pue@hostbridge{within(5s)}; event ereport.io.xmits.saf.para@hostbridge{within(5s)}; event ereport.io.xmits.saf.parb@hostbridge{within(5s)}; event ereport.io.xmits.saf.pars@hostbridge{within(5s)}; event ereport.io.xmits.saf.plla@hostbridge{within(5s)}; event ereport.io.xmits.saf.pllb@hostbridge{within(5s)}; event ereport.io.xmits.saf.plls@hostbridge{within(5s)}; event ereport.io.xmits.ecc.thresh@hostbridge{within(5s)}; event ereport.io.xmits.saf.dstat@hostbridge{within(5s)}; event ereport.io.xmits.pbmx.stdst@PCI_HB_DEV_PATH{within(5s)}; event ereport.io.xmits.pbmx.cndst@PCI_HB_DEV_PATH{within(5s)}; event ereport.io.xmits.pbmx.tato@PCI_HB_DEV_PATH{within(5s)}; event ereport.io.xmits.pbmx.stmmu@PCI_HB_DEV_PATH{within(5s)}; event ereport.io.xmits.pbmx.cnmmu@PCI_HB_DEV_PATH{within(5s)}; /* * A faulty Xmits hostbridge may cause: * * - para: a parity error on the internal memories of PCI block A. * - parb: a parity error on the internal memories of PCI block B. * - pars: a parity error on the internal memories of the Safari block. * - plla: a PLL lock error on the PCIA Leaf PLL. * - pllb: a PLL lock error on the PCIB Leaf PLL. * - plls: a PLL lock error on the Safari block PLL. * - stdst a streaming DMA split completion encounters a DSTAT error * - cndst a consistant DMA split completion encounters a DSTAT error * - bca: bad safari command from PCI block A. * - bcb: bad safari command from PCI block B. * - ciq-to: coherent input queue timeout. * - lpq-to: local PIO queue timeout. * - sfpq-to: safari foreign PIO queue timeout. * - ape: address parity error. * - pue: PIO uncorrectable error, bad reader. * - s-pue: secondary PIO UE, bad reader. * - ecc: multiple PIO CEs. * - to: safari bus timeout. * - bus: safari bus error. * - dstat: errant dstat on incoming data. * * The to, bus and dstat errors can cause a target abort to be sent onto the * pci bus in response to a dma request. We represent this using a device-ta * error to propagate into the generic pci.esc rules. */ prop fault.io.xmits@hostbridge (0)-> ereport.io.xmits.saf.para@hostbridge, ereport.io.xmits.saf.parb@hostbridge, ereport.io.xmits.saf.pars@hostbridge, ereport.io.xmits.saf.plla@hostbridge, ereport.io.xmits.saf.pllb@hostbridge, ereport.io.xmits.saf.plls@hostbridge, ereport.io.xmits.saf.bca@hostbridge, ereport.io.xmits.saf.bcb@hostbridge, ereport.io.xmits.saf.ciq-to@hostbridge, ereport.io.xmits.saf.lpq-to@hostbridge, ereport.io.xmits.saf.sfpq-to@hostbridge, ereport.io.xmits.saf.ape@hostbridge, ereport.io.xmits.ecc.pue@hostbridge, ereport.io.xmits.ecc.s-pue@hostbridge, ereport.io.xmits.pbmx.stdst@PCI_HB_DEV_PATH, ereport.io.xmits.pbmx.cndst@PCI_HB_DEV_PATH, error.io.xmits.ecc.thresh@hostbridge, error.io.xmits.saf.to@hostbridge, error.io.xmits.saf.bus@hostbridge, error.io.xmits.saf.dstat@hostbridge; prop error.io.xmits.ecc.thresh@hostbridge (2)-> ereport.io.xmits.ecc.thresh@hostbridge, ereport.io.xmits.ecc.pce@hostbridge; prop error.io.xmits.saf.to@hostbridge (2)-> ereport.io.xmits.saf.to@hostbridge, error.io.pci.device-ta@PCI_HB_DEV_PATH; prop error.io.xmits.saf.bus@hostbridge (2)-> ereport.io.xmits.saf.bus@hostbridge, error.io.pci.device-ta@PCI_HB_DEV_PATH; prop error.io.xmits.saf.dstat@hostbridge (1)-> ereport.io.xmits.saf.dstat@hostbridge; prop error.io.xmits.saf.dstat@hostbridge (0)-> error.io.pci.device-ta@PCI_HB_DEV_PATH; engine serd.io.xmits.ecc@hostbridge, N=3, T=1day, method=persistent, trip=ereport.io.xmits.ecc.thresh@hostbridge; event upset.io.xmits@hostbridge, engine=serd.io.xmits.ecc@hostbridge; /* * An upset xmits may cause: * * - pce: PIO correctable error. */ prop upset.io.xmits@hostbridge (0)-> ereport.io.xmits.ecc.pce@hostbridge; fru cpu; event fault.io.datapath@cpu, FITrate=CPU_FIT, FRU=cpu, retire=0; event error.io.cpu.ecc.thresh@cpu; event ereport.io.xmits.saf.ssm-dis@hostbridge{within(5s)}; /* * A faulty CPU may cause: * * - to: safari bus timeout. * - bus: safari bus error. * - dstat: incorrect dstat sent to hostbridge. * - ssm-dis: ssm command sent to hostbridge when not enabled. * - ape: safari address parity error. * - pue: PIO uncorrectable error. * - ecc: multiple PIO CEs. */ prop fault.io.datapath@cpu (0)-> error.io.xmits.saf.to@hostbridge, error.io.xmits.saf.bus@hostbridge, error.io.xmits.saf.dstat@hostbridge, ereport.io.xmits.saf.ssm-dis@hostbridge, ereport.io.xmits.saf.ape@hostbridge; prop fault.io.datapath@cpu[cpuid] (0)-> ereport.io.xmits.ecc.pue@hostbridge {((payloadprop("ecc-afsr") >> AGENT_ID_SHIFT) & AGENT_ID_MASK) == cpuid}; prop fault.io.datapath@cpu (0)-> error.io.cpu.ecc.thresh@cpu; prop error.io.cpu.ecc.thresh@cpu (1)-> ereport.io.xmits.ecc.thresh@hostbridge<>; prop error.io.cpu.ecc.thresh@cpu[cpuid] (1)-> ereport.io.xmits.ecc.pce@hostbridge<> {((payloadprop("ecc-afsr") >> AGENT_ID_SHIFT) & AGENT_ID_MASK) == cpuid}; event fault.io.hbus@hostbridge, FITrate=HBUS_FIT, FRU=hostbridge, ASRU=hostbridge; /* * A faulty host bus may cause: * * - ape: address parity error. * - pue: PIO uncorrectable error. * - s-pue: secondary PIO UE. * - ecc: multiple PIO CEs. */ prop fault.io.hbus@hostbridge (0)-> ereport.io.xmits.saf.ape@hostbridge, ereport.io.xmits.ecc.pue@hostbridge, ereport.io.xmits.ecc.s-pue@hostbridge, error.io.xmits.ecc.thresh@hostbridge; /* * A defective PCI driver may cause: * * - um: safari unmapped address error. * - mmu: a iommu translation error. */ event error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn; event error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn; event ereport.io.xmits.mmu@hostbridge/pcibus/pcidev/pcifn{within(5s)}; event ereport.io.xmits.saf.um@hostbridge{within(5s)}; event ereport.io.pci.rserr@hostbridge/pcibus/pcidev/pcifn{within(5s)}; prop error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn (0)-> ereport.io.xmits.saf.um@hostbridge; prop error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn (0)-> ereport.io.xmits.mmu@PCI_HB_DEV_PATH; prop error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn (0)-> ereport.io.xmits.saf.um@hostbridge; prop error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn (0)-> ereport.io.xmits.mmu@PCI_HB_DEV_PATH; event defect.io.pci.driver@hostbridge; /* * A defective PCI nexus driver may cause: * * - stmmu: A streaming DMA split completion transaction * encounters an MMU error. * - cnmmu: A consistant DMA split completion transaction * encounters an MMU error. */ prop defect.io.pci.driver@hostbridge (0)-> ereport.io.xmits.pbmx.stmmu@PCI_HB_DEV_PATH, ereport.io.xmits.pbmx.cnmmu@PCI_HB_DEV_PATH; fru pcibus; asru pcibus; event fault.io.pci.bus@hostbridge/pcibus, FITrate=PCI_BUS_FIT, FRU=pcibus, ASRU=pcibus; event ereport.io.xmits.bu@hostbridge/pcibus/pcidev/pcifn{within(5s)}; event ereport.io.xmits.s-bu@hostbridge/pcibus/pcidev/pcifn{within(5s)}; /* * A faulty PCI bus may cause: * * - bu: PCI bus unusable error. * - s-bu: secondary PCI bus unusable error. * - tato: DMA split completion target timeout error */ prop fault.io.pci.bus@hostbridge/pcibus (0)-> ereport.io.xmits.bu@PCI_HB_DEV_PATH, ereport.io.xmits.s-bu@PCI_HB_DEV_PATH, ereport.io.xmits.pbmx.tato@PCI_HB_DEV_PATH; fru pcibus/pcidev; asru pcibus/pcidev/pcifn; event fault.io.pci.device-interr@hostbridge/pcibus/pcidev/pcifn, FITrate=PCI_DEV_FIT, FRU=pcibus/pcidev, ASRU=pcibus/pcidev/pcifn; event fault.io.pci.device-interr@pcibus/pcidev/pcifn, FITrate=PCI_DEV_FIT, FRU=pcibus/pcidev, ASRU=pcibus/pcidev/pcifn; event error.io.xmits.pbm.rl@hostbridge/pcibus/pcidev/pcifn; event error.io.xmits.pbm.rl@pcibus/pcidev/pcifn; event error.io.xmits.pbm.rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn; event error.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn; event error.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn; event error.io.xmits.pbm.tto@hostbridge/pcibus/pcidev/pcifn; event error.io.xmits.pbm.target-tto@hostbridge/pcibus/pcidev/pcifn; event error.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn; event error.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn; event error.xmits.cpu.berr@cpu; event error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn; event error.io.pci.perr-pw-u@hostbridge/pcibus/pcidev/pcifn; event error.io.pci.perr-dw-u@hostbridge/pcibus/pcidev/pcifn; event error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn; event error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn; event error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn; event error.io.pci.retry-to-d@hostbridge/pcibus/pcidev/pcifn; event ereport.io.xmits.sbh@hostbridge/pcibus/pcidev/pcifn{within(5s)}; event ereport.io.xmits.pbm.rl@hostbridge/pcibus/pcidev/pcifn{within(5s)}; event ereport.io.xmits.pbm.tto@hostbridge/pcibus/pcidev/pcifn{within(5s)}; event ereport.io.xmits.pbm.s-rl@hostbridge/pcibus/pcidev/pcifn{within(5s)}; event ereport.io.xmits.pbm.s-tto@hostbridge/pcibus/pcidev/pcifn{within(5s)}; event ereport.io.xmits.pbm.s-ma@hostbridge/pcibus/pcidev/pcifn{within(5s)}; event ereport.io.xmits.pbm.s-rta@hostbridge/pcibus/pcidev/pcifn{within(5s)}; event ereport.io.xmits.pbm.s-mdpe@hostbridge/pcibus/pcidev/pcifn{within(5s)}; event ereport.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn{within(5s)}; event ereport.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn{within(5s)}; event ereport.io.pci.sserr@hostbridge/pcibus/pcidev/pcifn{within(5s)}; event ereport.cpu.ultraSPARC-III.berr@cpu{within(5s)}; event ereport.cpu.ultraSPARC-IIIplus.berr@cpu{within(5s)}; event ereport.cpu.ultraSPARC-IV.berr@cpu{within(5s)}; event ereport.cpu.ultraSPARC-IVplus.berr@cpu{within(5s)}; /* * A faulty PCI device may cause: * * - sbh: a streaming byte hole error. * - rl: it to exceed the number retriesfor a transaction. * - tto: it to not assert trdy# within the alloted timeout. * * For rl and tto, there may be a target- ereport on a child device. For rl, * there may also be an associated dto - the retry-to-d error propagates into * the pci.esc rules to handle this. */ prop fault.io.pci.device-interr@hostbridge/pcibus/pcidev/pcifn (0)-> ereport.io.xmits.sbh@PCI_HB_DEV_PATH; prop fault.io.pci.device-interr@pcibus/pcidev[fromdev]/pcifn (0)-> error.io.xmits.pbm.rl@pcibus/pcidev/pcifn { fromdev == todev && fromdev != 32 }, error.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn { fromdev == todev && fromdev != 32 }; prop error.io.xmits.pbm.rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn (1)-> error.io.xmits.pbm.rl@pcibus/pcidev/pcifn; prop error.io.xmits.pbm.rl@hostbridge/pcibus/pcidev/pcifn (1)-> ereport.io.xmits.pbm.rl@PCI_HB_DEV_PATH, ereport.io.xmits.pbm.s-rl@PCI_HB_DEV_PATH; prop error.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn (1)-> error.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn/pcibus<>/pcidev<>/pcifn<>; prop error.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn (0)-> ereport.io.xmits.pbm.target-rl@pcibus/pcidev/pcifn; prop error.io.xmits.pbm.rl@hostbridge/pcibus/pcidev/pcifn (0)-> error.io.pci.retry-to-d@hostbridge/pcibus/pcidev/pcifn; prop error.io.xmits.pbm.rl@hostbridge/pcibus/pcidev/pcifn (0)-> error.xmits.cpu.berr@cpu; prop fault.io.pci.device-interr@hostbridge/pcibus/pcidev[fromdev]/pcifn (0)-> error.io.xmits.pbm.tto@hostbridge/pcibus/pcidev/pcifn { fromdev == todev && fromdev != 32 }; prop error.io.xmits.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)-> ereport.io.xmits.pbm.tto@PCI_HB_DEV_PATH, ereport.io.xmits.pbm.s-tto@PCI_HB_DEV_PATH; prop error.io.xmits.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)-> ereport.io.xmits.bu@PCI_HB_DEV_PATH; prop error.io.xmits.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)-> error.io.xmits.pbm.target-tto@hostbridge/pcibus/pcidev/pcifn; prop error.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn (0)-> ereport.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn; prop error.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn (1)-> error.io.xmits.pbm.target-tto@pcibus/pcidev/pcifn/pcibus<>/pcidev<>/pcifn<>; /* * Need to add the following xmits specific propagations to complete the PCI * fault tree. These are to allow propagations to secondary errors and cpu * bus errors, and to represent the way the chip can raise both rserr and sserr * on detection of SERR# */ prop error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn (0)-> ereport.io.xmits.pbm.s-ma@PCI_HB_DEV_PATH; prop error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn (0)-> ereport.io.xmits.pbm.s-rta@PCI_HB_DEV_PATH; prop error.io.pci.perr-dw-u@hostbridge/pcibus/pcidev/pcifn (0)-> ereport.io.xmits.pbm.s-mdpe@PCI_HB_DEV_PATH; prop error.io.pci.perr-pw-u@hostbridge/pcibus/pcidev/pcifn (0)-> ereport.io.xmits.pbm.s-mdpe@PCI_HB_DEV_PATH; prop error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn (0)-> ereport.io.xmits.pbm.s-mdpe@PCI_HB_DEV_PATH; prop error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn (0)-> error.xmits.cpu.berr@cpu; prop error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn (0)-> error.xmits.cpu.berr@cpu; prop error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn (0)-> error.xmits.cpu.berr@cpu; prop error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn (1)-> ereport.io.pci.rserr@PCI_HB_DEV_PATH; prop error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn (0)-> ereport.io.pci.sserr@PCI_HB_DEV_PATH; prop error.xmits.cpu.berr@cpu (1)-> ereport.cpu.ultraSPARC-III.berr@cpu, ereport.cpu.ultraSPARC-IIIplus.berr@cpu, ereport.cpu.ultraSPARC-IV.berr@cpu, ereport.cpu.ultraSPARC-IVplus.berr@cpu; event error.io.xmits.ecc.drue@hostbridge; event ereport.io.xmits.ecc.drue@hostbridge{within(5s)}; event ereport.io.xmits.nodiag@hostbridge; /* * Upset used to hide ereports that can not be currently diagnosed. * * The drue error can cause a target abort to be sent onto the * pci bus in response to a dma request. We represent this using a device-ta * error to propagate into the generic pci.esc rules. */ engine serd.io.xmits.nodiag@hostbridge, N=1000, T=1hour, method=persistent, trip=ereport.io.xmits.nodiag@hostbridge; event upset.io.xmits.nodiag@hostbridge, engine=serd.io.xmits.nodiag@hostbridge; prop upset.io.xmits.nodiag@hostbridge (0)-> ereport.io.xmits.ecc.s-pce@hostbridge, error.io.xmits.ecc.drue@hostbridge, ereport.io.xmits.nodiag@hostbridge; prop error.io.xmits.ecc.drue@hostbridge (1)-> ereport.io.xmits.ecc.drue@hostbridge; prop error.io.xmits.ecc.drue@hostbridge (0)-> error.io.pci.device-ta@PCI_HB_DEV_PATH;