#
# Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
# Use is subject to license terms.
#
# CDDL HEADER START
#
# The contents of this file are subject to the terms of the
# Common Development and Distribution License (the "License").
# You may not use this file except in compliance with the License.
#
# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
# or http://www.opensolaris.org/os/licensing.
# See the License for the specific language governing permissions
# and limitations under the License.
#
# When distributing Covered Code, include this CDDL HEADER in each
# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
# If applicable, add the following below this CDDL HEADER, with the
# fields enclosed by brackets "[]" replaced with your own identifying
# information: Portions Copyright [yyyy] [name of copyright owner]
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# CDDL HEADER END
#
#ident	"%Z%%M%	%I%	%E% SMI"
#
# DO NOT EDIT -- this file is generated by the Event Registry.
#

FMDICT: name=SUN4V version=1 maxkey=3 dictid=0x3456

fault.cpu.ultraSPARC-T1.ireg=1
fault.cpu.ultraSPARC-T1.freg=2
fault.cpu.ultraSPARC-T1.itlb=3
fault.cpu.ultraSPARC-T1.dtlb=4
fault.cpu.ultraSPARC-T1.icache=5
fault.cpu.ultraSPARC-T1.dcache=6
fault.cpu.ultraSPARC-T1.mau=7
fault.cpu.ultraSPARC-T1.l2cachedata=8
fault.cpu.ultraSPARC-T1.l2cachetag=9
fault.cpu.ultraSPARC-T1.l2cachectl=10
fault.memory.page=11
fault.memory.dimm=12
fault.memory.bank=13
fault.memory.link-c=14
fault.cpu.ultraSPARC-T2.ireg=15
fault.cpu.ultraSPARC-T2.freg=16
fault.cpu.ultraSPARC-T2.misc_reg=17
fault.cpu.ultraSPARC-T2.itlb=18
fault.cpu.ultraSPARC-T2.dtlb=19
fault.cpu.ultraSPARC-T2.icache=20
fault.cpu.ultraSPARC-T2.dcache=21
fault.cpu.ultraSPARC-T2.mau=22
fault.cpu.ultraSPARC-T2.l2data-c=23
fault.cpu.ultraSPARC-T2.l2cachetag=24
fault.cpu.ultraSPARC-T2.l2cachectl=25
fault.memory.link-u=26
fault.cpu.ultraSPARC-T2.l2data-u=27
fault.cpu.ultraSPARC-T1.l2data-c=28
fault.cpu.ultraSPARC-T1.l2data-u=29
fault.memory.datapath=30
fault.io.n2.ncu=31
fault.io.n2.dmu=32
fault.io.n2.niu=33
fault.io.n2.siu=34
fault.io.n2.soc=35
fault.io.n2.crossbar=36
fault.io.fire.fw-epkt fault.io.fire.sw-epkt fault.io.fire.sw-fw-mismatch=37
fault.io.vf.ncx=38
fault.memory.link-f=39
fault.cpu.ultraSPARC-T2plus.ireg=40
fault.cpu.ultraSPARC-T2plus.freg=41
fault.cpu.ultraSPARC-T2plus.misc_reg=42
fault.cpu.ultraSPARC-T2plus.itlb=43
fault.cpu.ultraSPARC-T2plus.dtlb=44
fault.cpu.ultraSPARC-T2plus.icache=45
fault.cpu.ultraSPARC-T2plus.dcache=46
fault.cpu.ultraSPARC-T2plus.mau=47
fault.cpu.ultraSPARC-T2plus.l2data-c=48
fault.cpu.ultraSPARC-T2plus.l2cachetag=49
fault.cpu.ultraSPARC-T2plus.l2cachectl=50
fault.cpu.ultraSPARC-T2plus.l2data-u=51
fault.cpu.ultraSPARC-T2plus.lfu-f=52
fault.cpu.ultraSPARC-T2plus.lfu-p=53
fault.cpu.ultraSPARC-T2plus.lfu-u=54