'\" te
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.TH isalist 5 "20 Mar 2008" "SunOS 5.11" "Standards, Environments, and Macros"
.SH NAME
isalist \- the native instruction sets known to Solaris software
.SH DESCRIPTION
.sp
.LP
The possible instruction set names returned by \fBisalist\fR(1) and the
\fBSI_ISALIST\fR command of \fBsysinfo\fR(2) are listed here.
.sp
.LP
The list is ordered within an instruction set family in the sense that later
names are generally faster then earlier names; note that this is in the reverse
order than listed by \fBisalist\fR(1) and \fBsysinfo\fR(2). In the following
list of values, numbered entries generally represent increasing performance;
lettered entries are either mutually exclusive or cannot be ordered.
.sp
.LP
This feature is obsolete and may be removed in a future version of Solaris. The
lists below do not reflect all the extensions that have been made by modern
processors. See \fBgetisax\fR(2) for a better way to handle instruction set
extensions.
.SS "SPARC Platforms"
.sp
.LP
Where appropriate, correspondence with a given value of the \fB-xarch\fR option
of Sun's C 4.0 compiler is indicated. Other compilers might have similar
options.
.sp
.ne 2
.mk
.na
\fB1a. \fBsparc\fR\fR
.ad
.RS 27n
.rt  
Indicates the SPARC V8 instruction set, as defined in \fI\fR The SPARC
Architecture Manual, Version 8, Prentice-Hall, Inc., 1992. Some instructions
(such as integer multiply and divide, FSMULD, and all floating point operations
on quad operands) can be emulated by the kernel on certain systems.
.RE

.sp
.ne 2
.mk
.na
\fB1b. \fBsparcv7\fR\fR
.ad
.RS 27n
.rt  
Same as sparc. This corresponds to code produced with the -xarch=v7 option of
Sun's C 4.0 compiler.
.RE

.sp
.ne 2
.mk
.na
\fB2. \fBsparcv8-fsmuld\fR\fR
.ad
.RS 27n
.rt  
Like sparc, except that integer multiply and divide must be executed in
hardware. This corresponds to code produced with the -xarch=v8a option of Sun's
C 4.0 compiler.
.RE

.sp
.ne 2
.mk
.na
\fB3. \fBsparcv8\fR\fR
.ad
.RS 27n
.rt  
Like sparcv8-fsmuld, except that FSMULD must also be executed in hardware. This
corresponds to code produced with the -xarch=v8 option of Sun's C 4.0 compiler.
.RE

.sp
.ne 2
.mk
.na
\fB4. \fBsparcv8plus\fR\fR
.ad
.RS 27n
.rt  
Indicates the SPARC V8 instruction set plus those instructions in the SPARC V9
instruction set, as defined in \fI\fR The SPARC Architecture Manual, Version 9,
Prentice-Hall, 1994, that can be used according to \fI\fR The V8+ Technical
Specification. This corresponds to code produced with the -xarch=v8plus option
of Sun's C 4.0 compiler.
.RE

.sp
.ne 2
.mk
.na
\fB5a. \fBsparcv8plus+vis\fR\fR
.ad
.RS 27n
.rt  
Like sparcv8plus, with the addition of those UltraSPARC I Visualization
Instructions that can be used according to \fI\fR The V8+ Technical
Specification. This corresponds to code produced with the -xarch=v8plusa option
of Sun's C 4.0 compiler.
.RE

.sp
.ne 2
.mk
.na
\fB5b. \fBsparcv8plus+fmuladd\fR\fR
.ad
.RS 27n
.rt  
Like sparcv8plus, with the addition of the Fujitsu SPARC64 floating
multiply-add and multiply-subtract instructions.
.RE

.sp
.ne 2
.mk
.na
\fB6. \fBsparcv9\fR\fR
.ad
.RS 27n
.rt  
Indicates the SPARC V9 instruction set, as defined in \fI\fR The SPARC
Architecture Manual, Version 9, Prentice-Hall, 1994.
.RE

.sp
.ne 2
.mk
.na
\fB7a. \fBsparcv9+vis\fR\fR
.ad
.RS 27n
.rt  
Like sparcv9, with the addition of the UltraSPARC I Visualization Instructions.
.RE

.sp
.ne 2
.mk
.na
\fB7b. \fBsparcv9+vis2\fR\fR
.ad
.RS 27n
.rt  
Like sparcv9, with the addition of the UltraSPARC III Visualization
Instructions.
.RE

.sp
.ne 2
.mk
.na
\fB7c. \fBsparcv9+fmuladd\fR\fR
.ad
.RS 27n
.rt  
Like sparcv9, with the addition of the Fujitsu SPARC64 floating multiply-add
and multiply-subtract instructions.
.RE

.SS "x86 Platforms"
.sp
.ne 2
.mk
.na
\fB1. \fBi386\fR\fR
.ad
.RS 22n
.rt  
The Intel 80386 instruction set, as described in \fI\fR The i386 Microprocessor
Programmer's Reference Manual.
.RE

.sp
.ne 2
.mk
.na
\fB2. \fBi486\fR\fR
.ad
.RS 22n
.rt  
The Intel 80486 instruction set, as described in \fI\fR The i486 Microprocessor
Programmer's Reference Manual. (This is effectively i386, plus the CMPXCHG,
BSWAP, and XADD instructions.)
.RE

.sp
.ne 2
.mk
.na
\fB3. \fBpentium\fR\fR
.ad
.RS 22n
.rt  
The Intel Pentium instruction set, as described in \fI\fR The Pentium Processor
User's Manual. (This is effectively i486, plus the CPU_ID instruction, and any
features that the CPU_ID instruction indicates are present.)
.RE

.sp
.ne 2
.mk
.na
\fB4. \fBpentium+mmx\fR\fR
.ad
.RS 22n
.rt  
Like pentium, with the MMX instructions guaranteed present.
.RE

.sp
.ne 2
.mk
.na
\fB5. \fBpentium_pro\fR\fR
.ad
.RS 22n
.rt  
The Intel PentiumPro instruction set, as described in \fI\fR The PentiumPro
Family Developer's Manual. (This is effectively pentium, with the CMOVcc,
FCMOVcc, FCOMI, and RDPMC instructions guaranteed present.)
.RE

.sp
.ne 2
.mk
.na
\fB6. \fBpentium_pro+mmx\fR\fR
.ad
.RS 22n
.rt  
Like pentium_pro, with the MMX instructions guaranteed present.
.RE

.sp
.ne 2
.mk
.na
\fB7. \fBamd64\fR\fR
.ad
.RS 22n
.rt  
The AMD Opteron instruction set, as described in the \fIAMD64 Architecture
Programmer's Manual\fR.
.RE

.SH SEE ALSO
.sp
.LP
\fBisalist\fR(1), \fBgetisax\fR(2), \fBsysinfo\fR(2)