/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
 * or http://www.opensolaris.org/os/licensing.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */
/*
 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#pragma ident	"%Z%%M%	%I%	%E% SMI"

#pragma dictionary "SUN4U"

#define	HB_FIT		1000
#define HBUS_FIT	1000
#define PCI_BUS_FIT	500
#define PCI_DEV_FIT	1000
#define	CPU_FIT		500

#define	PCI_HB_DEV_PATH hostbridge/pcibus/pcidev[32]/pcifn[0]

fru hostbridge;
asru hostbridge;

event fault.io.tomatillo@hostbridge,
    FITrate=HB_FIT, FRU=hostbridge, ASRU=hostbridge;

event error.io.tom.jbus.um@hostbridge;
event error.io.tom.jbus.to@hostbridge;
event error.io.tom.jbus.bus@hostbridge;
event error.io.tom.jbus.iis@hostbridge;
event error.io.tom.mmu.inval@hostbridge/pcibus;
event error.io.tom.mmu.prot@hostbridge/pcibus;
event error.io.tom.mmu.bva@hostbridge/pcibus;
event error.io.tom.mmu.btt@hostbridge/pcibus;
event error.io.pci.device-ta@hostbridge/pcibus/pcidev/pcifn;

event ereport.io.tom.jbus.um@hostbridge{within(5s)};
event ereport.io.tom.jbus.to@hostbridge{within(5s)};
event ereport.io.tom.jbus.bus@hostbridge{within(5s)};
event ereport.io.tom.jbus.to-exp@hostbridge{within(5s)};
event ereport.io.tom.jbus.iis@hostbridge{within(5s)};
event ereport.io.tom.mmu.btt@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.mmu.bva@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.mmu.prot@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.mmu.inval@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.jbus.srds@hostbridge{within(5s)};
event ereport.io.tom.jbus.srdsa@hostbridge{within(5s)};
event ereport.io.tom.jbus.sown@hostbridge{within(5s)};
event ereport.io.tom.jbus.srdo@hostbridge{within(5s)};

/*
 * A faulty Tomatillo hostbridge may cause:
 *
 *  - um:	jbus unmapped address error.
 *  - to:	jbus timeout.
 *  - bus:	jbus bus error.
 *  - iis:	illegal coherency install state error.
 *  - inval:	iommu invalid entry error.
 *  - prot:	iommu protection error, attempted to write a read-only page.
 *  - bva:	iommu bad virtual address, address out of range.
 *  - btt:	iommu bad tsb size tbw size combination.
 *  - srds:	snoop error due to own RDS hitting cache line in S, O or M.
 *  - srdsa:	snoop error due to own RDSA hitting cache line in S, O or M.
 *  - sown:	snoop error due to own OWN hitting cache line in S or M.
 *  - srdo:	snoop error due to own RDO hitting cache line in O or M.
 *
 * The um, to, bus, btt, inval, prot and bva errors can cause a target abort to
 * be sent onto the pci bus in response to a dma request. We represent this
 * using a device-ta error to propagate into the generic pci.esc rules.
 */
prop fault.io.tomatillo@hostbridge (0)->
    error.io.tom.jbus.um@hostbridge,
    error.io.tom.jbus.to@hostbridge,
    error.io.tom.jbus.bus@hostbridge,
    error.io.tom.jbus.iis@hostbridge,
    error.io.tom.mmu.inval@hostbridge/pcibus,
    error.io.tom.mmu.prot@hostbridge/pcibus,
    error.io.tom.mmu.bva@hostbridge/pcibus,
    error.io.tom.mmu.btt@hostbridge/pcibus,
    ereport.io.tom.jbus.srds@hostbridge,
    ereport.io.tom.jbus.srdsa@hostbridge,
    ereport.io.tom.jbus.sown@hostbridge,
    ereport.io.tom.jbus.srdo@hostbridge;

prop error.io.tom.jbus.um@hostbridge (1)->
    ereport.io.tom.jbus.um@hostbridge;

prop error.io.tom.jbus.um@hostbridge (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

prop error.io.tom.jbus.to@hostbridge (1)->
    ereport.io.tom.jbus.to@hostbridge,
    ereport.io.tom.jbus.to-exp@hostbridge;

prop error.io.tom.jbus.to@hostbridge (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

prop error.io.tom.jbus.bus@hostbridge (1)->
    ereport.io.tom.jbus.bus@hostbridge;

prop error.io.tom.jbus.bus@hostbridge (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

prop error.io.tom.jbus.iis@hostbridge (1)->
    ereport.io.tom.jbus.iis@hostbridge;

prop error.io.tom.mmu.btt@hostbridge/pcibus (1)->
    ereport.io.tom.mmu.btt@PCI_HB_DEV_PATH;

prop error.io.tom.mmu.btt@hostbridge/pcibus (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH,
    error.io.tom.mmu.inval@hostbridge/pcibus;

prop error.io.tom.mmu.inval@hostbridge/pcibus (1)->
    ereport.io.tom.mmu.inval@PCI_HB_DEV_PATH;

prop error.io.tom.mmu.inval@hostbridge/pcibus (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

prop error.io.tom.mmu.prot@hostbridge/pcibus (1)->
    ereport.io.tom.mmu.prot@PCI_HB_DEV_PATH;

prop error.io.tom.mmu.prot@hostbridge/pcibus (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

prop error.io.tom.mmu.bva@hostbridge/pcibus (1)->
    ereport.io.tom.mmu.bva@PCI_HB_DEV_PATH;

prop error.io.tom.mmu.bva@hostbridge/pcibus (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

fru cpu;

event fault.io.datapath@cpu, FITrate=CPU_FIT, FRU=cpu, retire=0;

event error.io.tom.jbus.ibe@hostbridge;

event ereport.io.tom.jbus.ibe@hostbridge{within(5s)};
event ereport.io.tom.jbus.srd@hostbridge{within(5s)};
event ereport.io.tom.jbus.bc@hostbridge{within(5s)};

/*
 * A faulty CPU may cause:
 *
 *  - to:	jbus timeout error.
 *  - bus:	jbus bus error.
 *  - ibe:	illegal byte enable error.
 *  - iis:	illegal coherency install state error.
 *  - um:	jbus unmapped error.
 *  - srd:	foreign RD hitting cache line in S, O or M.
 *  - bc:	bad jbus command.
 *
 * The ibe error can cause a target abort to
 * be sent onto the pci bus in response to a dma request. We represent this
 * using a device-ta error to propagate into the generic pci.esc rules.
 */
prop fault.io.datapath@cpu (0)->
    error.io.tom.jbus.to@hostbridge,
    error.io.tom.jbus.bus@hostbridge,
    error.io.tom.jbus.ibe@hostbridge,
    error.io.tom.jbus.iis@hostbridge,
    error.io.tom.jbus.um@hostbridge,
    ereport.io.tom.jbus.srd@hostbridge,
    ereport.io.tom.jbus.bc@hostbridge;

prop error.io.tom.jbus.ibe@hostbridge (1)->
    ereport.io.tom.jbus.ibe@hostbridge;

prop error.io.tom.jbus.ibe@hostbridge (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

event fault.io.hbus@hostbridge,
    FITrate=HBUS_FIT, FRU=hostbridge, ASRU=hostbridge;

event error.io.tom.jbus.drpe@hostbridge;
event ereport.io.tom.jbus.ape@hostbridge{within(5s)};
event ereport.io.tom.jbus.pwpe@hostbridge{within(5s)};
event ereport.io.tom.jbus.drpe@hostbridge{within(5s)};
event ereport.io.tom.jbus.dwpe@hostbridge{within(5s)};
event ereport.io.tom.jbus.cpe@hostbridge{within(5s)};

/*
 * A faulty host bus may cause:
 *
 *  - ape:	jbus address parity error.
 *  - pwpe:	jbus PIO write parity error.
 *  - drpe:	jbus DMA read parity error.
 *  - dwpe:	jbus DMA write parity error.
 *  - cpe:	jbus control parity error.
 *
 * The drpe error can cause a target abort to
 * be sent onto the pci bus in response to a dma request. We represent this
 * using a device-ta error to propagate into the generic pci.esc rules.
 */
prop fault.io.hbus@hostbridge(0)->
    ereport.io.tom.jbus.ape@hostbridge,
    ereport.io.tom.jbus.pwpe@hostbridge,
    error.io.tom.jbus.drpe@hostbridge,
    ereport.io.tom.jbus.dwpe@hostbridge,
    ereport.io.tom.jbus.cpe@hostbridge;

prop error.io.tom.jbus.drpe@hostbridge(1)->
    ereport.io.tom.jbus.drpe@hostbridge;

prop error.io.tom.jbus.drpe@hostbridge(0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

fru pcibus/pcidev;
asru pcibus/pcidev/pcifn;

event fault.io.pci.device-interr@hostbridge/pcibus/pcidev/pcifn,
    FITrate=PCI_DEV_FIT, FRU=pcibus/pcidev, ASRU=pcibus/pcidev/pcifn;

event fault.io.pci.device-interr@pcibus/pcidev/pcifn,
    FITrate=PCI_DEV_FIT, FRU=pcibus/pcidev, ASRU=pcibus/pcidev/pcifn;

event error.io.tom.pbm.rl@hostbridge/pcibus/pcidev/pcifn;
event error.io.tom.pbm.rl@pcibus/pcidev/pcifn;
event error.io.tom.pbm.rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn;
event error.io.tom.pbm.target-rl@pcibus/pcidev/pcifn;
event error.io.tom.pbm.target-rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn;
event error.io.tom.pbm.tto@hostbridge/pcibus/pcidev/pcifn;
event error.io.tom.pbm.target-tto@hostbridge/pcibus/pcidev/pcifn;
event error.io.tom.pbm.target-tto@pcibus/pcidev/pcifn;
event error.io.tom.pbm.target-tto@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn;
event error.tom.cpu.berr@cpu;
event error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.perr-pw-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.perr-dw-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn;
event error.io.pci.retry-to-d@hostbridge/pcibus/pcidev/pcifn;

event ereport.io.tom.pbm.tto@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.pbm.rl@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.pbm.s-tto@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.pbm.s-rl@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.pbm.s-ma@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.pbm.s-rta@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.pbm.s-mdpe@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.pbm.target-tto@pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.pbm.target-rl@pcibus/pcidev/pcifn{within(5s)};
event ereport.io.pci.rserr@hostbridge/pcibus/pcidev/pcifn{within(5s)};

/*
 * A faulty PCI device may cause:
 *
 *  - rl:	it to exceed the limit on retrying a transaction.
 *  - tto:	it to not assert trdy# within the set timeout.
 *
 * For rl and tto, there may be a target- ereport on a child device. For rl,
 * there may also be an associated dto - the retry-to-d error propagates into
 * the pci.esc rules to handle this.
 */
prop fault.io.pci.device-interr@pcibus/pcidev[fromdev]/pcifn (0)->
    error.io.tom.pbm.rl@pcibus/pcidev<todev>/pcifn {
	fromdev == todev && fromdev != 32 },
    error.io.tom.pbm.target-rl@pcibus/pcidev<todev>/pcifn {
	fromdev == todev && fromdev != 32 };

prop error.io.tom.pbm.rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn (1)->
    error.io.tom.pbm.rl@pcibus/pcidev/pcifn;

prop error.io.tom.pbm.rl@hostbridge/pcibus/pcidev/pcifn (1)->
    ereport.io.tom.pbm.rl@PCI_HB_DEV_PATH,
    ereport.io.tom.pbm.s-rl@PCI_HB_DEV_PATH;

prop error.io.tom.pbm.target-rl@pcibus/pcidev/pcifn (1)->
    error.io.tom.pbm.target-rl@pcibus/pcidev/pcifn/pcibus<>/pcidev<>/pcifn<>;

prop error.io.tom.pbm.target-rl@pcibus/pcidev/pcifn (0)->
    ereport.io.tom.pbm.target-rl@pcibus/pcidev/pcifn;

prop error.io.tom.pbm.rl@hostbridge/pcibus/pcidev/pcifn (0)->
    error.tom.cpu.berr@cpu;

prop error.io.tom.pbm.rl@hostbridge/pcibus/pcidev/pcifn (0)->
    error.io.pci.retry-to-d@hostbridge/pcibus/pcidev/pcifn;

prop fault.io.pci.device-interr@hostbridge/pcibus/pcidev[fromdev]/pcifn (0)->
    error.io.tom.pbm.tto@hostbridge/pcibus/pcidev<todev>/pcifn {
	fromdev == todev && fromdev != 32};

prop error.io.tom.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)->
    ereport.io.tom.pbm.tto@PCI_HB_DEV_PATH,
    ereport.io.tom.pbm.s-tto@PCI_HB_DEV_PATH;

prop error.io.tom.pbm.tto@hostbridge/pcibus/pcidev/pcifn (1)->
    error.io.tom.pbm.target-tto@hostbridge/pcibus/pcidev/pcifn;

prop error.io.tom.pbm.target-tto@pcibus/pcidev/pcifn (0)->
    ereport.io.tom.pbm.target-tto@pcibus/pcidev/pcifn;

prop error.io.tom.pbm.target-tto@pcibus/pcidev/pcifn (1)->
    error.io.tom.pbm.target-tto@pcibus/pcidev/pcifn/pcibus<>/pcidev<>/pcifn<>;

/*
 * Need to add the following tomatillo specific propagations to complete the
 * fault tree. These are to allow propagations to secondary errors and cpu
 * bus errors, and to represent the way the chip raises rserr
 * on detection of SERR#
 */
prop error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.tom.pbm.s-ma@PCI_HB_DEV_PATH;

prop error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.tom.pbm.s-rta@PCI_HB_DEV_PATH;

prop error.io.pci.perr-pw-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.tom.pbm.s-mdpe@PCI_HB_DEV_PATH;

prop error.io.pci.perr-dw-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.tom.pbm.s-mdpe@PCI_HB_DEV_PATH;

prop error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.tom.pbm.s-mdpe@PCI_HB_DEV_PATH;

prop error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn (0)->
    error.tom.cpu.berr@cpu;

prop error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn (0)->
    error.tom.cpu.berr@cpu;

prop error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn (0)->
    error.tom.cpu.berr@cpu;

prop error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn (1)->
    ereport.io.pci.rserr@PCI_HB_DEV_PATH;

event ereport.cpu.ultraSPARC-IIIi.berr@cpu{within(5s)};

prop error.tom.cpu.berr@cpu (1)->
    ereport.cpu.ultraSPARC-IIIi.berr@cpu;

/*
 * A bad request from a downstream device/driver may cause
 *
 *  - inval:	iommu invalid entry error.
 *  - prot:	iommu protection error, attempted to write a read-only page.
 *  - bva:	iommu bad virtual address, address out of range.
 *  - btt:	iommu bad tsb size tbw size combination.
 */
event error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn;

prop error.io.pci.badreq-pw-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.tom.mmu.inval@PCI_HB_DEV_PATH,
    ereport.io.tom.mmu.prot@PCI_HB_DEV_PATH,
    ereport.io.tom.mmu.bva@PCI_HB_DEV_PATH,
    ereport.io.tom.mmu.btt@PCI_HB_DEV_PATH;

event error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn;

prop error.io.pci.badreq-drw-u@hostbridge/pcibus/pcidev/pcifn (0)->
    ereport.io.tom.mmu.inval@PCI_HB_DEV_PATH,
    ereport.io.tom.mmu.prot@PCI_HB_DEV_PATH,
    ereport.io.tom.mmu.bva@PCI_HB_DEV_PATH,
    ereport.io.tom.mmu.btt@PCI_HB_DEV_PATH;

event error.io.tom.ecc.drue@hostbridge;
event error.io.tom.mmu.ue@hostbridge/pcibus;
event error.io.tom.mmu.to@hostbridge/pcibus;
event ereport.io.tom.jbus.sgr@hostbridge{within(5s)};
event ereport.io.tom.jbus.spci@hostbridge{within(5s)};
event ereport.io.tom.jbus.snp@hostbridge{within(5s)};
event ereport.io.tom.ecc.drue@hostbridge{within(5s)};
event ereport.io.tom.mmu.ue@hostbridge/pcibus/pcidev/pcifn{within(5s)};
event ereport.io.tom.mmu.to@hostbridge/pcibus/pcidev/pcifn{within(5s)};

event ereport.io.tom.nodiag@hostbridge;

/*
 * Upset used to hide ereports that can not be currently diagnosed.
 *
 * The ue, to and drue errors can cause a target abort to
 * be sent onto the pci bus in response to a dma request. We represent this
 * using a device-ta error to propagate into the generic pci.esc rules.
 */
engine serd.io.tom.nodiag@hostbridge,
    N=1000, T=1hour, method=persistent,
    trip=ereport.io.tom.nodiag@hostbridge;

event upset.io.tom.nodiag@hostbridge,
    engine=serd.io.tom.nodiag@hostbridge;

prop upset.io.tom.nodiag@hostbridge (0)->
    ereport.io.tom.jbus.sgr@hostbridge,
    ereport.io.tom.jbus.spci@hostbridge,
    ereport.io.tom.jbus.snp@hostbridge,
    ereport.io.tom.nodiag@hostbridge;

prop upset.io.tom.nodiag@hostbridge (0)->
    error.io.tom.ecc.drue@hostbridge,
    error.io.tom.mmu.to@hostbridge/pcibus,
    error.io.tom.mmu.ue@hostbridge/pcibus;

prop error.io.tom.mmu.ue@hostbridge/pcibus (1)->
    ereport.io.tom.mmu.ue@PCI_HB_DEV_PATH;

prop error.io.tom.mmu.ue@hostbridge/pcibus (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

prop error.io.tom.mmu.to@hostbridge/pcibus (1)->
    ereport.io.tom.mmu.to@PCI_HB_DEV_PATH;

prop error.io.tom.mmu.to@hostbridge/pcibus (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;

prop error.io.tom.ecc.drue@hostbridge (1)->
    ereport.io.tom.ecc.drue@hostbridge;

prop error.io.tom.ecc.drue@hostbridge (0)->
    error.io.pci.device-ta@PCI_HB_DEV_PATH;