#
# CDDL HEADER START
#
# The contents of this file are subject to the terms of the
# Common Development and Distribution License (the "License").
# You may not use this file except in compliance with the License.
#
# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
# or http://www.opensolaris.org/os/licensing.
# See the License for the specific language governing permissions
# and limitations under the License.
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# When distributing Covered Code, include this CDDL HEADER in each
# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
# If applicable, add the following below this CDDL HEADER, with the
# fields enclosed by brackets "[]" replaced with your own identifying
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# Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
# Use is subject to license terms.
#

#ident	"%Z%%M%	%I%	%E% SMI"

one hci1394_state_s

### HAL interface entry points
root hci1394_s1394if_shutdown
root hci1394_s1394if_phy
root hci1394_s1394if_read
root hci1394_s1394if_read_response
root hci1394_s1394if_write
root hci1394_s1394if_write_response
root hci1394_s1394if_response_complete
root hci1394_s1394if_lock
root hci1394_s1394if_lock_response
root hci1394_alloc_isoch_dma
root hci1394_free_isoch_dma
root hci1394_start_isoch_dma
root hci1394_stop_isoch_dma
root hci1394_update_isoch_dma
root hci1394_s1394if_update_config_rom
root hci1394_s1394if_reset_bus
root hci1394_s1394if_short_bus_reset
root hci1394_s1394if_set_contender_bit
root hci1394_s1394if_set_root_holdoff_bit
root hci1394_s1394if_set_gap_count
root hci1394_s1394if_csr_read
root hci1394_s1394if_csr_write
root hci1394_s1394if_csr_cswap32
root hci1394_s1394if_phy_filter_set
root hci1394_s1394if_phy_filter_clr
root hci1394_s1394if_power_state_change

### timeout callbacks
root hci1394_async_pending_timeout

### currently unused functions
root hci1394_isoch_resume
root hci1394_ixl_set_start
root hci1394_ohci_arreq_stop
root hci1394_ohci_arresp_stop
root hci1394_ohci_link_disable
root hci1394_ohci_phy_clr

add h1394_lock_request/recv_lock_req targets s1394_send_response
add h1394_read_request/recv_read_req targets s1394_send_response
add h1394_write_request/recv_write_req targets s1394_send_response

add s1394_hal_s::halinfo.hal_events.response_complete targets \
	hci1394_s1394if_response_complete
add s1394_hal_s::halinfo.hal_events.set_contender_bit targets \
	hci1394_s1394if_set_contender_bit

### hci1394 callbacks
add hci1394_ixl_dma_sync/callback targets warlock_dummy
add hci1394_iso_ctxt_s::isoch_dma_stopped targets warlock_dummy

add hci1394_tlist_s::tl_timer_info.tlt_callback targets \
	hci1394_async_pending_timeout
add hci1394_q_s::q_info.qi_start targets hci1394_async_arreq_start \
	hci1394_async_arresp_start hci1394_async_atreq_start \
	hci1394_async_atresp_start 
add hci1394_q_s::q_info.qi_wake targets hci1394_async_arreq_wake \
	hci1394_async_arresp_wake hci1394_async_atreq_wake \
	hci1394_async_atresp_wake 

# CMP/FCP
add s1394_cmp_notify_reg_change/cb target warlock_dummy
add s1394_fcp_recv_write_request/cb target warlock_dummy

add h1394_read_request/recv_read_req target s1394_cmp_ompr_recv_read_request
add h1394_lock_request/recv_lock_req target s1394_cmp_ompr_recv_lock_request
add h1394_read_request/recv_read_req target s1394_cmp_impr_recv_read_request
add h1394_lock_request/recv_lock_req target s1394_cmp_impr_recv_lock_request
add h1394_write_request/recv_write_req target s1394_fcp_resp_recv_write_request
add h1394_write_request/recv_write_req target s1394_fcp_cmd_recv_write_request

add bus_ops::bus_config targets warlock_dummy
add bus_ops::bus_unconfig targets warlock_dummy