[
    {
        "BriefDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]",
        "Counter": "0,1,2,3,4,5",
        "Deprecated": "1",
        "EventCode": "0xe4",
        "EventName": "LBR_INSERTS.ANY",
        "PEBS": "1",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0xB7",
        "EventName": "OCR.COREWB_M.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10008",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that have any type of response.",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores that have any type of response.",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0xB7",
        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10800",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state)",
        "Counter": "0,1,2,3,4,5",
        "EventCode": "0x75",
        "EventName": "SERIALIZATION.C01_MS_SCB",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    }
]